From: Pavel Machek <pavel@denx.de>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements
Date: Fri, 2 Feb 2024 12:45:41 +0100 [thread overview]
Message-ID: <ZbzV5bNL9qwCmQca@duo.ucw.cz> (raw)
In-Reply-To: <20240202113754.202827-1-biju.das.jz@bp.renesas.com>
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Hi!
> This patch series aims to improve versa3 clock driver.
>
> All the patches are cherry-picked from the mainline.
Series looks okay to me, I can apply it if there are no other comments
and if it passes testing.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2024-02-02 11:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 3/6] clk: versaclock3: Avoid unnecessary padding Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 4/6] clk: versaclock3: Use u8 return type for get_parent() callback Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 5/6] clk: versaclock3: Add missing space between ')' and '{' Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 6/6] clk: versaclock3: Drop ret variable Biju Das
2024-02-02 11:45 ` Pavel Machek [this message]
2024-02-02 12:08 ` [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements nobuhiro1.iwamatsu
2024-02-05 11:23 ` Pavel Machek
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