From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757229AbdERS3F (ORCPT ); Thu, 18 May 2017 14:29:05 -0400 Received: from mail-qk0-f194.google.com ([209.85.220.194]:34013 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754636AbdERS3B (ORCPT ); Thu, 18 May 2017 14:29:01 -0400 From: "Jingoo Han" To: "'Song Xiaowei'" , , , , , , , , Cc: , , , , , References: <20170515115523.126970-1-songxiaowei@hisilicon.com> In-Reply-To: <20170515115523.126970-1-songxiaowei@hisilicon.com> Subject: Re: [PATCH 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Date: Thu, 18 May 2017 14:28:57 -0400 Message-ID: <001801d2d004$9dfa7850$d9ef68f0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQGhP54TfRWBK/3lCIBNgwBvtpuorKJdiGdA Content-Language: ko Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, May 15, 2017 7:55 AM, Song Xiaowei wrote > > Hisilicon PCIe Driver shares the common functions fo PCIe dw-host > > The poweron functions is developed on hi3660 SoC, while Others Functions > are common for Kirin series SoCs. > > Lowpower(L1ss and SR), hotplug and MSI feature are not supported How about 'Low power mode', instead of 'Lowpower'? 'L1ss' is L1 sub state. Then, what is 'SR'? > currently. > > Cc: Guodong Xu > Signed-off-by: Song Xiaowei > --- > drivers/pci/dwc/Kconfig | 10 + > drivers/pci/dwc/Makefile | 1 + > drivers/pci/dwc/pcie-kirin.c | 522 > +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 533 insertions(+) > create mode 100644 drivers/pci/dwc/pcie-kirin.c > > diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig > index d2d2ba5b8a68..13e617b78430 100644 > --- a/drivers/pci/dwc/Kconfig > +++ b/drivers/pci/dwc/Kconfig > @@ -130,4 +130,14 @@ config PCIE_ARTPEC6 > Say Y here to enable PCIe controller support on Axis ARTPEC-6 > SoCs. This PCIe controller uses the DesignWare core. > > +config PCIE_KIRIN > + depends on OF && ARM64 > + bool "HiSilicon Kirin series SoCs PCIe controllers" > + depends on PCI > + select PCIEPORTBUS > + select PCIE_DW_HOST > + help > + Say Y here if you want PCIe controller support on HiSilicon Kirin > series SoCs > + kirin960 SoC > + > endmenu > diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile > index a2df13c28798..4bd69bacd4ab 100644 > --- a/drivers/pci/dwc/Makefile > +++ b/drivers/pci/dwc/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > # The following drivers are for devices that use the generic ACPI > # pci_root.c driver but don't support standard ECAM config access. > diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c > new file mode 100644 > index 000000000000..739f72dae16d > --- /dev/null > +++ b/drivers/pci/dwc/pcie-kirin.c > @@ -0,0 +1,522 @@ > +/* > + * PCIe host controller driver for Kirin Phone SoCs > + * > + * Copyright (C) 2015 Hilisicon Electronics Co., Ltd. You sent this patch to mailing list in '2017'. So, please use 2017, instead of 2015. > + * http://www.huawei.com > + * > + * Author: Xiaowei Song > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "pcie-designware.h" Please re-order these header files in alphabetical order for 'readability'. Best regards, Jingoo Han [....]