[PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits		1
 #define cpu_has_octeon_cache	1
 #define cpu_has_saa		octeon_has_saa()
-#define cpu_has_mips32r1	0
-#define cpu_has_mips32r2	0
-#define cpu_has_mips64r1	0
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	1
 #define cpu_has_mips64r2	1
 #define cpu_has_dsp		0
 #define cpu_has_dsp2		0
-- 
1.9.1

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com] 
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits		1
 #define cpu_has_octeon_cache	1
 #define cpu_has_saa		octeon_has_saa()
-#define cpu_has_mips32r1	0
-#define cpu_has_mips32r2	0
-#define cpu_has_mips64r1	0
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	1
 #define cpu_has_mips64r2	1
 #define cpu_has_dsp		0
 #define cpu_has_dsp2		0
-- 
1.9.1

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com] 
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits		1
 #define cpu_has_octeon_cache	1
 #define cpu_has_saa		octeon_has_saa()
-#define cpu_has_mips32r1	0
-#define cpu_has_mips32r2	0
-#define cpu_has_mips64r1	0
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	1
 #define cpu_has_mips64r2	1
 #define cpu_has_dsp		0
 #define cpu_has_dsp2		0
-- 
1.9.1

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

ping
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Wednesday, April 05, 2017 6:01 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; Petar Jovanovic
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com]
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits         1
 #define cpu_has_octeon_cache   1
 #define cpu_has_saa            octeon_has_saa()
-#define cpu_has_mips32r1       0
-#define cpu_has_mips32r2       0
-#define cpu_has_mips64r1       0
+#define cpu_has_mips32r1       1
+#define cpu_has_mips32r2       1
+#define cpu_has_mips64r1       1
 #define cpu_has_mips64r2       1
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0
--
1.9.1

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Can anyone take a look at this? Thank you.

-----Original Message-----
From: Petar Jovanovic [mailto:Petar.Jovanovic@imgtec.com] 
Sent: Tuesday, April 25, 2017 7:25 PM
To: Petar Jovanovic <petar.jovanovic@rt-rk.com>; linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Wednesday, April 05, 2017 6:01 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; Petar Jovanovic
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com]
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits         1
 #define cpu_has_octeon_cache   1
 #define cpu_has_saa            octeon_has_saa()
-#define cpu_has_mips32r1       0
-#define cpu_has_mips32r2       0
-#define cpu_has_mips64r1       0
+#define cpu_has_mips32r1       1
+#define cpu_has_mips32r2       1
+#define cpu_has_mips64r1       1
 #define cpu_has_mips64r2       1
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0
--
1.9.1

=

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Can anyone take a look at this? Thank you.

-----Original Message-----
From: Petar Jovanovic [mailto:Petar.Jovanovic@imgtec.com] 
Sent: Tuesday, April 25, 2017 7:25 PM
To: Petar Jovanovic <petar.jovanovic@rt-rk.com>; linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Wednesday, April 05, 2017 6:01 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; Petar Jovanovic
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com]
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits         1
 #define cpu_has_octeon_cache   1
 #define cpu_has_saa            octeon_has_saa()
-#define cpu_has_mips32r1       0
-#define cpu_has_mips32r2       0
-#define cpu_has_mips64r1       0
+#define cpu_has_mips32r1       1
+#define cpu_has_mips32r2       1
+#define cpu_has_mips64r1       1
 #define cpu_has_mips64r2       1
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0
--
1.9.1

=

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Anyone? This small change has been on the list for two months now.
Thanks in advance.
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Monday, May 08, 2017 5:25 PM
To: Petar Jovanovic; linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

Can anyone take a look at this? Thank you.

-----Original Message-----
From: Petar Jovanovic [mailto:Petar.Jovanovic@imgtec.com]
Sent: Tuesday, April 25, 2017 7:25 PM
To: Petar Jovanovic <petar.jovanovic@rt-rk.com>; linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Wednesday, April 05, 2017 6:01 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; Petar Jovanovic
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

ping.

-----Original Message-----
From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com]
Sent: Wednesday, March 15, 2017 6:59 PM
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org; david.daney@cavium.com; petar.jovanovic@imgtec.com;
Petar Jovanovic <petar.jovanovic@rt-rk.com>
Subject: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
---
 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bb..a4f7986 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits         1
 #define cpu_has_octeon_cache   1
 #define cpu_has_saa            octeon_has_saa()
-#define cpu_has_mips32r1       0
-#define cpu_has_mips32r2       0
-#define cpu_has_mips64r1       0
+#define cpu_has_mips32r1       1
+#define cpu_has_mips32r2       1
+#define cpu_has_mips64r1       1
 #define cpu_has_mips64r2       1
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0
--
1.9.1

=

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Maciej W. Rozycki]

On Mon, 15 May 2017, Petar Jovanovic wrote:

> Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
> mips64r1. This will affect show_cpuinfo() that will now correctly expose
> mips32r1, mips32r2 and mips64r1 as supported ISAs.

 I suspect it will affect more than just `show_cpuinfo', e.g. some inline 
asm, and you could have included a justification as to why this patch is 
correct, such as by referring to how `set_isa' sets flags in `isa_level'.  
Anyway it LGTM, so:

Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>

 Such problems pop up from time to time, so overall we probably want to 
have a consistency check with a BUG_ON or suchlike implemented somewhere, 
preferably once the console is running so that the kernel does not just 
silently hang without output, iterating over these macros and verifying 
against actual CPU info.

 HTH,

  Maciej

Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[David Daney]

On 05/20/2017 06:37 PM, Maciej W. Rozycki wrote:
> On Mon, 15 May 2017, Petar Jovanovic wrote:
> 
>> Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
>> mips64r1. This will affect show_cpuinfo() that will now correctly expose
>> mips32r1, mips32r2 and mips64r1 as supported ISAs.
> 
>   I suspect it will affect more than just `show_cpuinfo', e.g. some inline
> asm, and you could have included a justification as to why this patch is
> correct, such as by referring to how `set_isa' sets flags in `isa_level'.

That is correct, and exactly what I said in my reply to the patch when 
it was posted.  When the OCTEON code was merged, different code paths 
were taken in the kernel, and there was a deliberate decision to 
structure mach-cavium-octeon/cpu-feature-overrides.h the way we did it.

I also noted that the information exposed to userspace via /proc/cpuinfo 
should be represented in the kernel by a distinct mechanism from how the 
kernel makes internal decisions about CPU features.


> Anyway it LGTM, so:
> 
> Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
> 
>   Such problems pop up from time to time, so overall we probably want to
> have a consistency check with a BUG_ON or suchlike implemented somewhere,
> preferably once the console is running so that the kernel does not just
> silently hang without output, iterating over these macros and verifying
> against actual CPU info.
> 
>   HTH,
> 
>    Maciej
> 

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

-----Original Message-----
From: David Daney [mailto:ddaney@caviumnetworks.com] 
Sent: Monday, May 22, 2017 6:26 PM
To: Maciej W. Rozycki <macro@imgtec.com>; Petar Jovanovic <Petar.Jovanovic@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@rt-rk.com>; linux-mips@linux-mips.org; ralf@linux-mips.org; david.daney@cavium.com
Subject: Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

On 05/20/2017 06:37 PM, Maciej W. Rozycki wrote:
>>   I suspect it will affect more than just `show_cpuinfo', e.g. some inline
>> asm, and you could have included a justification as to why this patch is
>> correct, such as by referring to how `set_isa' sets flags in `isa_level'.

> That is correct, and exactly what I said in my reply to the patch when 
> it was posted.  When the OCTEON code was merged, different code paths 
> were taken in the kernel, and there was a deliberate decision to 
> structure mach-cavium-octeon/cpu-feature-overrides.h the way we did it.

In the current ToT, I have not seen where this change would affect apart
from show_cpuinfo(). I understood from your words it was different at the
time when the original patch was added.

Petar

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

-----Original Message-----
From: David Daney [mailto:ddaney@caviumnetworks.com] 
Sent: Monday, May 22, 2017 6:26 PM
To: Maciej W. Rozycki <macro@imgtec.com>; Petar Jovanovic <Petar.Jovanovic@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@rt-rk.com>; linux-mips@linux-mips.org; ralf@linux-mips.org; david.daney@cavium.com
Subject: Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

On 05/20/2017 06:37 PM, Maciej W. Rozycki wrote:
>>   I suspect it will affect more than just `show_cpuinfo', e.g. some inline
>> asm, and you could have included a justification as to why this patch is
>> correct, such as by referring to how `set_isa' sets flags in `isa_level'.

> That is correct, and exactly what I said in my reply to the patch when 
> it was posted.  When the OCTEON code was merged, different code paths 
> were taken in the kernel, and there was a deliberate decision to 
> structure mach-cavium-octeon/cpu-feature-overrides.h the way we did it.

In the current ToT, I have not seen where this change would affect apart
from show_cpuinfo(). I understood from your words it was different at the
time when the original patch was added.

Petar

Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Maciej W. Rozycki]

On Mon, 22 May 2017, David Daney wrote:

> >   I suspect it will affect more than just `show_cpuinfo', e.g. some inline
> > asm, and you could have included a justification as to why this patch is
> > correct, such as by referring to how `set_isa' sets flags in `isa_level'.
> 
> That is correct, and exactly what I said in my reply to the patch when it was
> posted.  When the OCTEON code was merged, different code paths were taken in
> the kernel, and there was a deliberate decision to structure
> mach-cavium-octeon/cpu-feature-overrides.h the way we did it.
> 
> I also noted that the information exposed to userspace via /proc/cpuinfo
> should be represented in the kernel by a distinct mechanism from how the
> kernel makes internal decisions about CPU features.

 Explicit checks for Octeon should then be used instead in the individual 
pieces of code affected, e.g.:

	if (cpu_has_mips32r1 && !cpu_mach_octeon)

or suchlike, possibly with an explanatory comment as to why such an 
exclusion has been made.  The `cpu_has_mips32r1', etc. macros are supposed 
to be generic architectural checks.

 Also any design decisions should have been noted in the description of 
the original commit.

  Maciej

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Can this change be applied now?

Thanks.

Regards,
Petar

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Can this change be applied now?

Thanks.

Regards,
Petar

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

Ping.
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, June 16, 2017 3:26 PM
To: Maciej Rozycki; 'David Daney'
Cc: Petar Jovanovic; linux-mips@linux-mips.org; ralf@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

Can this change be applied now?

Thanks.

Regards,
Petar

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Maciej W. Rozycki]

On Thu, 6 Jul 2017, Petar Jovanovic wrote:

> Ping.

 I think we came to the conclusion that the way to move forward is to 
implement Octeon-specific controls where generic R1/R2 ISA ones are now 
(ab)used to get the desired effect.  Only once this is in place your 
change can go in.

 So if you want that, then I suggest that you either implement the 
prerequsite clean-up yourself or find someone who will do this for you.  

 HTH,

  Maciej

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

-----Original Message-----
From: Maciej W. Rozycki
> I think we came to the conclusion that the way to move forward is to 
> implement Octeon-specific controls where generic R1/R2 ISA ones are now 
> (ab)used to get the desired effect.  Only once this is in place your 
> change can go in.

As I said earlier in the thread, "in the current ToT, I have not seen
where this change would affect apart from show_cpuinfo()"[1]. So, if
someone implements Octeon-specific controls, where this should be used?
I am not aware of the places where Octeon (ab)uses it in the current
kernel code. David says he "cannot recall exactly what the issues
were" [2].

Petar

[1] https://www.linux-mips.org/archives/linux-mips/2017-05/msg00103.html
[2] https://www.linux-mips.org/archives/linux-mips/2017-03/msg00149.html

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

-----Original Message-----
From: Maciej W. Rozycki
> I think we came to the conclusion that the way to move forward is to 
> implement Octeon-specific controls where generic R1/R2 ISA ones are now 
> (ab)used to get the desired effect.  Only once this is in place your 
> change can go in.

As I said earlier in the thread, "in the current ToT, I have not seen
where this change would affect apart from show_cpuinfo()"[1]. So, if
someone implements Octeon-specific controls, where this should be used?
I am not aware of the places where Octeon (ab)uses it in the current
kernel code. David says he "cannot recall exactly what the issues
were" [2].

Petar

[1] https://www.linux-mips.org/archives/linux-mips/2017-05/msg00103.html
[2] https://www.linux-mips.org/archives/linux-mips/2017-03/msg00149.html

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Maciej W. Rozycki]

On Fri, 7 Jul 2017, Petar Jovanovic wrote:

> As I said earlier in the thread, "in the current ToT, I have not seen
> where this change would affect apart from show_cpuinfo()"[1]. So, if
> someone implements Octeon-specific controls, where this should be used?

 Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)' arch/mips'
does not show anything else indeed.  Please make it unambiguous in the 
patch description then, i.e. that there is no functional change beyond
reporting in `show_cpuinfo'.

> I am not aware of the places where Octeon (ab)uses it in the current
> kernel code. David says he "cannot recall exactly what the issues
> were" [2].

 Thanks for the pointer as this message has not been recorded in 
patchwork due to its changed `Subject'.

 I disagree with David there.  The intended use for generic ISA level 
controls is the same between userland and the kernel.  That is say 
`cpu_has_mips_r2' can be used to conditionally turn on a piece of code 
that uses a MIPSr2 mandatory architectural feature, such as the ROTR 
instruction or the CP0.EBase register.

 Anything that is allowed to vary between implementations, be it the 
availability of a feature or a choice made between possible solutions 
for optimisation reasons, has to use a separate control, either the CPU 
identifier or a dedicated `cpu_<foo>' setting, like we do with cache 
controls for example.

  Maciej

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Maciej W. Rozycki]

On Fri, 7 Jul 2017, Petar Jovanovic wrote:

> As I said earlier in the thread, "in the current ToT, I have not seen
> where this change would affect apart from show_cpuinfo()"[1]. So, if
> someone implements Octeon-specific controls, where this should be used?

 Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)' arch/mips'
does not show anything else indeed.  Please make it unambiguous in the 
patch description then, i.e. that there is no functional change beyond
reporting in `show_cpuinfo'.

> I am not aware of the places where Octeon (ab)uses it in the current
> kernel code. David says he "cannot recall exactly what the issues
> were" [2].

 Thanks for the pointer as this message has not been recorded in 
patchwork due to its changed `Subject'.

 I disagree with David there.  The intended use for generic ISA level 
controls is the same between userland and the kernel.  That is say 
`cpu_has_mips_r2' can be used to conditionally turn on a piece of code 
that uses a MIPSr2 mandatory architectural feature, such as the ROTR 
instruction or the CP0.EBase register.

 Anything that is allowed to vary between implementations, be it the 
availability of a feature or a choice made between possible solutions 
for optimisation reasons, has to use a separate control, either the CPU 
identifier or a dedicated `cpu_<foo>' setting, like we do with cache 
controls for example.

  Maciej

Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[David Daney]

On 07/07/2017 08:04 AM, Maciej W. Rozycki wrote:
> On Fri, 7 Jul 2017, Petar Jovanovic wrote:
> 
>> As I said earlier in the thread, "in the current ToT, I have not seen
>> where this change would affect apart from show_cpuinfo()"[1]. So, if
>> someone implements Octeon-specific controls, where this should be used?
> 
>   Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)' arch/mips'
> does not show anything else indeed.  Please make it unambiguous in the
> patch description then, i.e. that there is no functional change beyond
> reporting in `show_cpuinfo'.
> 
>> I am not aware of the places where Octeon (ab)uses it in the current
>> kernel code. David says he "cannot recall exactly what the issues
>> were" [2].
> 

In my recent review of the code while working the the eBPF JIT, I tried 
to audit the use of cpu_has_* as it relates to OCTEON.  My current 
thoughts are that there is no reason not to merge Petar's patch.

Ralf, please add ...

Acked-by: David Daney <david.daney@cavium.com>

Sorry for the pain here.



>   Thanks for the pointer as this message has not been recorded in
> patchwork due to its changed `Subject'.
> 
>   I disagree with David there.  The intended use for generic ISA level
> controls is the same between userland and the kernel.  That is say
> `cpu_has_mips_r2' can be used to conditionally turn on a piece of code
> that uses a MIPSr2 mandatory architectural feature, such as the ROTR
> instruction or the CP0.EBase register.
> 
>   Anything that is allowed to vary between implementations, be it the
> availability of a feature or a choice made between possible solutions
> for optimisation reasons, has to use a separate control, either the CPU
> identifier or a dedicated `cpu_<foo>' setting, like we do with cache
> controls for example.
> 
>    Maciej
> 

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

________________________________________
From: David Daney [ddaney@caviumnetworks.com]
Sent: Friday, July 07, 2017 6:19 PM
To: Maciej Rozycki; Petar Jovanovic; ralf@linux-mips.org
Cc: Petar Jovanovic; linux-mips@linux-mips.org; david.daney@cavium.com
Subject: Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

On 07/07/2017 08:04 AM, Maciej W. Rozycki wrote:
> On Fri, 7 Jul 2017, Petar Jovanovic wrote:
>
>> As I said earlier in the thread, "in the current ToT, I have not seen
>> where this change would affect apart from show_cpuinfo()"[1]. So, if
>> someone implements Octeon-specific controls, where this should be used?
>
>   Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)' arch/mips'
> does not show anything else indeed.  Please make it unambiguous in the
> patch description then, i.e. that there is no functional change beyond
> reporting in `show_cpuinfo'.
>
>> I am not aware of the places where Octeon (ab)uses it in the current
>> kernel code. David says he "cannot recall exactly what the issues
>> were" [2].
>

> In my recent review of the code while working the the eBPF JIT, I tried
> to audit the use of cpu_has_* as it relates to OCTEON.  My current
> thoughts are that there is no reason not to merge Petar's patch.

> Ralf, please add ...

> Acked-by: David Daney <david.daney@cavium.com>

> Sorry for the pain here.


Ralf?

Regards,
Petar

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

ping

-----Original Message-----
From: Petar Jovanovic [mailto:Petar.Jovanovic@imgtec.com] 
Sent: Monday, August 7, 2017 7:00 PM
To: David Daney <ddaney@caviumnetworks.com>; Maciej Rozycki
<Maciej.Rozycki@imgtec.com>; Petar Jovanovic <petar.jovanovic@rt-rk.com>;
ralf@linux-mips.org
Cc: linux-mips@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1


________________________________________
From: David Daney [ddaney@caviumnetworks.com]
Sent: Friday, July 07, 2017 6:19 PM
To: Maciej Rozycki; Petar Jovanovic; ralf@linux-mips.org
Cc: Petar Jovanovic; linux-mips@linux-mips.org; david.daney@cavium.com
Subject: Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

On 07/07/2017 08:04 AM, Maciej W. Rozycki wrote:
> On Fri, 7 Jul 2017, Petar Jovanovic wrote:
>
>> As I said earlier in the thread, "in the current ToT, I have not seen 
>> where this change would affect apart from show_cpuinfo()"[1]. So, if 
>> someone implements Octeon-specific controls, where this should be used?
>
>   Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)'
arch/mips'
> does not show anything else indeed.  Please make it unambiguous in the 
> patch description then, i.e. that there is no functional change beyond 
> reporting in `show_cpuinfo'.
>
>> I am not aware of the places where Octeon (ab)uses it in the current 
>> kernel code. David says he "cannot recall exactly what the issues 
>> were" [2].
>

> In my recent review of the code while working the the eBPF JIT, I 
> tried to audit the use of cpu_has_* as it relates to OCTEON.  My 
> current thoughts are that there is no reason not to merge Petar's patch.

> Ralf, please add ...

> Acked-by: David Daney <david.daney@cavium.com>

> Sorry for the pain here.


Ralf?

Regards,
Petar
=

RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

[Petar Jovanovic]

ping

-----Original Message-----
From: Petar Jovanovic [mailto:Petar.Jovanovic@imgtec.com] 
Sent: Monday, August 7, 2017 7:00 PM
To: David Daney <ddaney@caviumnetworks.com>; Maciej Rozycki
<Maciej.Rozycki@imgtec.com>; Petar Jovanovic <petar.jovanovic@rt-rk.com>;
ralf@linux-mips.org
Cc: linux-mips@linux-mips.org; david.daney@cavium.com
Subject: RE: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1


________________________________________
From: David Daney [ddaney@caviumnetworks.com]
Sent: Friday, July 07, 2017 6:19 PM
To: Maciej Rozycki; Petar Jovanovic; ralf@linux-mips.org
Cc: Petar Jovanovic; linux-mips@linux-mips.org; david.daney@cavium.com
Subject: Re: [PATCH] MIPS: Octeon: Expose support for mips32r1, mips32r2 and
mips64r1

On 07/07/2017 08:04 AM, Maciej W. Rozycki wrote:
> On Fri, 7 Jul 2017, Petar Jovanovic wrote:
>
>> As I said earlier in the thread, "in the current ToT, I have not seen 
>> where this change would affect apart from show_cpuinfo()"[1]. So, if 
>> someone implements Octeon-specific controls, where this should be used?
>
>   Right, `egrep -r 'cpu_has_(mips_r1|mips32r1|mips64r1|mips32r2)'
arch/mips'
> does not show anything else indeed.  Please make it unambiguous in the 
> patch description then, i.e. that there is no functional change beyond 
> reporting in `show_cpuinfo'.
>
>> I am not aware of the places where Octeon (ab)uses it in the current 
>> kernel code. David says he "cannot recall exactly what the issues 
>> were" [2].
>

> In my recent review of the code while working the the eBPF JIT, I 
> tried to audit the use of cpu_has_* as it relates to OCTEON.  My 
> current thoughts are that there is no reason not to merge Petar's patch.

> Ralf, please add ...

> Acked-by: David Daney <david.daney@cavium.com>

> Sorry for the pain here.


Ralf?

Regards,
Petar
=