From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Chao Zhu" Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER Date: Tue, 19 Mar 2019 11:24:06 +0800 Message-ID: <001d01d4de03$378f18a0$a6ad49e0$@linux.vnet.ibm.com> References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Cc: , , , , , To: "'Dekel Peled'" Return-path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by dpdk.org (Postfix) with ESMTP id 257021DBD for ; Tue, 19 Mar 2019 04:24:14 +0100 (CET) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2J3Nws5117001 for ; Mon, 18 Mar 2019 23:24:14 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rarbjg6un-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 18 Mar 2019 23:24:13 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 19 Mar 2019 03:24:09 -0000 In-Reply-To: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Content-Language: zh-cn List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Dekel£¬ To control the memory order for device memory, I think you should use rte_io_mb() instead of rte_mb(). This will generate correct result. rte_wmb() is used for system memory. > -----Original Message----- > From: Dekel Peled > Sent: Monday, March 18, 2019 8:58 PM > To: chaozhu@linux.vnet.ibm.com > Cc: yskoh@mellanox.com; shahafs@mellanox.com; dev@dpdk.org; > orika@mellanox.com; thomas@monjalon.net; dekelp@mellanox.com; > stable@dpdk.org > Subject: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER > > From previous patch description: "to improve performance on PPC64, use light > weight sync instruction instead of sync instruction." > > Excerpt from IBM doc [1], section "Memory barrier instructions": > "The second form of the sync instruction is light-weight sync, or lwsync. > This form is used to control ordering for storage accesses to system memory > only. It does not create a memory barrier for accesses to device memory." > > This patch removes the use of lwsync, so calls to rte_wmb() and > rte_rmb() will provide correct memory barrier to ensure order of accesses to > system memory and device memory. > > [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > Cc: stable@dpdk.org > > Signed-off-by: Dekel Peled > --- > lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index ce38350..797381c 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -63,11 +63,7 @@ > * Guarantees that the STORE operations generated before the barrier > * occur before the STORE operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_wmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_wmb() asm volatile("sync" : : : "memory") > -#endif > > /** > * Read memory barrier. > @@ -75,11 +71,7 @@ > * Guarantees that the LOAD operations generated before the barrier > * occur before the LOAD operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_rmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_rmb() asm volatile("sync" : : : "memory") > -#endif > > #define rte_smp_mb() rte_mb() > > -- > 1.8.3.1