From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schwierzeck Date: Wed, 26 Sep 2018 21:25:18 +0200 Subject: [U-Boot] [PATCH 2/6] MSCC: add support for VCoreIII SoCs In-Reply-To: <20180925130108.19211-3-gregory.clement@bootlin.com> References: <20180925130108.19211-1-gregory.clement@bootlin.com> <20180925130108.19211-3-gregory.clement@bootlin.com> Message-ID: <0057072a-0991-a73a-aa21-b2a1bfcb1971@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de Hi Gregory, On 25.09.2018 15:01, Gregory CLEMENT wrote: > These families of SoCs are found in the Microsemi Switches solution. > > Currently the support for two families support is added: > - Ocelot (VSC7513, VSC7514) already supported in Linux > - Luton (Luton10: VSC7423, VSC7424, VSC7428 and Luton26: VSC7425, > VSC7426, VSC7426, VSC7427, VSC7429) Is this some polished version of the original vendor U-Boot? Could you maybe add Ocelot and Luton in separate patches? > > Signed-off-by: Gregory CLEMENT > --- > arch/mips/Kconfig | 6 + > arch/mips/Makefile | 1 + > arch/mips/mach-mscc/Kconfig | 101 ++ > arch/mips/mach-mscc/Makefile | 6 + > arch/mips/mach-mscc/cpu.c | 72 ++ > arch/mips/mach-mscc/dram.c | 62 ++ > arch/mips/mach-mscc/include/ioremap.h | 49 + > arch/mips/mach-mscc/include/mach/cache.h | 36 + > arch/mips/mach-mscc/include/mach/common.h | 31 + > arch/mips/mach-mscc/include/mach/ddr.h | 753 +++++++++++++++ > .../mips/mach-mscc/include/mach/luton/luton.h | 37 + > .../include/mach/luton/luton_devcpu_gcb.h | 16 + > .../include/mach/luton/luton_icpu_cfg-ref.h | 884 ++++++++++++++++++ > .../include/mach/luton/luton_icpu_cfg.h | 247 +++++ > .../mach-mscc/include/mach/ocelot/ocelot.h | 35 + > .../include/mach/ocelot/ocelot_devcpu_gcb.h | 353 +++++++ > .../include/mach/ocelot/ocelot_icpu_cfg.h | 884 ++++++++++++++++++ > arch/mips/mach-mscc/include/mach/tlb.h | 65 ++ > arch/mips/mach-mscc/lowlevel_init.S | 29 + > arch/mips/mach-mscc/lowlevel_init_luton.S | 63 ++ > arch/mips/mach-mscc/reset.c | 37 + > 21 files changed, 3767 insertions(+) > create mode 100644 arch/mips/mach-mscc/Kconfig > create mode 100644 arch/mips/mach-mscc/Makefile > create mode 100644 arch/mips/mach-mscc/cpu.c > create mode 100644 arch/mips/mach-mscc/dram.c > create mode 100644 arch/mips/mach-mscc/include/ioremap.h > create mode 100644 arch/mips/mach-mscc/include/mach/cache.h > create mode 100644 arch/mips/mach-mscc/include/mach/common.h > create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h > create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h > create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h > create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h > create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h > create mode 100644 arch/mips/mach-mscc/lowlevel_init.S > create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S > create mode 100644 arch/mips/mach-mscc/reset.c > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 6e5e0ffe65..c4fc3d077b 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -58,6 +58,11 @@ config ARCH_ATH79 > select OF_CONTROL > imply CMD_DM > > +config ARCH_MSCC > + bool "Support MSCC VCore-III" > + select OF_CONTROL > + select DM > + > config ARCH_BMIPS > bool "Support BMIPS SoCs" > select CLK > @@ -118,6 +123,7 @@ source "board/imgtec/xilfpga/Kconfig" > source "board/micronas/vct/Kconfig" > source "board/qemu-mips/Kconfig" > source "arch/mips/mach-ath79/Kconfig" > +source "arch/mips/mach-mscc/Kconfig" > source "arch/mips/mach-bmips/Kconfig" > source "arch/mips/mach-pic32/Kconfig" > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index a36f5f1fb6..acb1340942 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -14,6 +14,7 @@ libs-y += arch/mips/lib/ > machine-$(CONFIG_ARCH_ATH79) += ath79 > machine-$(CONFIG_ARCH_BMIPS) += bmips > machine-$(CONFIG_MACH_PIC32) += pic32 > +machine-$(CONFIG_ARCH_MSCC) += mscc > > machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) > libs-y += $(machdirs) > diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig > new file mode 100644 > index 0000000000..20148bfe15 > --- /dev/null > +++ b/arch/mips/mach-mscc/Kconfig > @@ -0,0 +1,101 @@ > +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +if ARCH_MSCC > + > +config SYS_DCACHE_SIZE > + default 32768 > + > +config SYS_DCACHE_LINE_SIZE > + default 32 > + > +config SYS_ICACHE_SIZE > + default 32768 > + > +config SYS_ICACHE_LINE_SIZE > + default 32 > + > +endif from the code below I assume you have a MIPS24k core? If so you should use the automatic cache size detection > + > +menu "MSCC VCore-III platforms" > + depends on ARCH_MSCC > + > +config SOC_VCOREIII > + select SUPPORTS_LITTLE_ENDIAN > + select SUPPORTS_BIG_ENDIAN > + select SUPPORTS_CPU_MIPS32_R1 > + select SUPPORTS_CPU_MIPS32_R2 > + select ROM_EXCEPTION_VECTORS > + select MIPS_TUNE_24KC > + bool sort this alpahetically > + > +config SYS_SOC > + default "mscc" > + > +config SOC_OCELOT > + bool > + select SOC_VCOREIII > + help > + This supports MSCC Ocelot family of SOCs. > + > +config SOC_LUTON > + bool > + select SOC_VCOREIII > + help > + This supports MSCC Luton family of SOCs. > + > +config SYS_CONFIG_NAME > + default "vcoreiii" > + > +choice > + prompt "Board select" > + > +config TARGET_OCELOT_PCB120 > + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" > + select SOC_OCELOT > + help > + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > + ocelot_pcb120 > + > +config TARGET_OCELOT_PCB123 > + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" > + select SOC_OCELOT > + help > + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > + ocelot_pcb123 > + > +config TARGET_LUTON_PCB091 > + bool "MSCC PCB091 Reference Board" > + select SOC_LUTON > + select MSCC_BITBANG_SPI_GPIO > + help > + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to > + luton_pcb091 > +endchoice > + > +choice > + prompt "DDR type" > + > +config DDRTYPE_H5TQ4G63MFR > + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" > + > +config DDRTYPE_MT41K256M16 > + bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)" > + > +config DDRTYPE_H5TQ1G63BFA > + bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)" > + > +config DDRTYPE_MT41J128M16HA > + bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)" > + > +config DDRTYPE_MT41K128M16JT > + bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)" > + > +config DDRTYPE_MT47H128M8HQ > + bool "Micron MT47H128M8-3 (1Gbit, DDR-533 at CL4 @ 4.80ns 16Mbisx8x8)" > + > +endchoice > + > +source "board/mscc/ocelot/Kconfig" > +source "board/mscc/luton/Kconfig" > + > +endmenu > diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile > new file mode 100644 > index 0000000000..6c60f26ca4 > --- /dev/null > +++ b/arch/mips/mach-mscc/Makefile > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +CFLAGS_cpu.o += -finline-limit=64000 > + > +obj-y += cpu.o dram.o reset.o lowlevel_init.o > +obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o > diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c > new file mode 100644 > index 0000000000..3d6dd78c61 > --- /dev/null > +++ b/arch/mips/mach-mscc/cpu.c > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#include > + > +#include > +#include > + > +#include > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* NOTE: lowlevel_init() function does not have access to the > + * stack. Thus, all called functions must be inlined, and (any) local > + * variables must be kept in registers. > + */ > +void vcoreiii_tlb_init(void) > +{ > + register int tlbix = 0; > + > + init_tlb(); > + > + /* 0x70000000 size 32M (0x02000000) */ > + create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, MMU_REGIO_RW); > +#ifdef CONFIG_SOC_LUTON > + create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, MMU_REGIO_RW); > +#endif > + /* 0x40000000 - 0x43ffffff - NON-CACHED! */ > + /* Flash CS0-3, each 16M = 64M total (16 x 4 below ) */ > + create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO, MMU_REGIO_RO); > + create_tlb(tlbix++, MSCC_FLASH_TO+SZ_32M, SZ_16M, MMU_REGIO_RO, MMU_REGIO_RO); > + > + /* 0x20000000 - up */ > +#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M > + create_tlb(tlbix++, MSCC_DDR_TO, SZ_64M, MMU_REGIO_RW, MMU_REGIO_INVAL); > +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M > + create_tlb(tlbix++, MSCC_DDR_TO, SZ_64M, MMU_REGIO_RW, MMU_REGIO_RW); > +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M > + create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW, MMU_REGIO_INVAL); > +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M > + create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW, MMU_REGIO_RW); > +#else /* 1024M */ > + create_tlb(tlbix++, MSCC_DDR_TO, SZ_512M, MMU_REGIO_RW, MMU_REGIO_RW); > +#endif can't you leave that to the kernel? U-Boot is only running in kernel mode and doesn't need MMU mappings. > +} > + > +int mach_cpu_init(void) > +{ > + /* Speed up NOR flash access */ > +#ifdef CONFIG_SOC_LUTON > + writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + > +#else > + writel( > +#endif > + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + > + ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG)); > + > + /* Disable all IRQs - map to destination map 0 */ > + writel(0, REG_CFG(ICPU_INTR_ENA)); > +#ifdef CONFIG_SOC_OCELOT > + writel(~0, REG_CFG(ICPU_DST_INTR_MAP(0))); > + writel(0, REG_CFG(ICPU_DST_INTR_MAP(1))); > + writel(0, REG_CFG(ICPU_DST_INTR_MAP(2))); > + writel(0, REG_CFG(ICPU_DST_INTR_MAP(3))); > +#else > + writel(ICPU_INTR_IRQ0_ENA_IRQ0_ENA, REG_CFG(ICPU_INTR_IRQ0_ENA)); > +#endif do you really need to disable interrupts after a cold or warm boot? > + return 0; > +} > diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c > new file mode 100644 > index 0000000000..2db9001fe9 > --- /dev/null > +++ b/arch/mips/mach-mscc/dram.c > @@ -0,0 +1,62 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#include > + > +#include > +#include > + > +#include > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int vcoreiii_ddr_init(void) > +{ > + int res; > + if (!(readl(REG_CFG(ICPU_MEMCTRL_STAT)) & > + ICPU_MEMCTRL_STAT_INIT_DONE)) { > + hal_vcoreiii_init_memctl(); > + hal_vcoreiii_wait_memctl(); > + if (hal_vcoreiii_init_dqs() != 0 || > + hal_vcoreiii_train_bytelane(0) != 0 > +#ifdef CONFIG_SOC_OCELOT > + || hal_vcoreiii_train_bytelane(1) != 0 > +#endif > + ) > + hal_vcoreiii_ddr_failed(); > + } > + > +#if (CONFIG_SYS_TEXT_BASE != 0x20000000) > + res = dram_check(); > + if (res == 0) > + hal_vcoreiii_ddr_verified(); > + else > + hal_vcoreiii_ddr_failed(); > + > + /* Clear boot-mode and read-back to activate/verify */ > + writel(readl(REG_CFG(ICPU_GENERAL_CTRL))& ~ICPU_GENERAL_CTRL_BOOT_MODE_ENA, > + REG_CFG(ICPU_GENERAL_CTRL)); clrbits_32()? > + readl(REG_CFG(ICPU_GENERAL_CTRL)); > +#else > + res = 0; > +#endif > + return res; > +} > + > +int print_cpuinfo(void) > +{ > + printf("MSCC VCore-III MIPS 24Kec\n"); > + > + return 0; > +} > + > +int dram_init(void) > +{ > + while (vcoreiii_ddr_init()); > + > + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; > + return 0; > +} > diff --git a/arch/mips/mach-mscc/include/ioremap.h b/arch/mips/mach-mscc/include/ioremap.h > new file mode 100644 > index 0000000000..684f89168c > --- /dev/null > +++ b/arch/mips/mach-mscc/include/ioremap.h > @@ -0,0 +1,49 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef __ASM_MACH_MSCC_IOREMAP_H > +#define __ASM_MACH_MSCC_IOREMAP_H > + > +#include > +#include > + > +/* > + * Allow physical addresses to be fixed up to help peripherals located > + * outside the low 32-bit range -- generic pass-through version. > + */ > +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, > + phys_addr_t size) > +{ > + return phys_addr; > +} > + > +static inline int is_vcoreiii_internal_registers(phys_addr_t offset) > +{ > +#if defined(CONFIG_ARCH_MSCC) > + if ((offset >= MSCC_IO_ORIGIN1_OFFSET && offset < (MSCC_IO_ORIGIN1_OFFSET+MSCC_IO_ORIGIN1_SIZE)) || > + (offset >= MSCC_IO_ORIGIN2_OFFSET && offset < (MSCC_IO_ORIGIN2_OFFSET+MSCC_IO_ORIGIN2_SIZE))) > + return 1; > +#endif > + > + return 0; > +} > + > +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, > + unsigned long flags) > +{ > + if (is_vcoreiii_internal_registers(offset)) > + return (void __iomem *)offset; > + > + return NULL; > +} > + > +static inline int plat_iounmap(const volatile void __iomem *addr) > +{ > + return is_vcoreiii_internal_registers((unsigned long)addr); > +} > + > +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT > + > +#endif /* __ASM_MACH_MSCC_IOREMAP_H */ > diff --git a/arch/mips/mach-mscc/include/mach/cache.h b/arch/mips/mach-mscc/include/mach/cache.h > new file mode 100644 > index 0000000000..f3d09014f3 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/cache.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > +#define MIPS32_CACHE_OP(which, op) (which | (op << 2)) > + > +#define MIPS32_WHICH_ICACHE 0x0 > +#define MIPS32_WHICH_DCACHE 0x1 > + > +#define MIPS32_INDEX_INVALIDATE 0x0 > +#define MIPS32_INDEX_LOAD_TAG 0x1 > +#define MIPS32_INDEX_STORE_TAG 0x2 > +#define MIPS32_HIT_INVALIDATE 0x4 > +#define MIPS32_ICACHE_FILL 0x5 > +#define MIPS32_DCACHE_HIT_INVALIDATE 0x5 > +#define MIPS32_DCACHE_HIT_WRITEBACK 0x6 > +#define MIPS32_FETCH_AND_LOCK 0x7 > + > +#define ICACHE_LOAD_LOCK (MIPS32_CACHE_OP(MIPS32_WHICH_ICACHE, MIPS32_FETCH_AND_LOCK)) > + > +#define CACHE_LINE_LEN 32 you can use ARCH_DMA_MINALIGN for this > + > +/* Prefetch and lock instructions into cache */ > +static inline void icache_lock(void *func, size_t len) > +{ > + int i, lines = ((len - 1) / CACHE_LINE_LEN) + 1; > + for (i = 0; i < lines; i++) { > + asm volatile (" cache %0, %1(%2)" > + : /* No Output */ > + : "I" ICACHE_LOAD_LOCK, > + "n" (i*CACHE_LINE_LEN), > + "r" (func) > + : /* No Clobbers */); > + } > +} could you try to implement this in a generic way in arch/mips/lib/cache.c or arch/mips/include/asm/cacheops.h? > + > diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h > new file mode 100644 > index 0000000000..7e5c81c925 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/common.h > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef __ASM_MACH_COMMON_H > +#define __ASM_MACH_COMMON_H > + > +// Stick to using register offsets - matching readl()/writel() prototypes > +#define MSCC_IOREG(t,o) ((void *)MSCC_IOADDR(t,o)) > + > +#if defined(CONFIG_SOC_OCELOT) > +#include > +#include > +#include > +#elif defined(CONFIG_SOC_LUTON) > +#include > +#include > +#include > +#else > +#error Unsupported platform > +#endif > + > +#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ > +#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ > +#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ > +#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ > + > +#define VCOREIII_TIMER_DIVIDER 25 // Clock tick ~ 0.1 us > + > +#endif /* __ASM_MACH_COMMON_H */ > diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h > new file mode 100644 > index 0000000000..aef3facdca > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/ddr.h > @@ -0,0 +1,753 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef __ASM_MACH_DDR_H > +#define __ASM_MACH_DDR_H > + > +#include > +#include > +#include > + > +#define MIPS_VCOREIII_MEMORY_DDR3 > +#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE > + > +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ > + > +/* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 13 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 2437 > +#define VC3_MPAR_tRAS_min 12 > +#define VC3_MPAR_CL 6 > +#define VC3_MPAR_tWTR 4 > +#define VC3_MPAR_tRC 16 > +#define VC3_MPR_tFAW 16 > +#define VC3_MPAR_tRP 5 > +#define VC3_MPAR_tRRD 4 > +#define VC3_MPAR_tRCD 5 > +#define VC3_MPAR_tMRD 4 > +#define VC3_MPAR_tRFC 35 > +#define VC3_MPAR_CWL 5 > +#define VC3_MPAR_tXPR 38 > +#define VC3_MPAR_tMOD 12 > +#define VC3_MPAR_tDLLK 512 > +#define VC3_MPAR_tWR 5 > + > +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) /* Validation board */ > + > +/* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 14 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 2437 > +#define VC3_MPAR_tRAS_min 12 > +#define VC3_MPAR_CL 5 > +#define VC3_MPAR_tWTR 4 > +#define VC3_MPAR_tRC 16 > +#define VC3_MPAR_tFAW 16 > +#define VC3_MPAR_tRP 5 > +#define VC3_MPAR_tRRD 4 > +#define VC3_MPAR_tRCD 5 > +#define VC3_MPAR_tMRD 4 > +#define VC3_MPAR_tRFC 50 > +#define VC3_MPAR_CWL 5 > +#define VC3_MPAR_tXPR 54 > +#define VC3_MPAR_tMOD 12 > +#define VC3_MPAR_tDLLK 512 > +#define VC3_MPAR_tWR 5 > + > +#elif defined(CONFIG_DDRTYPE_MT41K256M16) /* JR2 Validation board */ > + > +/* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 15 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 2437 > +#define VC3_MPAR_tRAS_min 12 > +#define VC3_MPAR_CL 5 > +#define VC3_MPAR_tWTR 4 > +#define VC3_MPAR_tRC 16 > +#define VC3_MPAR_tFAW 16 > +#define VC3_MPAR_tRP 5 > +#define VC3_MPAR_tRRD 4 > +#define VC3_MPAR_tRCD 5 > +#define VC3_MPAR_tMRD 4 > +#define VC3_MPAR_tRFC 82 > +#define VC3_MPAR_CWL 5 > +#define VC3_MPAR_tXPR 85 > +#define VC3_MPAR_tMOD 12 > +#define VC3_MPAR_tDLLK 512 > +#define VC3_MPAR_tWR 5 > + > +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) /* JR2 Reference board */ > + > +/* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 15 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 2437 > +#define VC3_MPAR_tRAS_min 12 > +#define VC3_MPAR_CL 6 > +#define VC3_MPAR_tWTR 4 > +#define VC3_MPAR_tRC 17 > +#define VC3_MPAR_tFAW 16 > +#define VC3_MPAR_tRP 5 > +#define VC3_MPAR_tRRD 4 > +#define VC3_MPAR_tRCD 5 > +#define VC3_MPAR_tMRD 4 > +#define VC3_MPAR_tRFC 82 > +#define VC3_MPAR_CWL 5 > +#define VC3_MPAR_tXPR 85 > +#define VC3_MPAR_tMOD 12 > +#define VC3_MPAR_tDLLK 512 > +#define VC3_MPAR_tWR 5 > + > +#elif defined(CONFIG_DDRTYPE_MT41K128M16JT) > + > +/* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 14 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 2437 > +#define VC3_MPAR_tRAS_min 12 > +#define VC3_MPAR_CL 6 > +#define VC3_MPAR_tWTR 4 > +#define VC3_MPAR_tRC 16 > +#define VC3_MPAR_tFAW 16 > +#define VC3_MPAR_tRP 5 > +#define VC3_MPAR_tRRD 4 > +#define VC3_MPAR_tRCD 5 > +#define VC3_MPAR_tMRD 4 > +#define VC3_MPAR_tRFC 82 > +#define VC3_MPAR_CWL 5 > +#define VC3_MPAR_tXPR 85 > +#define VC3_MPAR_tMOD 12 > +#define VC3_MPAR_tDLLK 512 > +#define VC3_MPAR_tWR 5 > + > +#elif defined(CONFIG_DDRTYPE_MT47H128M8HQ) /* Luton10/26 Refboards */ > + > +/* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533 at CL4 @ 4.80ns */ > +#define VC3_MPAR_bank_addr_cnt 3 > +#define VC3_MPAR_row_addr_cnt 14 > +#define VC3_MPAR_col_addr_cnt 10 > +#define VC3_MPAR_tREFI 1625 > +#define VC3_MPAR_tRAS_min 9 > +#define VC3_MPAR_CL 4 > +#define VC3_MPAR_tWTR 2 > +#define VC3_MPAR_tRC 12 > +#define VC3_MPAR_tFAW 8 > +#define VC3_MPAR_tRP 4 > +#define VC3_MPAR_tRRD 2 > +#define VC3_MPAR_tRCD 4 > + > +#define VC3_MPAR_tRPA 4 > +#define VC3_MPAR_tRP 4 > + > +#define VC3_MPAR_tMRD 2 > +#define VC3_MPAR_tRFC 27 > + > +#define VC3_MPAR__400_ns_dly 84 > + > +#define VC3_MPAR_tWR 4 > +#undef MIPS_VCOREIII_MEMORY_DDR3 > +#else > + > +#error Unknown DDR system configuration - please add! > + > +#endif > + > +#ifdef CONFIG_SOC_OCELOT > +#define MIPS_VCOREIII_MEMORY_16BIT 1 > +#endif > + > +#define MIPS_VCOREIII_MEMORY_SSTL_ODT 7 > +#define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7 > +#define VCOREIII_DDR_DQS_MODE_CALIBRATE > + > +#ifdef MIPS_VCOREIII_MEMORY_16BIT > + #define VC3_MPAR_16BIT 1 > +#else > + #define VC3_MPAR_16BIT 0 > +#endif > + > +#ifdef MIPS_VCOREIII_MEMORY_DDR3 > + #define VC3_MPAR_DDR3_MODE 1 /* DDR3 */ > + #define VC3_MPAR_BURST_LENGTH 8 /* Always 8 (1) for DDR3 */ > + #ifdef MIPS_VCOREIII_MEMORY_16BIT > +#define VC3_MPAR_BURST_SIZE 1 /* Always 1 for DDR3/16bit */ > + #else > + #define VC3_MPAR_BURST_SIZE 0 > + #endif > +#else > + #define VC3_MPAR_DDR3_MODE 0 /* DDR2 */ > + #ifdef MIPS_VCOREIII_MEMORY_16BIT > + #define VC3_MPAR_BURST_LENGTH 4 /* in DDR2 16-bit mode, use burstlen 4 */ > + #else > + #define VC3_MPAR_BURST_LENGTH 8 /* For 8-bit IF we must run burst-8 */ > + #endif > + #define VC3_MPAR_BURST_SIZE 0 /* Always 0 for DDR2 */ > +#endif > + > +#define VC3_MPAR_RL VC3_MPAR_CL > +#if !defined(MIPS_VCOREIII_MEMORY_DDR3) > +#define VC3_MPAR_WL (VC3_MPAR_RL-1) > +#define VC3_MPAR_MD VC3_MPAR_tMRD > +#define VC3_MPAR_ID VC3_MPAR__400_ns_dly > +#define VC3_MPAR_SD VC3_MPAR_tXSRD > +#define VC3_MPAR_OW (VC3_MPAR_WL-2) > +#define VC3_MPAR_OR (VC3_MPAR_WL-3) > +#define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA) > +#define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW) > +#define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4) > +#define MSCC_MEMPARM_MR0 \ > + (VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | ((VC3_MPAR_tWR-1) << 9) > +#define MSCC_MEMPARM_MR1 0x382 /* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */ > +#define MSCC_MEMPARM_MR2 0 > +#define MSCC_MEMPARM_MR3 0 > +#else > +#define VC3_MPAR_WL VC3_MPAR_CWL > +#define VC3_MPAR_MD VC3_MPAR_tMOD > +#define VC3_MPAR_ID VC3_MPAR_tXPR > +#define VC3_MPAR_SD VC3_MPAR_tDLLK > +#define VC3_MPAR_OW 2 > +#define VC3_MPAR_OR 2 > +#define VC3_MPAR_RP VC3_MPAR_tRP > +#define VC3_MPAR_FAW VC3_MPAR_tFAW > +#define VC3_MPAR_BL 4 > +#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9) > +#define MSCC_MEMPARM_MR1 0x0040 /* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */ > +#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3) > +#define MSCC_MEMPARM_MR3 0 > +#endif /* MIPS_VCOREIII_MEMORY_DDR3 */ > + > +#define MSCC_MEMPARM_MEMCFG \ > + ((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ? \ > + ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) | \ > + (VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) | \ > + (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \ > + (VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) | \ > + (VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \ > + (VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \ > + ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt-1) | \ > + ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt-1) > + > +#define MSCC_MEMPARM_PERIOD \ > + ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \ > + ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI) > + > +#ifdef CONFIG_SOC_OCELOT > +#define MSCC_MEMPARM_TIMING0 \ > + ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL+VC3_MPAR_BL+1-VC3_MPAR_WL) | \ > + ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL-1) | \ > + ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) | \ > + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min-1) | \ > + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL + \ > + VC3_MPAR_BL + \ > + VC3_MPAR_tWR - 1) | \ > + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL-1) | \ > + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL-1) | \ > + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL-3) > + > +#define MSCC_MEMPARM_TIMING1 \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC-1) | \ > + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW-1) | \ > + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP-1) | \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD-1) | \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD-1) | \ > + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \ > + VC3_MPAR_BL + \ > + VC3_MPAR_tWTR - 1) > + > +#define MSCC_MEMPARM_TIMING2 \ > + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP-1) | \ > + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD-1) | \ > + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC-1) | \ > + ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID-1) > + > +#define MSCC_MEMPARM_TIMING3 \ > + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL + VC3_MPAR_tWTR - 1) | \ > + ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR-1) | \ > + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW-1) | \ > + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL-3) > + > +#else > +#define MSCC_MEMPARM_TIMING0 \ > + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min-1) | \ > + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \ > + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \ > + VC3_MPAR_tWR) | \ > + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \ > + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL-3) | \ > + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL-3) > + > +#define MSCC_MEMPARM_TIMING1 \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC-1) | \ > + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW) | \ > + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP-1) | \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD-1) | \ > + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD-1) | \ > + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \ > + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \ > + VC3_MPAR_tWTR) > +#define MSCC_MEMPARM_TIMING2 \ > + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA-1) | \ > + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD-1) | \ > + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC-1) | \ > + ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly) > + > +#define MSCC_MEMPARM_TIMING3 \ > + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL-1) | \ > + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL-1) | \ > + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL-3) > + > +#endif > + > +enum { > + DDR_TRAIN_OK, > + DDR_TRAIN_CONTINUE, > + DDR_TRAIN_ERROR, > +}; > + > +/* We actually have very few 'pause' possibilities apart from > + * these assembly nops (at this very early stage). */ > +#define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop") > + > + > +/* NB: Assumes inlining as no stack is available! */ > +static inline void set_dly(u32 bytelane, u32 dly) > +{ > + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > + r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M; > + r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly); > + writel(r, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > +} > + > +static inline bool incr_dly(u32 bytelane) > +{ > + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) { > + writel(r + 1, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > + return true; > + } > + > + return false; > +} > +static inline bool adjust_dly(int adjust) > +{ > + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(0))); > + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) { > + writel(r + adjust, REG_CFG(ICPU_MEMCTRL_DQS_DLY(0))); > + return true; > + } > + > + return false; > +} > + > +/* NB: Assumes inlining as no stack is available! */ > +static inline void center_dly(u32 bytelane, u32 start) > +{ > + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))) - start; > + writel(start + (r >> 1), REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > +} > + > +static inline void memphy_soft_reset(void) > +{ > + writel(readl(REG_CFG(ICPU_MEMPHY_CFG)) | ICPU_MEMPHY_CFG_PHY_FIFO_RST, > + REG_CFG(ICPU_MEMPHY_CFG)); > + PAUSE(); > + writel(readl(REG_CFG(ICPU_MEMPHY_CFG)) & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST, > + REG_CFG(ICPU_MEMPHY_CFG)); > + PAUSE(); > +} > +#ifdef CONFIG_SOC_OCELOT > +static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd }; > + > +static inline void sleep_100ns(u32 val) > +{ > + /* Set the timer tick generator to 100 ns */ > + writel(VCOREIII_TIMER_DIVIDER-1, REG_CFG(ICPU_TIMER_TICK_DIV)); > + > + /* Set the timer value */ > + writel(val, REG_CFG(ICPU_TIMER_VALUE(0))); > + > + /* Enable timer 0 for one-shot */ > + writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA, > + REG_CFG(ICPU_TIMER_CTRL(0))); > + > + /* Wait for timer 0 to reach 0 */ > + while (readl(REG_CFG(ICPU_TIMER_VALUE(0))) != 0) > + ; > +} > + > +static inline void hal_vcoreiii_ddr_reset_assert(void) > +{ > + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ > + writel(readl(REG_GCB(PERF_GPIO_OE)) | BIT(19), REG_GCB(PERF_GPIO_OE)); > + writel(BIT(19), REG_GCB(PERF_GPIO_OUT_CLR)); > + sleep_100ns(10000); > +} > + > +static inline void hal_vcoreiii_ddr_reset_release(void) > +{ > + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ > + writel(readl(REG_GCB(PERF_GPIO_OE)) | BIT(19), REG_GCB(PERF_GPIO_OE)); > + writel(BIT(19), REG_GCB(PERF_GPIO_OUT_SET)); > + sleep_100ns(10000); > +} > + > +/* > + * DDR memory sanity checking failed, tally and do hard reset > + * > + * NB: Assumes inlining as no stack is available! > + */ > +static inline void hal_vcoreiii_ddr_failed(void) > +{ > + register u32 reset; > + > + writel(readl(REG_CFG(ICPU_GPR(6))) + 1, REG_CFG(ICPU_GPR(6))); > + > + writel(readl(REG_GCB(PERF_GPIO_OE)) & ~BIT(19), > + REG_GCB(PERF_GPIO_OE)); > + > + /* Jump to reset - does not return */ > + reset = KSEG0ADDR(_machine_restart); > + icache_lock((void*)reset, 128); // Reset while running from cache > + asm volatile ("jr %0" : : "r" (reset)); > + > + while(1) > + ; can't you just use panic() or hang()? > +} > +/* > + * DDR memory sanity checking done, possibly enable ECC. > + * > + * NB: Assumes inlining as no stack is available! > + */ > +static inline void hal_vcoreiii_ddr_verified(void) > +{ > +#ifdef MIPS_VCOREIII_MEMORY_ECC > + /* Finally, enable ECC */ > + u32 val = readl(REG_CFG(ICPU_MEMCTRL_CFG)); shouldn't it "register u32 val" like in the other functions? > + > + val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA; > + val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE; > + > + writel(val, REG_CFG(ICPU_MEMCTRL_CFG)); > +#endif > + > + /* Reset Status register - sticky bits */ > + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), > + REG_CFG(ICPU_MEMCTRL_STAT)); > +} > +/* NB: Assumes inlining as no stack is available! */ > +static inline int look_for(u32 bytelane) > +{ > + register u32 i; > + /* Reset FIFO in case any previous access failed */ > + for (i = 0; i < sizeof(training_data); i++) { > + register u32 byte; > + memphy_soft_reset(); > + /* Reset sticky bits */ > + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), REG_CFG(ICPU_MEMCTRL_STAT)); > + /* Read data */ > + byte = ((volatile u8 *) MSCC_DDR_TO)[bytelane + (i * 4)]; > + if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) & > + (ICPU_MEMCTRL_STAT_RDATA_MASKED| > + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) { > + /* Noise on the line */ > + goto read_error; > + } > + /* If mismatch, increment DQS - if possible */ > + if (byte != training_data[i]) { > + read_error: > + if (!incr_dly(bytelane)) { > + return DDR_TRAIN_ERROR; > + } > + return DDR_TRAIN_CONTINUE; > + } > + } > + return DDR_TRAIN_OK; > +} > + > + > +/* NB: Assumes inlining as no stack is available! */ > +static inline int look_past(u32 bytelane) > +{ > + register u32 i; > + /* Reset FIFO in case any previous access failed */ > + for (i = 0; i < sizeof(training_data); i++) { > + register u32 byte; > + memphy_soft_reset(); > + /* Ack sticky bits */ > + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), REG_CFG(ICPU_MEMCTRL_STAT)); > + byte = ((volatile u8 *) MSCC_DDR_TO)[bytelane + (i * 4)]; > + if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) & > + (ICPU_MEMCTRL_STAT_RDATA_MASKED| > + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) { > + /* Noise on the line */ > + goto read_error; > + } > + /* Bail out when we see first mismatch */ > + if (byte != training_data[i]) { > + read_error: > + return DDR_TRAIN_OK; > + } > + } > + /* All data compares OK, increase DQS and retry */ > + if (!incr_dly(bytelane)) > + return DDR_TRAIN_ERROR; > + > + return DDR_TRAIN_CONTINUE; > +} > + > +static inline int hal_vcoreiii_train_bytelane(u32 bytelane) > +{ > + register int res; > + register u32 dqs_s; > + > + set_dly(bytelane, 0); // Start training at DQS=0 > + while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE) > + ; > + if(res != DDR_TRAIN_OK) > + return res; > + > + dqs_s = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))); > + while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE) > + ; > + if(res != DDR_TRAIN_OK) > + return res; > + /* Reset FIFO - for good measure */ > + memphy_soft_reset(); > + /* Adjust to center [dqs_s;cur] */ > + center_dly(bytelane, dqs_s); > + return DDR_TRAIN_OK; > +} > +/* This algorithm is converted from the TCL training algorithm used > + * during silicon simulation. > + * NB: Assumes inlining as no stack is available! > + */ > +static inline int hal_vcoreiii_init_dqs(void) > +{ > +#define MAX_DQS 32 > + register u32 i, j; > + for (i = 0; i < MAX_DQS; i++) { > + set_dly(0, i); // Byte-lane 0 > + for (j = 0; j < MAX_DQS; j++) { > + register u32 __attribute__ ((unused)) byte; > + set_dly(1, j); // Byte-lane 1 > + /* Reset FIFO in case any previous access failed */ > + memphy_soft_reset(); > + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), > + REG_CFG(ICPU_MEMCTRL_STAT)); > + byte = ((volatile u8 *) MSCC_DDR_TO)[0]; > + byte = ((volatile u8 *) MSCC_DDR_TO)[1]; > + if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) & > + (ICPU_MEMCTRL_STAT_RDATA_MASKED| > + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) { > + } else { > + return 0; > + } > + } > + } > + return -1; > +} > + > + > +static inline int dram_check(void) > +{ > +#define DDR ((volatile u32 *) MSCC_DDR_TO) > + register u32 i; > + > + for (i = 0; i < 8; i++) { > + DDR[i] = ~i; > + if (DDR[i] != ~i) { > + return 1; > + } > + } > + return 0; > +} > +#else /* Luton */ > + > +static inline void sleep_100ns(u32 val) > +{ > +} > +static inline void hal_vcoreiii_ddr_reset_assert(void) > +{ > +} > +static inline void hal_vcoreiii_ddr_reset_release(void) > +{ > +} > +static inline void hal_vcoreiii_ddr_failed(void) > +{ > + register u32 memphy_cfg = readl(REG_CFG(ICPU_MEMPHY_CFG)); > + > + /* Do a fifo reset and start over */ > + writel( memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST, > + REG_CFG(ICPU_MEMPHY_CFG)); > + writel( memphy_cfg & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST, > + REG_CFG(ICPU_MEMPHY_CFG)); > + writel( memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST, > + REG_CFG(ICPU_MEMPHY_CFG)); > +} > + > +static inline void hal_vcoreiii_ddr_verified(void){} > + > +static inline int look_for(u32 data) > +{ > + register u32 byte = ((volatile u8 *) MSCC_DDR_TO)[0]; > + > + if (data != byte) { > + if (!incr_dly(0)) > + return DDR_TRAIN_ERROR; > + return DDR_TRAIN_CONTINUE; > + } > + > + return DDR_TRAIN_OK; > +} > + > +/* This algorithm is converted from the TCL training algorithm used > + * during silicon simulation. > + * NB: Assumes inlining as no stack is available! > + */ > +static inline int hal_vcoreiii_train_bytelane(u32 bytelane) > +{ > + register int res; > + > + set_dly(bytelane, 0); // Start training at DQS=0 > + while ((res = look_for(0xff)) == DDR_TRAIN_CONTINUE) > + ; > + if(res != DDR_TRAIN_OK) > + return res; > + > + set_dly(bytelane, 0); // Start training at DQS=0 > + while ((res = look_for(0x00)) == DDR_TRAIN_CONTINUE) > + ; > + > + if(res != DDR_TRAIN_OK) > + return res; > + > + adjust_dly(-3); > + > + return DDR_TRAIN_OK; > +} > + > +static inline int hal_vcoreiii_init_dqs(void) > +{ > + return 0; > +} > + > +static inline int dram_check(void) > +{ > +#define DDR ((volatile u32 *) MSCC_DDR_TO) > + register u32 i; > + > + for (i = 0; i < 8; i++) { > + DDR[i] = ~i; > + if (DDR[i] != ~i) { > + return 1; > + } > + } > + > + return 0; > +} > +#endif > + > +/* NB: Called *early* to init memory controller - > + * assumes inlining as no stack is available! */ > +static inline void hal_vcoreiii_init_memctl(void) > +{ > + /* Ensure DDR is in reset */ > + hal_vcoreiii_ddr_reset_assert(); > + > + /* Wait maybe not needed, but ... */ > + PAUSE(); > + > + /* Drop sys ctl memory controller forced reset */ > + writel(readl(REG_CFG(ICPU_RESET)) & ~ICPU_RESET_MEM_RST_FORCE, REG_CFG(ICPU_RESET)); > + PAUSE(); > + > + /* Drop Reset, enable SSTL */ > + writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, REG_CFG(ICPU_MEMPHY_CFG)); > + PAUSE(); > + > + /* Start the automatic SSTL output and ODT drive-strength calibration */ > + writel(/* ODT */ > + ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) | > + /* drive strength */ > + ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) | > + /* Start calibration process */ > + ICPU_MEMPHY_ZCAL_ZCAL_ENA, REG_CFG(ICPU_MEMPHY_ZCAL)); > + > + while(readl(REG_CFG(ICPU_MEMPHY_ZCAL)) & ICPU_MEMPHY_ZCAL_ZCAL_ENA) > + ; /* Wait for ZCAL to clear */ > +#ifdef CONFIG_SOC_OCELOT > + /* Check no ZCAL_ERR */ > + if (readl(REG_CFG(ICPU_MEMPHY_ZCAL_STAT)) & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR) { > + hal_vcoreiii_ddr_failed(); > + } > +#endif > + /* Drive CL, CK, ODT */ > + writel(readl(REG_CFG(ICPU_MEMPHY_CFG)) | > + ICPU_MEMPHY_CFG_PHY_ODT_OE | > + ICPU_MEMPHY_CFG_PHY_CK_OE | > + ICPU_MEMPHY_CFG_PHY_CL_OE, REG_CFG(ICPU_MEMPHY_CFG)); > + > + /* Initialize memory controller */ > + writel(MSCC_MEMPARM_MEMCFG, REG_CFG(ICPU_MEMCTRL_CFG)); > + writel(MSCC_MEMPARM_PERIOD, REG_CFG(ICPU_MEMCTRL_REF_PERIOD)); > + > + writel(MSCC_MEMPARM_TIMING0, REG_CFG(ICPU_MEMCTRL_TIMING0)); > + writel(MSCC_MEMPARM_TIMING1, REG_CFG(ICPU_MEMCTRL_TIMING1)); > + writel(MSCC_MEMPARM_TIMING2, REG_CFG(ICPU_MEMCTRL_TIMING2)); > + writel(MSCC_MEMPARM_TIMING3, REG_CFG(ICPU_MEMCTRL_TIMING3)); > + writel(MSCC_MEMPARM_MR0, REG_CFG(ICPU_MEMCTRL_MR0_VAL)); > + writel(MSCC_MEMPARM_MR1, REG_CFG(ICPU_MEMCTRL_MR1_VAL)); > + writel(MSCC_MEMPARM_MR2, REG_CFG(ICPU_MEMCTRL_MR2_VAL)); > + writel(MSCC_MEMPARM_MR3, REG_CFG(ICPU_MEMCTRL_MR3_VAL)); > + > +#ifdef CONFIG_SOC_OCELOT > + /* Termination setup - enable ODT */ > + writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA | > + /* Assert ODT0 for any write */ > + ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3), > + REG_CFG(ICPU_MEMCTRL_TERMRES_CTRL)); > + > + /* Release Reset from DDR */ > + hal_vcoreiii_ddr_reset_release(); > + > + writel(readl(REG_CFG(ICPU_GPR(7))) + 1, REG_CFG(ICPU_GPR(7))); > +#else /* Luton */ > + /* Termination setup - disable ODT */ > + writel(0, REG_CFG(ICPU_MEMCTRL_TERMRES_CTRL)); > + > +#endif > +} > + > +static void inline hal_vcoreiii_wait_memctl(void) > +{ > + /* Now, rip it! */ > + writel(ICPU_MEMCTRL_CTRL_INITIALIZE, REG_CFG(ICPU_MEMCTRL_CTRL)); > + > + while(!(readl(REG_CFG(ICPU_MEMCTRL_STAT)) & ICPU_MEMCTRL_STAT_INIT_DONE)) > + ; > + > + /* Settle...? */ > + sleep_100ns(10000); > +#ifdef CONFIG_SOC_OCELOT > + /* Establish data contents in DDR RAM for training */ > + ((volatile u32 *)MSCC_DDR_TO)[0] = 0xcacafefe; > + ((volatile u32 *)MSCC_DDR_TO)[1] = 0x22221111; > + ((volatile u32 *)MSCC_DDR_TO)[2] = 0x44443333; > + ((volatile u32 *)MSCC_DDR_TO)[3] = 0x66665555; > + ((volatile u32 *)MSCC_DDR_TO)[4] = 0x88887777; > + ((volatile u32 *)MSCC_DDR_TO)[5] = 0xaaaa9999; > + ((volatile u32 *)MSCC_DDR_TO)[6] = 0xccccbbbb; > + ((volatile u32 *)MSCC_DDR_TO)[7] = 0xeeeedddd; > +#else > + ((volatile u32 *)MSCC_DDR_TO)[0] = 0xff; > +#endif use writel() or at least __raw_writel() > +} > +#endif /* __ASM_MACH_DDR_H */ > diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h > new file mode 100644 > index 0000000000..4f761b1bb7 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Microsemi Ocelot Switch driver > + * > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_H_ > +#define _MSCC_OCELOT_H_ > + > +#include > +#include > + > +/* > + * Target offset base(s) > + */ > +#define MSCC_IO_ORIGIN1_OFFSET 0x60000000 > +#define MSCC_IO_ORIGIN1_SIZE 0x01000000 > +#define MSCC_IO_ORIGIN2_OFFSET 0x70000000 > +#define MSCC_IO_ORIGIN2_SIZE 0x00200000 > +#ifndef MSCC_IO_OFFSET1 > +#define MSCC_IO_OFFSET1(offset) (MSCC_IO_ORIGIN1_OFFSET + offset) > +#endif > +#ifndef MSCC_IO_OFFSET2 > +#define MSCC_IO_OFFSET2(offset) (MSCC_IO_ORIGIN2_OFFSET + offset) > +#endif > +#define BASE_CFG 0x70000000 > +#define BASE_UART 0x70100000 > +#define BASE_DEVCPU_GCB 0x60070000 > +#define BASE_MACRO 0x600a0000 > + > +#define REG_OFFSET(t, o) ((volatile unsigned long *)(t + (o))) > +#define REG_CFG(x) REG_OFFSET(BASE_CFG, x) > +#define REG_GCB(x) REG_OFFSET(BASE_DEVCPU_GCB, x) > +#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x) No header files with offsets please except when needed for ASM code. This should come from device-tree. > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h > new file mode 100644 > index 0000000000..0d80c8a534 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ > +#define _MSCC_OCELOT_DEVCPU_GCB_H_ > + > +#define PERF_GPR 0x4 > + > +#define PERF_SOFT_RST 0x90 > + > +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) > +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref.h > new file mode 100644 > index 0000000000..5a5fe079e1 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref.h > @@ -0,0 +1,884 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_ICPU_CFG_H_ > +#define _MSCC_OCELOT_ICPU_CFG_H_ > + > +#define ICPU_GPR(x) (0x4 * (x)) > +#define ICPU_GPR_RSZ 0x4 > + > +#define ICPU_RESET 0x20 > + > +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) > +#define ICPU_RESET_CORE_RST_PROTECT BIT(2) > +#define ICPU_RESET_CORE_RST_FORCE BIT(1) > +#define ICPU_RESET_MEM_RST_FORCE BIT(0) No header files with thousand of register definitions please. Only define what you need per driver. > + > +#define ICPU_GENERAL_CTRL 0x24 > + > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14) > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13) > +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12) > +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8) > +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3) > +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2) > +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1) > +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) > + > +#define ICPU_GENERAL_STAT 0x28 > + > +#define ICPU_GENERAL_STAT_PI_SLV_WR_ERR BIT(9) > +#define ICPU_GENERAL_STAT_PI_SLV_RD_ERR BIT(8) > +#define ICPU_GENERAL_STAT_VCORE_CFG(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_GENERAL_STAT_VCORE_CFG_M GENMASK(7, 4) > +#define ICPU_GENERAL_STAT_VCORE_CFG_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_GENERAL_STAT_REG_IF_ERR(x) (((x) << 1) & GENMASK(3, 1)) > +#define ICPU_GENERAL_STAT_REG_IF_ERR_M GENMASK(3, 1) > +#define ICPU_GENERAL_STAT_REG_IF_ERR_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define ICPU_GENERAL_STAT_CPU_SLEEP BIT(0) > + > +#define ICPU_PI_MST_CFG 0x2c > + > +#define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7) > +#define ICPU_PI_MST_CFG_CLK_POL BIT(6) > +#define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5) > +#define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) > +#define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0) > + > +#define ICPU_PI_MST_CTRL 0x30 > + > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_XFER_ENA BIT(22) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_ENA BIT(21) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT(x) (((x) << 18) & GENMASK(20, 18)) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_M GENMASK(20, 18) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_X(x) (((x) & GENMASK(20, 18)) >> 18) > +#define ICPU_PI_MST_CTRL_CS_TRISTATE_CTRL BIT(17) > +#define ICPU_PI_MST_CTRL_DONE_POL BIT(16) > +#define ICPU_PI_MST_CTRL_SMPL_ON_DONE BIT(15) > +#define ICPU_PI_MST_CTRL_WAITCC(x) (((x) << 7) & GENMASK(14, 7)) > +#define ICPU_PI_MST_CTRL_WAITCC_M GENMASK(14, 7) > +#define ICPU_PI_MST_CTRL_WAITCC_X(x) (((x) & GENMASK(14, 7)) >> 7) > +#define ICPU_PI_MST_CTRL_CSCC(x) (((x) << 5) & GENMASK(6, 5)) > +#define ICPU_PI_MST_CTRL_CSCC_M GENMASK(6, 5) > +#define ICPU_PI_MST_CTRL_CSCC_X(x) (((x) & GENMASK(6, 5)) >> 5) > +#define ICPU_PI_MST_CTRL_OECC(x) (((x) << 3) & GENMASK(4, 3)) > +#define ICPU_PI_MST_CTRL_OECC_M GENMASK(4, 3) > +#define ICPU_PI_MST_CTRL_OECC_X(x) (((x) & GENMASK(4, 3)) >> 3) > +#define ICPU_PI_MST_CTRL_HLDCC(x) ((x) & GENMASK(2, 0)) > +#define ICPU_PI_MST_CTRL_HLDCC_M GENMASK(2, 0) > + > +#define ICPU_PI_MST_STATUS 0x34 > + > +#define ICPU_PI_MST_STATUS_TIMEOUT_ERR_STICKY BIT(0) > + > +#define ICPU_PI_SLV_CFG 0x38 > + > +#define ICPU_PI_SLV_CFG_DONEPOL_VAL BIT(24) > +#define ICPU_PI_SLV_CFG_DONEPOL_SET BIT(23) > +#define ICPU_PI_SLV_CFG_BIGENDIAN BIT(22) > +#define ICPU_PI_SLV_CFG_DONEPARK(x) (((x) << 16) & GENMASK(21, 16)) > +#define ICPU_PI_SLV_CFG_DONEPARK_M GENMASK(21, 16) > +#define ICPU_PI_SLV_CFG_DONEPARK_X(x) (((x) & GENMASK(21, 16)) >> 16) > +#define ICPU_PI_SLV_CFG_DONEWAIT(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_PI_SLV_CFG_DONEWAIT_M GENMASK(15, 8) > +#define ICPU_PI_SLV_CFG_DONEWAIT_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_PI_SLV_CFG_CSWAIT(x) ((x) & GENMASK(7, 0)) > +#define ICPU_PI_SLV_CFG_CSWAIT_M GENMASK(7, 0) > + > +#define ICPU_SPI_MST_CFG 0x3c > + > +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11) > +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) > +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) > + > +#define ICPU_SPI_MST_STATUS 0x40 > +#define ICPU_SPI_MST_STATUS_RSZ 0x4 > + > +#define ICPU_SPI_MST_STATUS_UNSUP_ERR BIT(0) > + > +#define ICPU_SW_MODE 0x50 > + > +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) > +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12) > +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) > +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10) > +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) > +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) > +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0) > + > +#define ICPU_MPU8051_CFG 0x54 > + > +#define ICPU_MPU8051_CFG_UART_SYS_ENA BIT(0) > + > +#define ICPU_MPU8051_STAT 0x58 > + > +#define ICPU_MPU8051_STAT_MPU8051_SBA_ERR BIT(9) > +#define ICPU_MPU8051_STAT_MPU8051_STOP BIT(8) > +#define ICPU_MPU8051_STAT_MPU8051_GPR(x) ((x) & GENMASK(7, 0)) > +#define ICPU_MPU8051_STAT_MPU8051_GPR_M GENMASK(7, 0) > + > +#define ICPU_MPU8051_MMAP 0x5c > + > +#define ICPU_MPU8051_MMAP_MSADDR_CODE_HIGH BIT(7) > +#define ICPU_MPU8051_MMAP_MSADDR_CODE_LOW BIT(6) > +#define ICPU_MPU8051_MMAP_MSADDR_DATA_HIGH BIT(5) > +#define ICPU_MPU8051_MMAP_MSADDR_DATA_LOW BIT(4) > +#define ICPU_MPU8051_MMAP_MAP_CODE_HIGH BIT(3) > +#define ICPU_MPU8051_MMAP_MAP_CODE_LOW BIT(2) > +#define ICPU_MPU8051_MMAP_MAP_DATA_HIGH BIT(1) > +#define ICPU_MPU8051_MMAP_MAP_DATA_LOW BIT(0) > + > +#define ICPU_MEMACC_CTRL 0x60 > + > +#define ICPU_MEMACC_CTRL_MEMACC_EXAMINE BIT(1) > +#define ICPU_MEMACC_CTRL_MEMACC_DO BIT(0) > + > +#define ICPU_MEMACC 0x64 > + > +#define ICPU_MEMACC_MEMACC_STOP(x) (((x) << 18) & GENMASK(31, 18)) > +#define ICPU_MEMACC_MEMACC_STOP_M GENMASK(31, 18) > +#define ICPU_MEMACC_MEMACC_STOP_X(x) (((x) & GENMASK(31, 18)) >> 18) > +#define ICPU_MEMACC_MEMACC_START(x) (((x) << 2) & GENMASK(15, 2)) > +#define ICPU_MEMACC_MEMACC_START_M GENMASK(15, 2) > +#define ICPU_MEMACC_MEMACC_START_X(x) (((x) & GENMASK(15, 2)) >> 2) > + > +#define ICPU_MEMACC_SBA 0x68 > + > +#define ICPU_MPU8051_IROM 0x6c > + > +#define ICPU_INTR_RAW 0x70 > + > +#define ICPU_INTR_TRIGGER 0x74 > +#define ICPU_INTR_TRIGGER_RSZ 0x4 > + > +#define ICPU_INTR_FORCE 0x7c > + > +#define ICPU_INTR_STICKY 0x80 > + > +#define ICPU_INTR_BYPASS 0x84 > + > +#define ICPU_INTR_ENA 0x88 > + > +#define ICPU_INTR_ENA_CLR 0x8c > + > +#define ICPU_INTR_ENA_SET 0x90 > + > +#define ICPU_INTR_IDENT 0x94 > + > +#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) > +#define ICPU_DST_INTR_MAP_RSZ 0x4 > + > +#define ICPU_DST_INTR_IDENT 0xa8 > +#define ICPU_DST_INTR_IDENT_RSZ 0x4 > + > +#define ICPU_EXT_SRC_INTR_POL 0xb8 > + > +#define ICPU_EXT_DST_INTR_POL 0xbc > + > +#define ICPU_EXT_DST_INTR_DRV 0xc0 > + > +#define ICPU_DEV_INTR_POL 0xc4 > + > +#define ICPU_DEV_INTR_RAW 0xc8 > + > +#define ICPU_DEV_INTR_TRIGGER 0xcc > +#define ICPU_DEV_INTR_TRIGGER_RSZ 0x4 > + > +#define ICPU_DEV_INTR_STICKY 0xd4 > + > +#define ICPU_DEV_INTR_BYPASS 0xd8 > + > +#define ICPU_DEV_INTR_ENA 0xdc > + > +#define ICPU_DEV_INTR_IDENT 0xe0 > + > +#define ICPU_WDT 0xe4 > + > +#define ICPU_WDT_WDT_STATUS BIT(9) > +#define ICPU_WDT_WDT_ENABLE BIT(8) > +#define ICPU_WDT_WDT_LOCK(x) ((x) & GENMASK(7, 0)) > +#define ICPU_WDT_WDT_LOCK_M GENMASK(7, 0) > + > +#define ICPU_TIMER_TICK_DIV 0xe8 > + > +#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) > +#define ICPU_TIMER_VALUE_RSZ 0x4 > + > +#define ICPU_TIMER_RELOAD_VALUE 0xf8 > +#define ICPU_TIMER_RELOAD_VALUE_RSZ 0x4 > + > +#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) > +#define ICPU_TIMER_CTRL_RSZ 0x4 > + > +#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3) > +#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2) > +#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1) > +#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0) > + > +#define ICPU_MEMCTRL_CTRL 0x110 > + > +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) > +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2) > +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) > +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) > + > +#define ICPU_MEMCTRL_CFG 0x114 > + > +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) > +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) > +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) > +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) > +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) > +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_STAT 0x118 > + > +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) > +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) > +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) > +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) > + > +#define ICPU_MEMCTRL_REF_PERIOD 0x11c > + > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_ZQCAL 0x120 > + > +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1) > +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0) > + > +#define ICPU_MEMCTRL_TIMING0 0x124 > + > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING1 0x128 > + > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING2 0x12c > + > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_TIMING3 0x130 > + > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING4 0x134 > + > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0) > + > +#define ICPU_MEMCTRL_MR0_VAL 0x138 > + > +#define ICPU_MEMCTRL_MR1_VAL 0x13c > + > +#define ICPU_MEMCTRL_MR2_VAL 0x140 > + > +#define ICPU_MEMCTRL_MR3_VAL 0x144 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL 0x148 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) > + > +#define ICPU_MEMCTRL_DFT 0x14c > + > +#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7) > +#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6) > +#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5) > +#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4) > +#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1)) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1) > +#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0) > + > +#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x)) > +#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4 > + > +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) > + > +#define ICPU_MEMCTRL_DQS_AUTO 0x158 > +#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4 > + > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6)) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0) > + > +#define ICPU_MEMPHY_CFG 0x160 > + > +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) > +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) > +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) > +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) > +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) > +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) > +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) > +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) > +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) > +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) > +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0) > + > +#define ICPU_MEMPHY_DFT 0x164 > + > +#define ICPU_MEMPHY_DFT_PHY_DLL_BYPASS BIT(0) > + > +#define ICPU_MEMPHY_DLLCFG0 0x168 > +#define ICPU_MEMPHY_DLLCFG0_RSZ 0x4 > + > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6(x) (((x) << 30) & GENMASK(31, 30)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6_M GENMASK(31, 30) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6_X(x) (((x) & GENMASK(31, 30)) >> 30) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_LOCK_DET_EN BIT(29) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5(x) (((x) << 27) & GENMASK(28, 27)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5_M GENMASK(28, 27) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5_X(x) (((x) & GENMASK(28, 27)) >> 27) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3(x) (((x) << 24) & GENMASK(26, 24)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3_M GENMASK(26, 24) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3_X(x) (((x) & GENMASK(26, 24)) >> 24) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES4 BIT(23) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2(x) (((x) << 20) & GENMASK(22, 20)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2_M GENMASK(22, 20) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2_X(x) (((x) & GENMASK(22, 20)) >> 20) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES3 BIT(19) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1(x) (((x) << 16) & GENMASK(18, 16)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1_M GENMASK(18, 16) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES2 BIT(15) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0_M GENMASK(14, 12) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES1 BIT(11) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A(x) (((x) << 9) & GENMASK(10, 9)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A_M GENMASK(10, 9) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A_X(x) (((x) & GENMASK(10, 9)) >> 9) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D(x) (((x) << 6) & GENMASK(8, 6)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D_M GENMASK(8, 6) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_EN BIT(5) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM(x) (((x) << 2) & GENMASK(4, 2)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM_M GENMASK(4, 2) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM_X(x) (((x) & GENMASK(4, 2)) >> 2) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES0(x) ((x) & GENMASK(1, 0)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES0_M GENMASK(1, 0) > + > +#define ICPU_MEMPHY_DLLCFG1 0x174 > +#define ICPU_MEMPHY_DLLCFG1_RSZ 0x4 > + > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES9 BIT(19) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_TEST_HIZB_A BIT(18) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8(x) (((x) << 12) & GENMASK(17, 12)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8_M GENMASK(17, 12) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM(x) (((x) << 9) & GENMASK(11, 9)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM_M GENMASK(11, 9) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM_X(x) (((x) & GENMASK(11, 9)) >> 9) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM(x) (((x) << 6) & GENMASK(8, 6)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM_M GENMASK(8, 6) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES7(x) ((x) & GENMASK(5, 0)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES7_M GENMASK(5, 0) > + > +#define ICPU_MEMPHY_DQ_DLY_TRM 0x180 > +#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 > + > +#define ICPU_MEMPHY_ZCAL 0x188 > + > +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_STAT 0x18c > + > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_OVR 0x190 > + > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA(x) (((x) << 12) & GENMASK(31, 12)) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA_M GENMASK(31, 12) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA_X(x) (((x) & GENMASK(31, 12)) >> 12) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_ENACLR_DIS BIT(2) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_ZCOMP BIT(1) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_ENA BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_FORCE 0x194 > + > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL_M GENMASK(3, 2) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZQ_OFF BIT(1) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ENA BIT(0) > + > +#define ICPU_TWI_CONFIG 0x198 > + > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD(x) (((x) << 1) & GENMASK(8, 1)) > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD_M GENMASK(8, 1) > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD_X(x) (((x) & GENMASK(8, 1)) >> 1) > +#define ICPU_TWI_CONFIG_TWI_DELAY_ENABLE BIT(0) > + > +#define ICPU_TWI_SPIKE_FILTER_CFG 0x19c > + > +#define ICPU_FDMA_DCB_LLP 0x1a0 > +#define ICPU_FDMA_DCB_LLP_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAP 0x1c8 > +#define ICPU_FDMA_DCB_DATAP_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAL 0x1f0 > +#define ICPU_FDMA_DCB_DATAL_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAL_TOKEN BIT(17) > +#define ICPU_FDMA_DCB_DATAL_DATAL(x) ((x) & GENMASK(15, 0)) > +#define ICPU_FDMA_DCB_DATAL_DATAL_M GENMASK(15, 0) > + > +#define ICPU_FDMA_DCB_STAT 0x218 > +#define ICPU_FDMA_DCB_STAT_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_STAT_BLOCKO(x) (((x) << 20) & GENMASK(31, 20)) > +#define ICPU_FDMA_DCB_STAT_BLOCKO_M GENMASK(31, 20) > +#define ICPU_FDMA_DCB_STAT_BLOCKO_X(x) (((x) & GENMASK(31, 20)) >> 20) > +#define ICPU_FDMA_DCB_STAT_PD BIT(19) > +#define ICPU_FDMA_DCB_STAT_ABORT BIT(18) > +#define ICPU_FDMA_DCB_STAT_EOF BIT(17) > +#define ICPU_FDMA_DCB_STAT_SOF BIT(16) > +#define ICPU_FDMA_DCB_STAT_BLOCKL(x) ((x) & GENMASK(15, 0)) > +#define ICPU_FDMA_DCB_STAT_BLOCKL_M GENMASK(15, 0) > + > +#define ICPU_FDMA_DCB_LLP_PREV 0x240 > +#define ICPU_FDMA_DCB_LLP_PREV_RSZ 0x4 > + > +#define ICPU_FDMA_CH_STAT 0x268 > + > +#define ICPU_FDMA_CH_SAFE 0x26c > + > +#define ICPU_FDMA_CH_ACTIVATE 0x270 > + > +#define ICPU_FDMA_CH_DISABLE 0x274 > + > +#define ICPU_FDMA_CH_FORCEDIS 0x278 > + > +#define ICPU_FDMA_CH_CNT 0x27c > +#define ICPU_FDMA_CH_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM(x) (((x) << 16) & GENMASK(31, 16)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM_M GENMASK(31, 16) > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM_X(x) (((x) & GENMASK(31, 16)) >> 16) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB_M GENMASK(15, 8) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_FDMA_CH_CNT_CH_CNT_SIG(x) ((x) & GENMASK(7, 0)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_SIG_M GENMASK(7, 0) > + > +#define ICPU_FDMA_CH_INJ_CNT 0x2a4 > +#define ICPU_FDMA_CH_INJ_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_CH_INJ_TICK_RLD 0x2c4 > +#define ICPU_FDMA_CH_INJ_TICK_RLD_RSZ 0x4 > + > +#define ICPU_FDMA_CH_INJ_TICK_CNT 0x2e4 > +#define ICPU_FDMA_CH_INJ_TICK_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_EVT_ERR 0x304 > + > +#define ICPU_FDMA_EVT_ERR_CODE 0x308 > + > +#define ICPU_FDMA_INTR_LLP 0x30c > + > +#define ICPU_FDMA_INTR_LLP_ENA 0x310 > + > +#define ICPU_FDMA_INTR_FRM 0x314 > + > +#define ICPU_FDMA_INTR_FRM_ENA 0x318 > + > +#define ICPU_FDMA_INTR_SIG 0x31c > + > +#define ICPU_FDMA_INTR_SIG_ENA 0x320 > + > +#define ICPU_FDMA_INTR_ENA 0x324 > + > +#define ICPU_FDMA_INTR_IDENT 0x328 > + > +#define ICPU_FDMA_CH_CFG 0x32c > +#define ICPU_FDMA_CH_CFG_RSZ 0x4 > + > +#define ICPU_FDMA_CH_CFG_STAT_IN_DATA_ENA BIT(7) > +#define ICPU_FDMA_CH_CFG_CH_INJ_GRP BIT(6) > +#define ICPU_FDMA_CH_CFG_CH_PRIO(x) (((x) << 2) & GENMASK(5, 2)) > +#define ICPU_FDMA_CH_CFG_CH_PRIO_M GENMASK(5, 2) > +#define ICPU_FDMA_CH_CFG_CH_PRIO_X(x) (((x) & GENMASK(5, 2)) >> 2) > +#define ICPU_FDMA_CH_CFG_DONE_STOP_ENA BIT(1) > +#define ICPU_FDMA_CH_CFG_DONEEOF_STOP_ENA BIT(0) > + > +#define ICPU_FDMA_GCFG 0x354 > + > +#define ICPU_FDMA_GCFG_FRM_AT_OFF BIT(12) > +#define ICPU_FDMA_GCFG_INJ_RF_WM(x) (((x) << 7) & GENMASK(11, 7)) > +#define ICPU_FDMA_GCFG_INJ_RF_WM_M GENMASK(11, 7) > +#define ICPU_FDMA_GCFG_INJ_RF_WM_X(x) (((x) & GENMASK(11, 7)) >> 7) > +#define ICPU_FDMA_GCFG_XTR_RF_WM(x) (((x) << 3) & GENMASK(6, 3)) > +#define ICPU_FDMA_GCFG_XTR_RF_WM_M GENMASK(6, 3) > +#define ICPU_FDMA_GCFG_XTR_RF_WM_X(x) (((x) & GENMASK(6, 3)) >> 3) > +#define ICPU_FDMA_GCFG_XTR_AVAIL_EXT_DIS BIT(2) > +#define ICPU_FDMA_GCFG_XTR_PRIO_BP_DIS BIT(1) > +#define ICPU_FDMA_GCFG_PD_IGNORE BIT(0) > + > +#define ICPU_FDMA_GSTAT 0x358 > + > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH(x) (((x) << 5) & GENMASK(10, 5)) > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH_M GENMASK(10, 5) > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH_X(x) (((x) & GENMASK(10, 5)) >> 5) > +#define ICPU_FDMA_GSTAT_XTR_RF_HIGH(x) ((x) & GENMASK(4, 0)) > +#define ICPU_FDMA_GSTAT_XTR_RF_HIGH_M GENMASK(4, 0) > + > +#define ICPU_FDMA_IDLECNT 0x35c > + > +#define ICPU_FDMA_CONST 0x360 > + > +#define ICPU_FDMA_CONST_CH_INJ_CNT(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_FDMA_CONST_CH_INJ_CNT_M GENMASK(15, 8) > +#define ICPU_FDMA_CONST_CH_INJ_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_FDMA_CONST_CH_XTR_CNT(x) ((x) & GENMASK(7, 0)) > +#define ICPU_FDMA_CONST_CH_XTR_CNT_M GENMASK(7, 0) > + > +#define ICPU_PCIE_CTRL 0x364 > + > +#define ICPU_PCIE_CTRL_POWERUP BIT(0) > + > +#define ICPU_PCIE_CFG 0x368 > + > +#define ICPU_PCIE_CFG_CG_DIS BIT(5) > +#define ICPU_PCIE_CFG_MEM_CG_DIS BIT(4) > +#define ICPU_PCIE_CFG_CONF_REQ_RETRY_ENA BIT(3) > +#define ICPU_PCIE_CFG_PCIE_BAR_WR_ENA BIT(2) > +#define ICPU_PCIE_CFG_LTSSM_DIS BIT(1) > +#define ICPU_PCIE_CFG_MEM_RING_CORE_ENA BIT(0) > + > +#define ICPU_PCIE_STAT 0x36c > + > +#define ICPU_PCIE_STAT_SLV_ERROR_REPLY BIT(12) > +#define ICPU_PCIE_STAT_LTSSM_STATE(x) (((x) << 6) & GENMASK(11, 6)) > +#define ICPU_PCIE_STAT_LTSSM_STATE_M GENMASK(11, 6) > +#define ICPU_PCIE_STAT_LTSSM_STATE_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define ICPU_PCIE_STAT_LINK_STATE(x) (((x) << 3) & GENMASK(5, 3)) > +#define ICPU_PCIE_STAT_LINK_STATE_M GENMASK(5, 3) > +#define ICPU_PCIE_STAT_LINK_STATE_X(x) (((x) & GENMASK(5, 3)) >> 3) > +#define ICPU_PCIE_STAT_PM_STATE(x) ((x) & GENMASK(2, 0)) > +#define ICPU_PCIE_STAT_PM_STATE_M GENMASK(2, 0) > + > +#define ICPU_PCIE_AUX_CFG 0x370 > + > +#define ICPU_PCIE_AUX_CFG_AUX_POWER_VAL BIT(0) > + > +#define ICPU_PCIE_DBG_STAT 0x374 > + > +#define ICPU_PCIE_DBG_STAT_TBI_RX_CE BIT(14) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_LOS BIT(13) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_SDET BIT(12) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA(x) (((x) << 2) & GENMASK(11, 2)) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA_M GENMASK(11, 2) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA_X(x) (((x) & GENMASK(11, 2)) >> 2) > +#define ICPU_PCIE_DBG_STAT_PM_L2_EXIT BIT(1) > +#define ICPU_PCIE_DBG_STAT_DATA_LINK_LAYER_UP BIT(0) > + > +#define ICPU_PCIEMST_REPLY_INFO 0x378 > + > +#define ICPU_PCIEMST_BAR1_OFFSET 0x37c > + > +#define ICPU_PCIEMST_BAR1_MASK 0x380 > + > +#define ICPU_PCIEMST_BAR2_OFFSET 0x384 > + > +#define ICPU_PCIEMST_BAR2_MASK 0x388 > + > +#define ICPU_PCIESLV_FDMA 0x38c > + > +#define ICPU_PCIESLV_FDMA_FDMA_TC(x) (((x) << 4) & GENMASK(6, 4)) > +#define ICPU_PCIESLV_FDMA_FDMA_TC_M GENMASK(6, 4) > +#define ICPU_PCIESLV_FDMA_FDMA_TC_X(x) (((x) & GENMASK(6, 4)) >> 4) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR_M GENMASK(3, 2) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_PCIESLV_FDMA_FDMA_OFFSET(x) ((x) & GENMASK(1, 0)) > +#define ICPU_PCIESLV_FDMA_FDMA_OFFSET_M GENMASK(1, 0) > + > +#define ICPU_PCIESLV_SBA 0x390 > + > +#define ICPU_PCIESLV_SBA_SBA_BE(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_PCIESLV_SBA_SBA_BE_M GENMASK(27, 24) > +#define ICPU_PCIESLV_SBA_SBA_BE_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_PCIESLV_SBA_SBA_RESERVED1 BIT(23) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE(x) (((x) << 15) & GENMASK(22, 15)) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE_M GENMASK(22, 15) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE_X(x) (((x) & GENMASK(22, 15)) >> 15) > +#define ICPU_PCIESLV_SBA_SBA_TC(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_PCIESLV_SBA_SBA_TC_M GENMASK(14, 12) > +#define ICPU_PCIESLV_SBA_SBA_TC_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_PCIESLV_SBA_SBA_ATTR(x) (((x) << 10) & GENMASK(11, 10)) > +#define ICPU_PCIESLV_SBA_SBA_ATTR_M GENMASK(11, 10) > +#define ICPU_PCIESLV_SBA_SBA_ATTR_X(x) (((x) & GENMASK(11, 10)) >> 10) > +#define ICPU_PCIESLV_SBA_SBA_TD BIT(9) > +#define ICPU_PCIESLV_SBA_SBA_EP BIT(8) > +#define ICPU_PCIESLV_SBA_SBA_RESERVED0 BIT(7) > +#define ICPU_PCIESLV_SBA_SBA_TYPE(x) (((x) << 2) & GENMASK(6, 2)) > +#define ICPU_PCIESLV_SBA_SBA_TYPE_M GENMASK(6, 2) > +#define ICPU_PCIESLV_SBA_SBA_TYPE_X(x) (((x) & GENMASK(6, 2)) >> 2) > +#define ICPU_PCIESLV_SBA_SBA_OFFSET(x) ((x) & GENMASK(1, 0)) > +#define ICPU_PCIESLV_SBA_SBA_OFFSET_M GENMASK(1, 0) > + > +#define ICPU_PCIEPCS_CFG 0x394 > + > +#define ICPU_PCIEPCS_CFG_TXRX_DETECT BIT(22) > +#define ICPU_PCIEPCS_CFG_SDETCOM_PERM BIT(21) > +#define ICPU_PCIEPCS_CFG_SDETCOM_DIS BIT(20) > +#define ICPU_PCIEPCS_CFG_BEACON_FORCE BIT(19) > +#define ICPU_PCIEPCS_CFG_RXRST_FORCE BIT(18) > +#define ICPU_PCIEPCS_CFG_RXRST_VAL BIT(17) > +#define ICPU_PCIEPCS_CFG_TXRST_FORCE BIT(16) > +#define ICPU_PCIEPCS_CFG_TXRST_VAL BIT(15) > +#define ICPU_PCIEPCS_CFG_RXSDET_XOR BIT(14) > +#define ICPU_PCIEPCS_CFG_RXSDET_FORCE BIT(13) > +#define ICPU_PCIEPCS_CFG_RXINV_ENA BIT(12) > +#define ICPU_PCIEPCS_CFG_RXSWAP_ENA BIT(11) > +#define ICPU_PCIEPCS_CFG_TXSWAP_ENA BIT(10) > +#define ICPU_PCIEPCS_CFG_IDLE_DATA_DIS BIT(9) > +#define ICPU_PCIEPCS_CFG_IDLE_DIS BIT(8) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY(x) (((x) << 5) & GENMASK(7, 5)) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY_M GENMASK(7, 5) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define ICPU_PCIEPCS_CFG_RXLP_FORCE BIT(4) > +#define ICPU_PCIEPCS_CFG_TXLP_FORCE BIT(3) > +#define ICPU_PCIEPCS_CFG_WAKE_POL BIT(2) > +#define ICPU_PCIEPCS_CFG_WAKE_OE BIT(1) > +#define ICPU_PCIEPCS_CFG_BEACON_DIS BIT(0) > + > +#define ICPU_PCIEPCS_BEACON 0x398 > + > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL(x) (((x) << 16) & GENMASK(25, 16)) > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL_M GENMASK(25, 16) > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL_X(x) (((x) & GENMASK(25, 16)) >> 16) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DIS BIT(15) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DLY(x) ((x) & GENMASK(14, 0)) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DLY_M GENMASK(14, 0) > + > +#define ICPU_PCIE_INTR 0x39c > + > +#define ICPU_PCIE_INTR_INTR_LTSSM_STATE BIT(4) > +#define ICPU_PCIE_INTR_INTR_LINK_STATE BIT(3) > +#define ICPU_PCIE_INTR_INTR_BAR1_WR BIT(2) > +#define ICPU_PCIE_INTR_INTR_BAR1_RD BIT(1) > +#define ICPU_PCIE_INTR_INTR_PM_STATE BIT(0) > + > +#define ICPU_PCIE_INTR_ENA 0x3a0 > + > +#define ICPU_PCIE_INTR_ENA_INTR_LTSSM_STATE_ENA BIT(4) > +#define ICPU_PCIE_INTR_ENA_INTR_LINK_STATE_ENA BIT(3) > +#define ICPU_PCIE_INTR_ENA_INTR_BAR1_WR_ENA BIT(2) > +#define ICPU_PCIE_INTR_ENA_INTR_BAR1_RD_ENA BIT(1) > +#define ICPU_PCIE_INTR_ENA_INTR_PM_STATE_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_IDENT 0x3a4 > + > +#define ICPU_PCIE_INTR_IDENT_INTR_LTSSM_STATE_IDENT BIT(4) > +#define ICPU_PCIE_INTR_IDENT_INTR_LINK_STATE_IDENT BIT(3) > +#define ICPU_PCIE_INTR_IDENT_INTR_BAR1_WR_IDENT BIT(2) > +#define ICPU_PCIE_INTR_IDENT_INTR_BAR1_RD_IDENT BIT(1) > +#define ICPU_PCIE_INTR_IDENT_INTR_PM_STATE_IDENT BIT(0) > + > +#define ICPU_PCIE_INTR_COMMON_CFG 0x3a8 > + > +#define ICPU_PCIE_INTR_COMMON_CFG_WAKEUP_ON_INTR_DIS BIT(2) > +#define ICPU_PCIE_INTR_COMMON_CFG_LEGACY_MODE_INTR_SEL BIT(1) > +#define ICPU_PCIE_INTR_COMMON_CFG_PCIE_INTR_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_CFG 0x3ac > +#define ICPU_PCIE_INTR_CFG_RSZ 0x4 > + > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER(x) (((x) << 15) & GENMASK(17, 15)) > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER_M GENMASK(17, 15) > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER_X(x) (((x) & GENMASK(17, 15)) >> 15) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS_M GENMASK(14, 12) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL(x) (((x) << 7) & GENMASK(11, 7)) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL_M GENMASK(11, 7) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL_X(x) (((x) & GENMASK(11, 7)) >> 7) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL(x) (((x) << 2) & GENMASK(6, 2)) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL_M GENMASK(6, 2) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL_X(x) (((x) & GENMASK(6, 2)) >> 2) > +#define ICPU_PCIE_INTR_CFG_INTR_FALLING_ENA BIT(1) > +#define ICPU_PCIE_INTR_CFG_INTR_RISING_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_STAT 0x3b4 > +#define ICPU_PCIE_INTR_STAT_RSZ 0x4 > + > +#define ICPU_PCIE_INTR_STAT_INTR_PENDING_FALLING BIT(1) > +#define ICPU_PCIE_INTR_STAT_INTR_PENDING_RISING BIT(0) > + > +#define ICPU_MANUAL_XTR 0x4000 > + > +#define ICPU_MANUAL_INJ 0x8000 > + > +#define ICPU_MANUAL_CFG 0xc000 > + > +#define ICPU_MANUAL_CFG_XTR_FLUSH_DIS BIT(4) > +#define ICPU_MANUAL_CFG_INJ_SWAP_ENA BIT(3) > +#define ICPU_MANUAL_CFG_XTR_SWAP_ENA BIT(2) > +#define ICPU_MANUAL_CFG_INJ_ENA BIT(1) > +#define ICPU_MANUAL_CFG_XTR_ENA BIT(0) > + > +#define ICPU_MANUAL_INTR 0xc004 > + > +#define ICPU_MANUAL_INTR_INTR_INJ_RDY BIT(2) > +#define ICPU_MANUAL_INTR_INTR_XTR_ANY_RDY BIT(1) > +#define ICPU_MANUAL_INTR_INTR_XTR_SOF_RDY BIT(0) > + > +#define ICPU_MANUAL_INTR_ENA 0xc008 > + > +#define ICPU_MANUAL_INTR_ENA_INTR_INJ_RDY_ENA BIT(2) > +#define ICPU_MANUAL_INTR_ENA_INTR_XTR_ANY_RDY_ENA BIT(1) > +#define ICPU_MANUAL_INTR_ENA_INTR_XTR_SOF_RDY_ENA BIT(0) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h > new file mode 100644 > index 0000000000..b0b09f4d21 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h > @@ -0,0 +1,247 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_ICPU_CFG_H_ > +#define _MSCC_OCELOT_ICPU_CFG_H_ > + > +#define ICPU_GPR(x) (0x4 * (x)) > +#define ICPU_GPR_RSZ 0x4 > + > +#define ICPU_RESET 0x20 > + > +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) > +#define ICPU_RESET_CORE_RST_PROTECT BIT(2) > +#define ICPU_RESET_CORE_RST_FORCE BIT(1) > +#define ICPU_RESET_MEM_RST_FORCE BIT(0) > + > +#define ICPU_GENERAL_CTRL 0x24 > + > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14) > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13) > +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12) > +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8) > +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3) > +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2) > +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1) > +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) > + > +#define ICPU_SPI_MST_CFG 0x3c > + > +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11) > +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) > +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) > + > + > +#define ICPU_SW_MODE 0x64 > + > +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) > +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12) > +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) > +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10) > +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) > +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) > +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0) > + > +#define ICPU_INTR_ENA 0x88 > + > +#define ICPU_INTR_IRQ0_ENA 0x98 > +#define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0) > + > +#define ICPU_MEMCTRL_CTRL 0x234 > + > +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) > +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2) > +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) > +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) > + > +#define ICPU_MEMCTRL_CFG 0x238 > + > +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) > +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) > +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) > +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) > +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) > +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_STAT 0x23C > + > +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) > +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) > +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) > +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) > + > +#define ICPU_MEMCTRL_REF_PERIOD 0x240 > + > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_TIMING0 0x248 > + > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING1 0x24c > + > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING2 0x250 > + > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_TIMING3 0x254 > + > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_MR0_VAL 0x258 > + > +#define ICPU_MEMCTRL_MR1_VAL 0x25c > + > +#define ICPU_MEMCTRL_MR2_VAL 0x260 > + > +#define ICPU_MEMCTRL_MR3_VAL 0x264 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL 0x268 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) > + > +#define ICPU_MEMCTRL_DQS_DLY(x) (0x270) > + > +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) > + > +#define ICPU_MEMPHY_CFG 0x278 > + > +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) > +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) > +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) > +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) > +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) > +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) > +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) > +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) > +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) > +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) > +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0) > +#define ICPU_MEMPHY_DQ_DLY_TRM 0x180 > +#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 > + > +#define ICPU_MEMPHY_ZCAL 0x294 > + > +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h > new file mode 100644 > index 0000000000..698e6808a4 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h > @@ -0,0 +1,35 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Microsemi Ocelot Switch driver > + * > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_H_ > +#define _MSCC_OCELOT_H_ > + > +#include > +#include > + > +/* > + * Target offset base(s) > + */ > +#define MSCC_IO_ORIGIN1_OFFSET 0x70000000 > +#define MSCC_IO_ORIGIN1_SIZE 0x00200000 > +#define MSCC_IO_ORIGIN2_OFFSET 0x71000000 > +#define MSCC_IO_ORIGIN2_SIZE 0x01000000 > +#ifndef MSCC_IO_OFFSET1 > +#define MSCC_IO_OFFSET1(offset) (MSCC_IO_ORIGIN1_OFFSET + offset) > +#endif > +#ifndef MSCC_IO_OFFSET2 > +#define MSCC_IO_OFFSET2(offset) (MSCC_IO_ORIGIN2_OFFSET + offset) > +#endif > +#define BASE_CFG 0x70000000 > +#define BASE_UART 0x70100000 > +#define BASE_DEVCPU_GCB 0x71070000 > + > +#define REG_OFFSET(t, o) ((volatile unsigned long *)(t + (o))) > +#define REG_CFG(x) REG_OFFSET(BASE_CFG, x) > +#define REG_GCB(x) REG_OFFSET(BASE_DEVCPU_GCB, x) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h > new file mode 100644 > index 0000000000..19f707a478 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h > @@ -0,0 +1,353 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ > +#define _MSCC_OCELOT_DEVCPU_GCB_H_ > + > +#define PERF_CHIP_ID 0x0 > + > +#define PERF_CHIP_ID_REV_ID(x) (((x) << 28) & GENMASK(31, 28)) > +#define PERF_CHIP_ID_REV_ID_M GENMASK(31, 28) > +#define PERF_CHIP_ID_REV_ID_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define PERF_CHIP_ID_PART_ID(x) (((x) << 12) & GENMASK(27, 12)) > +#define PERF_CHIP_ID_PART_ID_M GENMASK(27, 12) > +#define PERF_CHIP_ID_PART_ID_X(x) (((x) & GENMASK(27, 12)) >> 12) > +#define PERF_CHIP_ID_MFG_ID(x) (((x) << 1) & GENMASK(11, 1)) > +#define PERF_CHIP_ID_MFG_ID_M GENMASK(11, 1) > +#define PERF_CHIP_ID_MFG_ID_X(x) (((x) & GENMASK(11, 1)) >> 1) > +#define PERF_CHIP_ID_ONE BIT(0) > + > +#define PERF_GPR 0x4 > + > +#define PERF_SOFT_RST 0x8 > + > +#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2) > +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) > +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0) > + > +#define PERF_HW_CFG 0xc > + > +#define PERF_HW_CFG_DFT_STAT_ENA BIT(0) > + > +#define PERF_HW_STAT 0x10 > + > +#define PERF_HW_STAT_PLL0_CONF(x) (((x) << 1) & GENMASK(3, 1)) > +#define PERF_HW_STAT_PLL0_CONF_M GENMASK(3, 1) > +#define PERF_HW_STAT_PLL0_CONF_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define PERF_HW_STAT_MEM_FAIL BIT(0) > + > +#define PERF_FEA_STAT 0x14 > + > +#define PERF_FEA_DIS 0x18 > + > +#define PERF_SW_INTR 0x1c > + > +#define PERF_SW_INTR_SW1_INTR BIT(1) > +#define PERF_SW_INTR_SW0_INTR BIT(0) > + > +#define PERF_VA_CTRL 0x20 > + > +#define PERF_VA_CTRL_VA_SIZE(x) (((x) << 4) & GENMASK(5, 4)) > +#define PERF_VA_CTRL_VA_SIZE_M GENMASK(5, 4) > +#define PERF_VA_CTRL_VA_SIZE_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define PERF_VA_CTRL_VA_ERR(x) (((x) << 2) & GENMASK(3, 2)) > +#define PERF_VA_CTRL_VA_ERR_M GENMASK(3, 2) > +#define PERF_VA_CTRL_VA_ERR_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define PERF_VA_CTRL_VA_BUSY_RD BIT(1) > +#define PERF_VA_CTRL_VA_BUSY BIT(0) > + > +#define PERF_VA_ADDR 0x24 > + > +#define PERF_VA_DATA 0x28 > + > +#define PERF_VA_DATA_INCR 0x2c > + > +#define PERF_VA_DATA_INERT 0x30 > + > +#define PERF_GPIO_OUT_SET 0x34 > + > +#define PERF_GPIO_OUT_CLR 0x38 > + > +#define PERF_GPIO_OUT 0x3c > + > +#define PERF_GPIO_IN 0x40 > + > +#define PERF_GPIO_OE 0x44 > + > +#define PERF_GPIO_INTR 0x48 > + > +#define PERF_GPIO_INTR_ENA 0x4c > + > +#define PERF_GPIO_INTR_IDENT 0x50 > + > +#define PERF_GPIO_ALT(x) (0x54 + 4 * (x)) > +#define PERF_GPIO_ALT_RSZ 0x4 > + > +#define PERF_GPIO_SD_MAP 0x5c > +#define PERF_GPIO_SD_MAP_RSZ 0x4 > + > +#define PERF_MII_STATUS 0x9c > +#define PERF_MII_STATUS_GSZ 0x24 > + > +#define PERF_MII_STATUS_MIIM_SCAN_COMPLETE BIT(4) > +#define PERF_MII_STATUS_MIIM_STAT_BUSY BIT(3) > +#define PERF_MII_STATUS_MIIM_STAT_OPR_PEND BIT(2) > +#define PERF_MII_STATUS_MIIM_STAT_PENDING_RD BIT(1) > +#define PERF_MII_STATUS_MIIM_STAT_PENDING_WR BIT(0) > + > +#define PERF_MII_CFG_7226 0xa0 > +#define PERF_MII_CFG_7226_GSZ 0x24 > + > +#define PERF_MII_CFG_7226_MIIM_7226_CFG_FIELD BIT(9) > + > +#define PERF_MII_CMD 0xa4 > +#define PERF_MII_CMD_GSZ 0x24 > + > +#define PERF_MII_CMD_MIIM_CMD_VLD BIT(31) > +#define PERF_MII_CMD_MIIM_CMD_PHYAD(x) (((x) << 25) & GENMASK(29, 25)) > +#define PERF_MII_CMD_MIIM_CMD_PHYAD_M GENMASK(29, 25) > +#define PERF_MII_CMD_MIIM_CMD_PHYAD_X(x) (((x) & GENMASK(29, 25)) >> 25) > +#define PERF_MII_CMD_MIIM_CMD_REGAD(x) (((x) << 20) & GENMASK(24, 20)) > +#define PERF_MII_CMD_MIIM_CMD_REGAD_M GENMASK(24, 20) > +#define PERF_MII_CMD_MIIM_CMD_REGAD_X(x) (((x) & GENMASK(24, 20)) >> 20) > +#define PERF_MII_CMD_MIIM_CMD_WRDATA(x) (((x) << 4) & GENMASK(19, 4)) > +#define PERF_MII_CMD_MIIM_CMD_WRDATA_M GENMASK(19, 4) > +#define PERF_MII_CMD_MIIM_CMD_WRDATA_X(x) (((x) & GENMASK(19, 4)) >> 4) > +#define PERF_MII_CMD_MIIM_CMD_SINGLE_SCAN BIT(3) > +#define PERF_MII_CMD_MIIM_CMD_OPR_FIELD(x) (((x) << 1) & GENMASK(2, 1)) > +#define PERF_MII_CMD_MIIM_CMD_OPR_FIELD_M GENMASK(2, 1) > +#define PERF_MII_CMD_MIIM_CMD_OPR_FIELD_X(x) (((x) & GENMASK(2, 1)) >> 1) > +#define PERF_MII_CMD_MIIM_CMD_SCAN BIT(0) > + > +#define PERF_MII_DATA 0xa8 > +#define PERF_MII_DATA_GSZ 0x24 > + > +#define PERF_MII_DATA_MIIM_DATA_SUCCESS(x) (((x) << 16) & GENMASK(17, 16)) > +#define PERF_MII_DATA_MIIM_DATA_SUCCESS_M GENMASK(17, 16) > +#define PERF_MII_DATA_MIIM_DATA_SUCCESS_X(x) (((x) & GENMASK(17, 16)) >> 16) > +#define PERF_MII_DATA_MIIM_DATA_RDDATA(x) ((x) & GENMASK(15, 0)) > +#define PERF_MII_DATA_MIIM_DATA_RDDATA_M GENMASK(15, 0) > + > +#define PERF_MII_CFG 0xac > +#define PERF_MII_CFG_GSZ 0x24 > + > +#define PERF_MII_CFG_DEADLOCK_FIX_DIS BIT(11) > +#define PERF_MII_CFG_MIIM_ST_CFG_FIELD(x) (((x) << 9) & GENMASK(10, 9)) > +#define PERF_MII_CFG_MIIM_ST_CFG_FIELD_M GENMASK(10, 9) > +#define PERF_MII_CFG_MIIM_ST_CFG_FIELD_X(x) (((x) & GENMASK(10, 9)) >> 9) > +#define PERF_MII_CFG_MIIM_CFG_DBG BIT(8) > +#define PERF_MII_CFG_MIIM_CFG_PRESCALE(x) ((x) & GENMASK(7, 0)) > +#define PERF_MII_CFG_MIIM_CFG_PRESCALE_M GENMASK(7, 0) > + > +#define PERF_MII_SCAN_0 0xb0 > +#define PERF_MII_SCAN_0_GSZ 0x24 > + > +#define PERF_MII_SCAN_0_MIIM_SCAN_PHYADHI(x) (((x) << 5) & GENMASK(9, 5)) > +#define PERF_MII_SCAN_0_MIIM_SCAN_PHYADHI_M GENMASK(9, 5) > +#define PERF_MII_SCAN_0_MIIM_SCAN_PHYADHI_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define PERF_MII_SCAN_0_MIIM_SCAN_PHYADLO(x) ((x) & GENMASK(4, 0)) > +#define PERF_MII_SCAN_0_MIIM_SCAN_PHYADLO_M GENMASK(4, 0) > + > +#define PERF_MII_SCAN_1 0xb4 > +#define PERF_MII_SCAN_1_GSZ 0x24 > + > +#define PERF_MII_SCAN_1_MIIM_SCAN_MASK(x) (((x) << 16) & GENMASK(31, 16)) > +#define PERF_MII_SCAN_1_MIIM_SCAN_MASK_M GENMASK(31, 16) > +#define PERF_MII_SCAN_1_MIIM_SCAN_MASK_X(x) (((x) & GENMASK(31, 16)) >> 16) > +#define PERF_MII_SCAN_1_MIIM_SCAN_EXPECT(x) ((x) & GENMASK(15, 0)) > +#define PERF_MII_SCAN_1_MIIM_SCAN_EXPECT_M GENMASK(15, 0) > + > +#define PERF_MII_SCAN_RES 0xb8 > +#define PERF_MII_SCAN_RES_GSZ 0x24 > + > +#define PERF_MII_SCAN_RES_VLD 0xbc > +#define PERF_MII_SCAN_RES_VLD_GSZ 0x24 > + > +#define PERF_MII_SCAN_RES_STICKY 0xe4 > +#define PERF_MII_SCAN_RES_STICKY_RSZ 0x4 > + > +#define PERF_MII_SLAVE_CFG 0xec > + > +#define PERF_MII_SLAVE_CFG_SPIKE_FILTER_CFG(x) (((x) << 1) & GENMASK(5, 1)) > +#define PERF_MII_SLAVE_CFG_SPIKE_FILTER_CFG_M GENMASK(5, 1) > +#define PERF_MII_SLAVE_CFG_SPIKE_FILTER_CFG_X(x) (((x) & GENMASK(5, 1)) >> 1) > +#define PERF_MII_SLAVE_CFG_SPIKE_FILTER_ENA BIT(0) > + > +#define PERF_PHY_CFG 0xf0 > + > +#define PERF_PHY_CFG_PHY_COMA BIT(12) > +#define PERF_PHY_CFG_PHY_ADDR(x) (((x) << 9) & GENMASK(11, 9)) > +#define PERF_PHY_CFG_PHY_ADDR_M GENMASK(11, 9) > +#define PERF_PHY_CFG_PHY_ADDR_X(x) (((x) & GENMASK(11, 9)) >> 9) > +#define PERF_PHY_CFG_PHY_RESET(x) (((x) << 5) & GENMASK(8, 5)) > +#define PERF_PHY_CFG_PHY_RESET_M GENMASK(8, 5) > +#define PERF_PHY_CFG_PHY_RESET_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define PERF_PHY_CFG_PHY_COMMON_RESET BIT(4) > +#define PERF_PHY_CFG_PHY_ENA(x) ((x) & GENMASK(3, 0)) > +#define PERF_PHY_CFG_PHY_ENA_M GENMASK(3, 0) > + > +#define PERF_PHY_STAT 0xf4 > + > +#define PERF_PHY_STAT_PHY_COMA_OE BIT(22) > +#define PERF_PHY_STAT_PHY_COMA_O BIT(21) > +#define PERF_PHY_STAT_FAST_LINK_STATUS(x) (((x) << 17) & GENMASK(20, 17)) > +#define PERF_PHY_STAT_FAST_LINK_STATUS_M GENMASK(20, 17) > +#define PERF_PHY_STAT_FAST_LINK_STATUS_X(x) (((x) & GENMASK(20, 17)) >> 17) > +#define PERF_PHY_STAT_LINK_STAT_DUPLEX(x) (((x) << 13) & GENMASK(16, 13)) > +#define PERF_PHY_STAT_LINK_STAT_DUPLEX_M GENMASK(16, 13) > +#define PERF_PHY_STAT_LINK_STAT_DUPLEX_X(x) (((x) & GENMASK(16, 13)) >> 13) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_1000(x) (((x) << 9) & GENMASK(12, 9)) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_1000_M GENMASK(12, 9) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_1000_X(x) (((x) & GENMASK(12, 9)) >> 9) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_100(x) (((x) << 5) & GENMASK(8, 5)) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_100_M GENMASK(8, 5) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_100_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_10(x) (((x) << 1) & GENMASK(4, 1)) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_10_M GENMASK(4, 1) > +#define PERF_PHY_STAT_LINK_STAT_SPEED_10_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define PERF_PHY_STAT_SUPERVISOR_COMPLETE BIT(0) > + > +#define PERF_SIO_INPUT_DATA 0xf8 > +#define PERF_SIO_INPUT_DATA_RSZ 0x4 > + > +#define PERF_SIO_CFG 0x108 > + > +#define PERF_SIO_CFG_SIO_PWM_WINDOW(x) (((x) << 24) & GENMASK(31, 24)) > +#define PERF_SIO_CFG_SIO_PWM_WINDOW_M GENMASK(31, 24) > +#define PERF_SIO_CFG_SIO_PWM_WINDOW_X(x) (((x) & GENMASK(31, 24)) >> 24) > +#define PERF_SIO_CFG_SIO_REDUCED_GAP BIT(23) > +#define PERF_SIO_CFG_SIO_BMODE_1(x) (((x) << 21) & GENMASK(22, 21)) > +#define PERF_SIO_CFG_SIO_BMODE_1_M GENMASK(22, 21) > +#define PERF_SIO_CFG_SIO_BMODE_1_X(x) (((x) & GENMASK(22, 21)) >> 21) > +#define PERF_SIO_CFG_SIO_BMODE_0(x) (((x) << 19) & GENMASK(20, 19)) > +#define PERF_SIO_CFG_SIO_BMODE_0_M GENMASK(20, 19) > +#define PERF_SIO_CFG_SIO_BMODE_0_X(x) (((x) & GENMASK(20, 19)) >> 19) > +#define PERF_SIO_CFG_SIO_BLINK_RESET BIT(18) > +#define PERF_SIO_CFG_SIO_BURST_GAP_DIS BIT(17) > +#define PERF_SIO_CFG_SIO_BURST_GAP(x) (((x) << 12) & GENMASK(16, 12)) > +#define PERF_SIO_CFG_SIO_BURST_GAP_M GENMASK(16, 12) > +#define PERF_SIO_CFG_SIO_BURST_GAP_X(x) (((x) & GENMASK(16, 12)) >> 12) > +#define PERF_SIO_CFG_SIO_SINGLE_SHOT BIT(11) > +#define PERF_SIO_CFG_SIO_AUTO_REPEAT BIT(10) > +#define PERF_SIO_CFG_SIO_LD_POLARITY BIT(9) > +#define PERF_SIO_CFG_SIO_PORT_WIDTH(x) (((x) << 7) & GENMASK(8, 7)) > +#define PERF_SIO_CFG_SIO_PORT_WIDTH_M GENMASK(8, 7) > +#define PERF_SIO_CFG_SIO_PORT_WIDTH_X(x) (((x) & GENMASK(8, 7)) >> 7) > +#define PERF_SIO_CFG_SIO_REVERSE_OUTPUT BIT(6) > +#define PERF_SIO_CFG_SIO_REVERSE_INPUT BIT(5) > +#define PERF_SIO_CFG_SIO_GPIO_INTR_ENA(x) (((x) << 1) & GENMASK(4, 1)) > +#define PERF_SIO_CFG_SIO_GPIO_INTR_ENA_M GENMASK(4, 1) > +#define PERF_SIO_CFG_SIO_GPIO_INTR_ENA_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define PERF_SIO_CFG_SIO_MASTER_INTR_ENA BIT(0) > + > +#define PERF_SIO_CLOCK 0x10c > + > +#define PERF_SIO_CLOCK_SIO_CLK_FREQ(x) (((x) << 8) & GENMASK(19, 8)) > +#define PERF_SIO_CLOCK_SIO_CLK_FREQ_M GENMASK(19, 8) > +#define PERF_SIO_CLOCK_SIO_CLK_FREQ_X(x) (((x) & GENMASK(19, 8)) >> 8) > +#define PERF_SIO_CLOCK_SYS_CLK_PERIOD(x) ((x) & GENMASK(7, 0)) > +#define PERF_SIO_CLOCK_SYS_CLK_PERIOD_M GENMASK(7, 0) > + > +#define PERF_SIO_PORT_CFG 0x110 > +#define PERF_SIO_PORT_CFG_RSZ 0x4 > + > +#define PERF_SIO_PORT_CFG_BIT_SOURCE(x) (((x) << 12) & GENMASK(23, 12)) > +#define PERF_SIO_PORT_CFG_BIT_SOURCE_M GENMASK(23, 12) > +#define PERF_SIO_PORT_CFG_BIT_SOURCE_X(x) (((x) & GENMASK(23, 12)) >> 12) > +#define PERF_SIO_PORT_CFG_PWM_SOURCE(x) (((x) << 4) & GENMASK(11, 4)) > +#define PERF_SIO_PORT_CFG_PWM_SOURCE_M GENMASK(11, 4) > +#define PERF_SIO_PORT_CFG_PWM_SOURCE_X(x) (((x) & GENMASK(11, 4)) >> 4) > +#define PERF_SIO_PORT_CFG_BIT_POLARITY(x) ((x) & GENMASK(3, 0)) > +#define PERF_SIO_PORT_CFG_BIT_POLARITY_M GENMASK(3, 0) > + > +#define PERF_SIO_PORT_ENA 0x190 > + > +#define PERF_SIO_PWM_CFG 0x194 > +#define PERF_SIO_PWM_CFG_RSZ 0x4 > + > +#define PERF_SIO_INTR_POL 0x1a0 > +#define PERF_SIO_INTR_POL_RSZ 0x4 > + > +#define PERF_SIO_INTR_RAW 0x1b0 > +#define PERF_SIO_INTR_RAW_RSZ 0x4 > + > +#define PERF_SIO_INTR_TRIGGER0 0x1c0 > +#define PERF_SIO_INTR_TRIGGER0_RSZ 0x4 > + > +#define PERF_SIO_INTR_TRIGGER1 0x1d0 > +#define PERF_SIO_INTR_TRIGGER1_RSZ 0x4 > + > +#define PERF_SIO_INTR 0x1e0 > +#define PERF_SIO_INTR_RSZ 0x4 > + > +#define PERF_SIO_INTR_ENA 0x1f0 > + > +#define PERF_SIO_INTR_IDENT 0x1f4 > +#define PERF_SIO_INTR_IDENT_RSZ 0x4 > + > +#define PERF_FAN_CFG 0x204 > + > +#define PERF_FAN_CFG_DUTY_CYCLE(x) (((x) << 16) & GENMASK(23, 16)) > +#define PERF_FAN_CFG_DUTY_CYCLE_M GENMASK(23, 16) > +#define PERF_FAN_CFG_DUTY_CYCLE_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define PERF_FAN_CFG_CLK_CYCLES_10US(x) (((x) << 4) & GENMASK(15, 4)) > +#define PERF_FAN_CFG_CLK_CYCLES_10US_M GENMASK(15, 4) > +#define PERF_FAN_CFG_CLK_CYCLES_10US_X(x) (((x) & GENMASK(15, 4)) >> 4) > +#define PERF_FAN_CFG_INV_POL BIT(3) > +#define PERF_FAN_CFG_GATE_ENA BIT(2) > +#define PERF_FAN_CFG_PWM_OPEN_COL_ENA BIT(1) > +#define PERF_FAN_CFG_FAN_STAT_CFG BIT(0) > + > +#define PERF_PWM_FREQ 0x208 > + > +#define PERF_FAN_CNT 0x20c > + > +#define PERF_MEMITGR_CTRL 0x210 > + > +#define PERF_MEMITGR_CTRL_ACTIVATE BIT(0) > + > +#define PERF_MEMITGR_STAT 0x214 > + > +#define PERF_MEMITGR_STAT_INDICATION_OVF BIT(5) > +#define PERF_MEMITGR_STAT_INDICATION BIT(4) > +#define PERF_MEMITGR_STAT_MODE_LISTEN BIT(3) > +#define PERF_MEMITGR_STAT_MODE_DETECT BIT(2) > +#define PERF_MEMITGR_STAT_MODE_IDLE BIT(1) > +#define PERF_MEMITGR_STAT_MODE_BUSY BIT(0) > + > +#define PERF_MEMITGR_INFO 0x218 > + > +#define PERF_MEMITGR_INFO_MEM_ERR BIT(31) > +#define PERF_MEMITGR_INFO_MEM_COR BIT(30) > +#define PERF_MEMITGR_INFO_MEM_ERR_OVF BIT(29) > +#define PERF_MEMITGR_INFO_MEM_COR_OVF BIT(28) > +#define PERF_MEMITGR_INFO_MEM_ADDR(x) ((x) & GENMASK(27, 0)) > +#define PERF_MEMITGR_INFO_MEM_ADDR_M GENMASK(27, 0) > + > +#define PERF_MEMITGR_IDX 0x21c > + > +#define PERF_MEMITGR_DIV 0x220 > + > +#define PERF_MEMITGR_DBG 0x224 > + > +#define PERF_MEMITGR_DBG_MEM_DIV_SENSE BIT(9) > +#define PERF_MEMITGR_DBG_FORCE_INTR BIT(8) > +#define PERF_MEMITGR_DBG_SYNC_IN BIT(7) > +#define PERF_MEMITGR_DBG_ENA_IN BIT(6) > +#define PERF_MEMITGR_DBG_DATA_IN BIT(5) > +#define PERF_MEMITGR_DBG_INTR_IN BIT(4) > +#define PERF_MEMITGR_DBG_SYNC_OUT BIT(3) > +#define PERF_MEMITGR_DBG_ENA_OUT BIT(2) > +#define PERF_MEMITGR_DBG_FORCE_ENA BIT(1) > +#define PERF_MEMITGR_DBG_DETECT_ENA BIT(0) > + > +#define PERF_VRAP_ACCESS_STAT 0x228 > + > +#define PERF_VRAP_ACCESS_STAT_FRM_RECV_STICKY BIT(3) > +#define PERF_VRAP_ACCESS_STAT_CMD_INVALID_STICKY BIT(2) > +#define PERF_VRAP_ACCESS_STAT_FRM_INVALID_STICKY BIT(1) > +#define PERF_VRAP_ACCESS_STAT_REPLY_ABORT_STICKY BIT(0) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h > new file mode 100644 > index 0000000000..5a5fe079e1 > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h > @@ -0,0 +1,884 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_ICPU_CFG_H_ > +#define _MSCC_OCELOT_ICPU_CFG_H_ > + > +#define ICPU_GPR(x) (0x4 * (x)) > +#define ICPU_GPR_RSZ 0x4 > + > +#define ICPU_RESET 0x20 > + > +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) > +#define ICPU_RESET_CORE_RST_PROTECT BIT(2) > +#define ICPU_RESET_CORE_RST_FORCE BIT(1) > +#define ICPU_RESET_MEM_RST_FORCE BIT(0) > + > +#define ICPU_GENERAL_CTRL 0x24 > + > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14) > +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13) > +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12) > +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10) > +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8) > +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7) > +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4) > +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3) > +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2) > +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1) > +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) > + > +#define ICPU_GENERAL_STAT 0x28 > + > +#define ICPU_GENERAL_STAT_PI_SLV_WR_ERR BIT(9) > +#define ICPU_GENERAL_STAT_PI_SLV_RD_ERR BIT(8) > +#define ICPU_GENERAL_STAT_VCORE_CFG(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_GENERAL_STAT_VCORE_CFG_M GENMASK(7, 4) > +#define ICPU_GENERAL_STAT_VCORE_CFG_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_GENERAL_STAT_REG_IF_ERR(x) (((x) << 1) & GENMASK(3, 1)) > +#define ICPU_GENERAL_STAT_REG_IF_ERR_M GENMASK(3, 1) > +#define ICPU_GENERAL_STAT_REG_IF_ERR_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define ICPU_GENERAL_STAT_CPU_SLEEP BIT(0) > + > +#define ICPU_PI_MST_CFG 0x2c > + > +#define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7) > +#define ICPU_PI_MST_CFG_CLK_POL BIT(6) > +#define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5) > +#define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) > +#define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0) > + > +#define ICPU_PI_MST_CTRL 0x30 > + > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_XFER_ENA BIT(22) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_ENA BIT(21) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT(x) (((x) << 18) & GENMASK(20, 18)) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_M GENMASK(20, 18) > +#define ICPU_PI_MST_CTRL_DEVICE_PACED_TIMEOUT_X(x) (((x) & GENMASK(20, 18)) >> 18) > +#define ICPU_PI_MST_CTRL_CS_TRISTATE_CTRL BIT(17) > +#define ICPU_PI_MST_CTRL_DONE_POL BIT(16) > +#define ICPU_PI_MST_CTRL_SMPL_ON_DONE BIT(15) > +#define ICPU_PI_MST_CTRL_WAITCC(x) (((x) << 7) & GENMASK(14, 7)) > +#define ICPU_PI_MST_CTRL_WAITCC_M GENMASK(14, 7) > +#define ICPU_PI_MST_CTRL_WAITCC_X(x) (((x) & GENMASK(14, 7)) >> 7) > +#define ICPU_PI_MST_CTRL_CSCC(x) (((x) << 5) & GENMASK(6, 5)) > +#define ICPU_PI_MST_CTRL_CSCC_M GENMASK(6, 5) > +#define ICPU_PI_MST_CTRL_CSCC_X(x) (((x) & GENMASK(6, 5)) >> 5) > +#define ICPU_PI_MST_CTRL_OECC(x) (((x) << 3) & GENMASK(4, 3)) > +#define ICPU_PI_MST_CTRL_OECC_M GENMASK(4, 3) > +#define ICPU_PI_MST_CTRL_OECC_X(x) (((x) & GENMASK(4, 3)) >> 3) > +#define ICPU_PI_MST_CTRL_HLDCC(x) ((x) & GENMASK(2, 0)) > +#define ICPU_PI_MST_CTRL_HLDCC_M GENMASK(2, 0) > + > +#define ICPU_PI_MST_STATUS 0x34 > + > +#define ICPU_PI_MST_STATUS_TIMEOUT_ERR_STICKY BIT(0) > + > +#define ICPU_PI_SLV_CFG 0x38 > + > +#define ICPU_PI_SLV_CFG_DONEPOL_VAL BIT(24) > +#define ICPU_PI_SLV_CFG_DONEPOL_SET BIT(23) > +#define ICPU_PI_SLV_CFG_BIGENDIAN BIT(22) > +#define ICPU_PI_SLV_CFG_DONEPARK(x) (((x) << 16) & GENMASK(21, 16)) > +#define ICPU_PI_SLV_CFG_DONEPARK_M GENMASK(21, 16) > +#define ICPU_PI_SLV_CFG_DONEPARK_X(x) (((x) & GENMASK(21, 16)) >> 16) > +#define ICPU_PI_SLV_CFG_DONEWAIT(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_PI_SLV_CFG_DONEWAIT_M GENMASK(15, 8) > +#define ICPU_PI_SLV_CFG_DONEWAIT_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_PI_SLV_CFG_CSWAIT(x) ((x) & GENMASK(7, 0)) > +#define ICPU_PI_SLV_CFG_CSWAIT_M GENMASK(7, 0) > + > +#define ICPU_SPI_MST_CFG 0x3c > + > +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11) > +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) > +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) > +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) > + > +#define ICPU_SPI_MST_STATUS 0x40 > +#define ICPU_SPI_MST_STATUS_RSZ 0x4 > + > +#define ICPU_SPI_MST_STATUS_UNSUP_ERR BIT(0) > + > +#define ICPU_SW_MODE 0x50 > + > +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) > +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12) > +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) > +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10) > +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) > +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) > +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) > +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0) > + > +#define ICPU_MPU8051_CFG 0x54 > + > +#define ICPU_MPU8051_CFG_UART_SYS_ENA BIT(0) > + > +#define ICPU_MPU8051_STAT 0x58 > + > +#define ICPU_MPU8051_STAT_MPU8051_SBA_ERR BIT(9) > +#define ICPU_MPU8051_STAT_MPU8051_STOP BIT(8) > +#define ICPU_MPU8051_STAT_MPU8051_GPR(x) ((x) & GENMASK(7, 0)) > +#define ICPU_MPU8051_STAT_MPU8051_GPR_M GENMASK(7, 0) > + > +#define ICPU_MPU8051_MMAP 0x5c > + > +#define ICPU_MPU8051_MMAP_MSADDR_CODE_HIGH BIT(7) > +#define ICPU_MPU8051_MMAP_MSADDR_CODE_LOW BIT(6) > +#define ICPU_MPU8051_MMAP_MSADDR_DATA_HIGH BIT(5) > +#define ICPU_MPU8051_MMAP_MSADDR_DATA_LOW BIT(4) > +#define ICPU_MPU8051_MMAP_MAP_CODE_HIGH BIT(3) > +#define ICPU_MPU8051_MMAP_MAP_CODE_LOW BIT(2) > +#define ICPU_MPU8051_MMAP_MAP_DATA_HIGH BIT(1) > +#define ICPU_MPU8051_MMAP_MAP_DATA_LOW BIT(0) > + > +#define ICPU_MEMACC_CTRL 0x60 > + > +#define ICPU_MEMACC_CTRL_MEMACC_EXAMINE BIT(1) > +#define ICPU_MEMACC_CTRL_MEMACC_DO BIT(0) > + > +#define ICPU_MEMACC 0x64 > + > +#define ICPU_MEMACC_MEMACC_STOP(x) (((x) << 18) & GENMASK(31, 18)) > +#define ICPU_MEMACC_MEMACC_STOP_M GENMASK(31, 18) > +#define ICPU_MEMACC_MEMACC_STOP_X(x) (((x) & GENMASK(31, 18)) >> 18) > +#define ICPU_MEMACC_MEMACC_START(x) (((x) << 2) & GENMASK(15, 2)) > +#define ICPU_MEMACC_MEMACC_START_M GENMASK(15, 2) > +#define ICPU_MEMACC_MEMACC_START_X(x) (((x) & GENMASK(15, 2)) >> 2) > + > +#define ICPU_MEMACC_SBA 0x68 > + > +#define ICPU_MPU8051_IROM 0x6c > + > +#define ICPU_INTR_RAW 0x70 > + > +#define ICPU_INTR_TRIGGER 0x74 > +#define ICPU_INTR_TRIGGER_RSZ 0x4 > + > +#define ICPU_INTR_FORCE 0x7c > + > +#define ICPU_INTR_STICKY 0x80 > + > +#define ICPU_INTR_BYPASS 0x84 > + > +#define ICPU_INTR_ENA 0x88 > + > +#define ICPU_INTR_ENA_CLR 0x8c > + > +#define ICPU_INTR_ENA_SET 0x90 > + > +#define ICPU_INTR_IDENT 0x94 > + > +#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) > +#define ICPU_DST_INTR_MAP_RSZ 0x4 > + > +#define ICPU_DST_INTR_IDENT 0xa8 > +#define ICPU_DST_INTR_IDENT_RSZ 0x4 > + > +#define ICPU_EXT_SRC_INTR_POL 0xb8 > + > +#define ICPU_EXT_DST_INTR_POL 0xbc > + > +#define ICPU_EXT_DST_INTR_DRV 0xc0 > + > +#define ICPU_DEV_INTR_POL 0xc4 > + > +#define ICPU_DEV_INTR_RAW 0xc8 > + > +#define ICPU_DEV_INTR_TRIGGER 0xcc > +#define ICPU_DEV_INTR_TRIGGER_RSZ 0x4 > + > +#define ICPU_DEV_INTR_STICKY 0xd4 > + > +#define ICPU_DEV_INTR_BYPASS 0xd8 > + > +#define ICPU_DEV_INTR_ENA 0xdc > + > +#define ICPU_DEV_INTR_IDENT 0xe0 > + > +#define ICPU_WDT 0xe4 > + > +#define ICPU_WDT_WDT_STATUS BIT(9) > +#define ICPU_WDT_WDT_ENABLE BIT(8) > +#define ICPU_WDT_WDT_LOCK(x) ((x) & GENMASK(7, 0)) > +#define ICPU_WDT_WDT_LOCK_M GENMASK(7, 0) > + > +#define ICPU_TIMER_TICK_DIV 0xe8 > + > +#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) > +#define ICPU_TIMER_VALUE_RSZ 0x4 > + > +#define ICPU_TIMER_RELOAD_VALUE 0xf8 > +#define ICPU_TIMER_RELOAD_VALUE_RSZ 0x4 > + > +#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) > +#define ICPU_TIMER_CTRL_RSZ 0x4 > + > +#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3) > +#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2) > +#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1) > +#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0) > + > +#define ICPU_MEMCTRL_CTRL 0x110 > + > +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) > +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2) > +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) > +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) > + > +#define ICPU_MEMCTRL_CFG 0x114 > + > +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) > +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) > +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) > +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) > +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) > +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) > +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_STAT 0x118 > + > +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) > +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) > +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) > +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) > +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) > + > +#define ICPU_MEMCTRL_REF_PERIOD 0x11c > + > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_ZQCAL 0x120 > + > +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1) > +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0) > + > +#define ICPU_MEMCTRL_TIMING0 0x124 > + > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) > +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING1 0x128 > + > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING2 0x12c > + > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) > +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) > +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) > +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) > +#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0) > + > +#define ICPU_MEMCTRL_TIMING3 0x130 > + > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) > +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) > +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) > +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) > +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) > + > +#define ICPU_MEMCTRL_TIMING4 0x134 > + > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0)) > +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0) > + > +#define ICPU_MEMCTRL_MR0_VAL 0x138 > + > +#define ICPU_MEMCTRL_MR1_VAL 0x13c > + > +#define ICPU_MEMCTRL_MR2_VAL 0x140 > + > +#define ICPU_MEMCTRL_MR3_VAL 0x144 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL 0x148 > + > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) > +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) > + > +#define ICPU_MEMCTRL_DFT 0x14c > + > +#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7) > +#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6) > +#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5) > +#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4) > +#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1)) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1) > +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1) > +#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0) > + > +#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x)) > +#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4 > + > +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) > +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) > + > +#define ICPU_MEMCTRL_DQS_AUTO 0x158 > +#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4 > + > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6)) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1) > +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0) > + > +#define ICPU_MEMPHY_CFG 0x160 > + > +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) > +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) > +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) > +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) > +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) > +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) > +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) > +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) > +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) > +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) > +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0) > + > +#define ICPU_MEMPHY_DFT 0x164 > + > +#define ICPU_MEMPHY_DFT_PHY_DLL_BYPASS BIT(0) > + > +#define ICPU_MEMPHY_DLLCFG0 0x168 > +#define ICPU_MEMPHY_DLLCFG0_RSZ 0x4 > + > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6(x) (((x) << 30) & GENMASK(31, 30)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6_M GENMASK(31, 30) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES6_X(x) (((x) & GENMASK(31, 30)) >> 30) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_LOCK_DET_EN BIT(29) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5(x) (((x) << 27) & GENMASK(28, 27)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5_M GENMASK(28, 27) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES5_X(x) (((x) & GENMASK(28, 27)) >> 27) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3(x) (((x) << 24) & GENMASK(26, 24)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3_M GENMASK(26, 24) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM3_X(x) (((x) & GENMASK(26, 24)) >> 24) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES4 BIT(23) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2(x) (((x) << 20) & GENMASK(22, 20)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2_M GENMASK(22, 20) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM2_X(x) (((x) & GENMASK(22, 20)) >> 20) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES3 BIT(19) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1(x) (((x) << 16) & GENMASK(18, 16)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1_M GENMASK(18, 16) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM1_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES2 BIT(15) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0_M GENMASK(14, 12) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_BIAS_TRM0_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES1 BIT(11) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A(x) (((x) << 9) & GENMASK(10, 9)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A_M GENMASK(10, 9) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_A_X(x) (((x) & GENMASK(10, 9)) >> 9) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D(x) (((x) << 6) & GENMASK(8, 6)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D_M GENMASK(8, 6) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_D_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_TEST_CTRL_EN BIT(5) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM(x) (((x) << 2) & GENMASK(4, 2)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM_M GENMASK(4, 2) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_IPUMP_TRM_X(x) (((x) & GENMASK(4, 2)) >> 2) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES0(x) ((x) & GENMASK(1, 0)) > +#define ICPU_MEMPHY_DLLCFG0_DLLCFG_RES0_M GENMASK(1, 0) > + > +#define ICPU_MEMPHY_DLLCFG1 0x174 > +#define ICPU_MEMPHY_DLLCFG1_RSZ 0x4 > + > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES9 BIT(19) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_TEST_HIZB_A BIT(18) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8(x) (((x) << 12) & GENMASK(17, 12)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8_M GENMASK(17, 12) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES8_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM(x) (((x) << 9) & GENMASK(11, 9)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM_M GENMASK(11, 9) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FF_TRM_X(x) (((x) & GENMASK(11, 9)) >> 9) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM(x) (((x) << 6) & GENMASK(8, 6)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM_M GENMASK(8, 6) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_FB_TRM_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES7(x) ((x) & GENMASK(5, 0)) > +#define ICPU_MEMPHY_DLLCFG1_DLLCFG_RES7_M GENMASK(5, 0) > + > +#define ICPU_MEMPHY_DQ_DLY_TRM 0x180 > +#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 > + > +#define ICPU_MEMPHY_ZCAL 0x188 > + > +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) > +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_STAT 0x18c > + > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1) > +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_OVR 0x190 > + > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA(x) (((x) << 12) & GENMASK(31, 12)) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA_M GENMASK(31, 12) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_DATA_X(x) (((x) & GENMASK(31, 12)) >> 12) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_ENACLR_DIS BIT(2) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_ZCOMP BIT(1) > +#define ICPU_MEMPHY_ZCAL_OVR_ZCAL_OVR_ENA BIT(0) > + > +#define ICPU_MEMPHY_ZCAL_FORCE 0x194 > + > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL_M GENMASK(3, 2) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZCAL_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ZQ_OFF BIT(1) > +#define ICPU_MEMPHY_ZCAL_FORCE_ZCAL_FORCE_ENA BIT(0) > + > +#define ICPU_TWI_CONFIG 0x198 > + > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD(x) (((x) << 1) & GENMASK(8, 1)) > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD_M GENMASK(8, 1) > +#define ICPU_TWI_CONFIG_TWI_CNT_RELOAD_X(x) (((x) & GENMASK(8, 1)) >> 1) > +#define ICPU_TWI_CONFIG_TWI_DELAY_ENABLE BIT(0) > + > +#define ICPU_TWI_SPIKE_FILTER_CFG 0x19c > + > +#define ICPU_FDMA_DCB_LLP 0x1a0 > +#define ICPU_FDMA_DCB_LLP_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAP 0x1c8 > +#define ICPU_FDMA_DCB_DATAP_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAL 0x1f0 > +#define ICPU_FDMA_DCB_DATAL_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_DATAL_TOKEN BIT(17) > +#define ICPU_FDMA_DCB_DATAL_DATAL(x) ((x) & GENMASK(15, 0)) > +#define ICPU_FDMA_DCB_DATAL_DATAL_M GENMASK(15, 0) > + > +#define ICPU_FDMA_DCB_STAT 0x218 > +#define ICPU_FDMA_DCB_STAT_RSZ 0x4 > + > +#define ICPU_FDMA_DCB_STAT_BLOCKO(x) (((x) << 20) & GENMASK(31, 20)) > +#define ICPU_FDMA_DCB_STAT_BLOCKO_M GENMASK(31, 20) > +#define ICPU_FDMA_DCB_STAT_BLOCKO_X(x) (((x) & GENMASK(31, 20)) >> 20) > +#define ICPU_FDMA_DCB_STAT_PD BIT(19) > +#define ICPU_FDMA_DCB_STAT_ABORT BIT(18) > +#define ICPU_FDMA_DCB_STAT_EOF BIT(17) > +#define ICPU_FDMA_DCB_STAT_SOF BIT(16) > +#define ICPU_FDMA_DCB_STAT_BLOCKL(x) ((x) & GENMASK(15, 0)) > +#define ICPU_FDMA_DCB_STAT_BLOCKL_M GENMASK(15, 0) > + > +#define ICPU_FDMA_DCB_LLP_PREV 0x240 > +#define ICPU_FDMA_DCB_LLP_PREV_RSZ 0x4 > + > +#define ICPU_FDMA_CH_STAT 0x268 > + > +#define ICPU_FDMA_CH_SAFE 0x26c > + > +#define ICPU_FDMA_CH_ACTIVATE 0x270 > + > +#define ICPU_FDMA_CH_DISABLE 0x274 > + > +#define ICPU_FDMA_CH_FORCEDIS 0x278 > + > +#define ICPU_FDMA_CH_CNT 0x27c > +#define ICPU_FDMA_CH_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM(x) (((x) << 16) & GENMASK(31, 16)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM_M GENMASK(31, 16) > +#define ICPU_FDMA_CH_CNT_CH_CNT_FRM_X(x) (((x) & GENMASK(31, 16)) >> 16) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB_M GENMASK(15, 8) > +#define ICPU_FDMA_CH_CNT_CH_CNT_DCB_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_FDMA_CH_CNT_CH_CNT_SIG(x) ((x) & GENMASK(7, 0)) > +#define ICPU_FDMA_CH_CNT_CH_CNT_SIG_M GENMASK(7, 0) > + > +#define ICPU_FDMA_CH_INJ_CNT 0x2a4 > +#define ICPU_FDMA_CH_INJ_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_CH_INJ_TICK_RLD 0x2c4 > +#define ICPU_FDMA_CH_INJ_TICK_RLD_RSZ 0x4 > + > +#define ICPU_FDMA_CH_INJ_TICK_CNT 0x2e4 > +#define ICPU_FDMA_CH_INJ_TICK_CNT_RSZ 0x4 > + > +#define ICPU_FDMA_EVT_ERR 0x304 > + > +#define ICPU_FDMA_EVT_ERR_CODE 0x308 > + > +#define ICPU_FDMA_INTR_LLP 0x30c > + > +#define ICPU_FDMA_INTR_LLP_ENA 0x310 > + > +#define ICPU_FDMA_INTR_FRM 0x314 > + > +#define ICPU_FDMA_INTR_FRM_ENA 0x318 > + > +#define ICPU_FDMA_INTR_SIG 0x31c > + > +#define ICPU_FDMA_INTR_SIG_ENA 0x320 > + > +#define ICPU_FDMA_INTR_ENA 0x324 > + > +#define ICPU_FDMA_INTR_IDENT 0x328 > + > +#define ICPU_FDMA_CH_CFG 0x32c > +#define ICPU_FDMA_CH_CFG_RSZ 0x4 > + > +#define ICPU_FDMA_CH_CFG_STAT_IN_DATA_ENA BIT(7) > +#define ICPU_FDMA_CH_CFG_CH_INJ_GRP BIT(6) > +#define ICPU_FDMA_CH_CFG_CH_PRIO(x) (((x) << 2) & GENMASK(5, 2)) > +#define ICPU_FDMA_CH_CFG_CH_PRIO_M GENMASK(5, 2) > +#define ICPU_FDMA_CH_CFG_CH_PRIO_X(x) (((x) & GENMASK(5, 2)) >> 2) > +#define ICPU_FDMA_CH_CFG_DONE_STOP_ENA BIT(1) > +#define ICPU_FDMA_CH_CFG_DONEEOF_STOP_ENA BIT(0) > + > +#define ICPU_FDMA_GCFG 0x354 > + > +#define ICPU_FDMA_GCFG_FRM_AT_OFF BIT(12) > +#define ICPU_FDMA_GCFG_INJ_RF_WM(x) (((x) << 7) & GENMASK(11, 7)) > +#define ICPU_FDMA_GCFG_INJ_RF_WM_M GENMASK(11, 7) > +#define ICPU_FDMA_GCFG_INJ_RF_WM_X(x) (((x) & GENMASK(11, 7)) >> 7) > +#define ICPU_FDMA_GCFG_XTR_RF_WM(x) (((x) << 3) & GENMASK(6, 3)) > +#define ICPU_FDMA_GCFG_XTR_RF_WM_M GENMASK(6, 3) > +#define ICPU_FDMA_GCFG_XTR_RF_WM_X(x) (((x) & GENMASK(6, 3)) >> 3) > +#define ICPU_FDMA_GCFG_XTR_AVAIL_EXT_DIS BIT(2) > +#define ICPU_FDMA_GCFG_XTR_PRIO_BP_DIS BIT(1) > +#define ICPU_FDMA_GCFG_PD_IGNORE BIT(0) > + > +#define ICPU_FDMA_GSTAT 0x358 > + > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH(x) (((x) << 5) & GENMASK(10, 5)) > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH_M GENMASK(10, 5) > +#define ICPU_FDMA_GSTAT_INJ_RF_HIGH_X(x) (((x) & GENMASK(10, 5)) >> 5) > +#define ICPU_FDMA_GSTAT_XTR_RF_HIGH(x) ((x) & GENMASK(4, 0)) > +#define ICPU_FDMA_GSTAT_XTR_RF_HIGH_M GENMASK(4, 0) > + > +#define ICPU_FDMA_IDLECNT 0x35c > + > +#define ICPU_FDMA_CONST 0x360 > + > +#define ICPU_FDMA_CONST_CH_INJ_CNT(x) (((x) << 8) & GENMASK(15, 8)) > +#define ICPU_FDMA_CONST_CH_INJ_CNT_M GENMASK(15, 8) > +#define ICPU_FDMA_CONST_CH_INJ_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define ICPU_FDMA_CONST_CH_XTR_CNT(x) ((x) & GENMASK(7, 0)) > +#define ICPU_FDMA_CONST_CH_XTR_CNT_M GENMASK(7, 0) > + > +#define ICPU_PCIE_CTRL 0x364 > + > +#define ICPU_PCIE_CTRL_POWERUP BIT(0) > + > +#define ICPU_PCIE_CFG 0x368 > + > +#define ICPU_PCIE_CFG_CG_DIS BIT(5) > +#define ICPU_PCIE_CFG_MEM_CG_DIS BIT(4) > +#define ICPU_PCIE_CFG_CONF_REQ_RETRY_ENA BIT(3) > +#define ICPU_PCIE_CFG_PCIE_BAR_WR_ENA BIT(2) > +#define ICPU_PCIE_CFG_LTSSM_DIS BIT(1) > +#define ICPU_PCIE_CFG_MEM_RING_CORE_ENA BIT(0) > + > +#define ICPU_PCIE_STAT 0x36c > + > +#define ICPU_PCIE_STAT_SLV_ERROR_REPLY BIT(12) > +#define ICPU_PCIE_STAT_LTSSM_STATE(x) (((x) << 6) & GENMASK(11, 6)) > +#define ICPU_PCIE_STAT_LTSSM_STATE_M GENMASK(11, 6) > +#define ICPU_PCIE_STAT_LTSSM_STATE_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define ICPU_PCIE_STAT_LINK_STATE(x) (((x) << 3) & GENMASK(5, 3)) > +#define ICPU_PCIE_STAT_LINK_STATE_M GENMASK(5, 3) > +#define ICPU_PCIE_STAT_LINK_STATE_X(x) (((x) & GENMASK(5, 3)) >> 3) > +#define ICPU_PCIE_STAT_PM_STATE(x) ((x) & GENMASK(2, 0)) > +#define ICPU_PCIE_STAT_PM_STATE_M GENMASK(2, 0) > + > +#define ICPU_PCIE_AUX_CFG 0x370 > + > +#define ICPU_PCIE_AUX_CFG_AUX_POWER_VAL BIT(0) > + > +#define ICPU_PCIE_DBG_STAT 0x374 > + > +#define ICPU_PCIE_DBG_STAT_TBI_RX_CE BIT(14) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_LOS BIT(13) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_SDET BIT(12) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA(x) (((x) << 2) & GENMASK(11, 2)) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA_M GENMASK(11, 2) > +#define ICPU_PCIE_DBG_STAT_TBI_RX_DATA_X(x) (((x) & GENMASK(11, 2)) >> 2) > +#define ICPU_PCIE_DBG_STAT_PM_L2_EXIT BIT(1) > +#define ICPU_PCIE_DBG_STAT_DATA_LINK_LAYER_UP BIT(0) > + > +#define ICPU_PCIEMST_REPLY_INFO 0x378 > + > +#define ICPU_PCIEMST_BAR1_OFFSET 0x37c > + > +#define ICPU_PCIEMST_BAR1_MASK 0x380 > + > +#define ICPU_PCIEMST_BAR2_OFFSET 0x384 > + > +#define ICPU_PCIEMST_BAR2_MASK 0x388 > + > +#define ICPU_PCIESLV_FDMA 0x38c > + > +#define ICPU_PCIESLV_FDMA_FDMA_TC(x) (((x) << 4) & GENMASK(6, 4)) > +#define ICPU_PCIESLV_FDMA_FDMA_TC_M GENMASK(6, 4) > +#define ICPU_PCIESLV_FDMA_FDMA_TC_X(x) (((x) & GENMASK(6, 4)) >> 4) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR(x) (((x) << 2) & GENMASK(3, 2)) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR_M GENMASK(3, 2) > +#define ICPU_PCIESLV_FDMA_FDMA_ATTR_X(x) (((x) & GENMASK(3, 2)) >> 2) > +#define ICPU_PCIESLV_FDMA_FDMA_OFFSET(x) ((x) & GENMASK(1, 0)) > +#define ICPU_PCIESLV_FDMA_FDMA_OFFSET_M GENMASK(1, 0) > + > +#define ICPU_PCIESLV_SBA 0x390 > + > +#define ICPU_PCIESLV_SBA_SBA_BE(x) (((x) << 24) & GENMASK(27, 24)) > +#define ICPU_PCIESLV_SBA_SBA_BE_M GENMASK(27, 24) > +#define ICPU_PCIESLV_SBA_SBA_BE_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define ICPU_PCIESLV_SBA_SBA_RESERVED1 BIT(23) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE(x) (((x) << 15) & GENMASK(22, 15)) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE_M GENMASK(22, 15) > +#define ICPU_PCIESLV_SBA_SBA_MSG_CODE_X(x) (((x) & GENMASK(22, 15)) >> 15) > +#define ICPU_PCIESLV_SBA_SBA_TC(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_PCIESLV_SBA_SBA_TC_M GENMASK(14, 12) > +#define ICPU_PCIESLV_SBA_SBA_TC_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_PCIESLV_SBA_SBA_ATTR(x) (((x) << 10) & GENMASK(11, 10)) > +#define ICPU_PCIESLV_SBA_SBA_ATTR_M GENMASK(11, 10) > +#define ICPU_PCIESLV_SBA_SBA_ATTR_X(x) (((x) & GENMASK(11, 10)) >> 10) > +#define ICPU_PCIESLV_SBA_SBA_TD BIT(9) > +#define ICPU_PCIESLV_SBA_SBA_EP BIT(8) > +#define ICPU_PCIESLV_SBA_SBA_RESERVED0 BIT(7) > +#define ICPU_PCIESLV_SBA_SBA_TYPE(x) (((x) << 2) & GENMASK(6, 2)) > +#define ICPU_PCIESLV_SBA_SBA_TYPE_M GENMASK(6, 2) > +#define ICPU_PCIESLV_SBA_SBA_TYPE_X(x) (((x) & GENMASK(6, 2)) >> 2) > +#define ICPU_PCIESLV_SBA_SBA_OFFSET(x) ((x) & GENMASK(1, 0)) > +#define ICPU_PCIESLV_SBA_SBA_OFFSET_M GENMASK(1, 0) > + > +#define ICPU_PCIEPCS_CFG 0x394 > + > +#define ICPU_PCIEPCS_CFG_TXRX_DETECT BIT(22) > +#define ICPU_PCIEPCS_CFG_SDETCOM_PERM BIT(21) > +#define ICPU_PCIEPCS_CFG_SDETCOM_DIS BIT(20) > +#define ICPU_PCIEPCS_CFG_BEACON_FORCE BIT(19) > +#define ICPU_PCIEPCS_CFG_RXRST_FORCE BIT(18) > +#define ICPU_PCIEPCS_CFG_RXRST_VAL BIT(17) > +#define ICPU_PCIEPCS_CFG_TXRST_FORCE BIT(16) > +#define ICPU_PCIEPCS_CFG_TXRST_VAL BIT(15) > +#define ICPU_PCIEPCS_CFG_RXSDET_XOR BIT(14) > +#define ICPU_PCIEPCS_CFG_RXSDET_FORCE BIT(13) > +#define ICPU_PCIEPCS_CFG_RXINV_ENA BIT(12) > +#define ICPU_PCIEPCS_CFG_RXSWAP_ENA BIT(11) > +#define ICPU_PCIEPCS_CFG_TXSWAP_ENA BIT(10) > +#define ICPU_PCIEPCS_CFG_IDLE_DATA_DIS BIT(9) > +#define ICPU_PCIEPCS_CFG_IDLE_DIS BIT(8) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY(x) (((x) << 5) & GENMASK(7, 5)) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY_M GENMASK(7, 5) > +#define ICPU_PCIEPCS_CFG_IDLE_DLY_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define ICPU_PCIEPCS_CFG_RXLP_FORCE BIT(4) > +#define ICPU_PCIEPCS_CFG_TXLP_FORCE BIT(3) > +#define ICPU_PCIEPCS_CFG_WAKE_POL BIT(2) > +#define ICPU_PCIEPCS_CFG_WAKE_OE BIT(1) > +#define ICPU_PCIEPCS_CFG_BEACON_DIS BIT(0) > + > +#define ICPU_PCIEPCS_BEACON 0x398 > + > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL(x) (((x) << 16) & GENMASK(25, 16)) > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL_M GENMASK(25, 16) > +#define ICPU_PCIEPCS_BEACON_BEACON_VAL_X(x) (((x) & GENMASK(25, 16)) >> 16) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DIS BIT(15) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DLY(x) ((x) & GENMASK(14, 0)) > +#define ICPU_PCIEPCS_BEACON_BEACON_MAX_DLY_M GENMASK(14, 0) > + > +#define ICPU_PCIE_INTR 0x39c > + > +#define ICPU_PCIE_INTR_INTR_LTSSM_STATE BIT(4) > +#define ICPU_PCIE_INTR_INTR_LINK_STATE BIT(3) > +#define ICPU_PCIE_INTR_INTR_BAR1_WR BIT(2) > +#define ICPU_PCIE_INTR_INTR_BAR1_RD BIT(1) > +#define ICPU_PCIE_INTR_INTR_PM_STATE BIT(0) > + > +#define ICPU_PCIE_INTR_ENA 0x3a0 > + > +#define ICPU_PCIE_INTR_ENA_INTR_LTSSM_STATE_ENA BIT(4) > +#define ICPU_PCIE_INTR_ENA_INTR_LINK_STATE_ENA BIT(3) > +#define ICPU_PCIE_INTR_ENA_INTR_BAR1_WR_ENA BIT(2) > +#define ICPU_PCIE_INTR_ENA_INTR_BAR1_RD_ENA BIT(1) > +#define ICPU_PCIE_INTR_ENA_INTR_PM_STATE_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_IDENT 0x3a4 > + > +#define ICPU_PCIE_INTR_IDENT_INTR_LTSSM_STATE_IDENT BIT(4) > +#define ICPU_PCIE_INTR_IDENT_INTR_LINK_STATE_IDENT BIT(3) > +#define ICPU_PCIE_INTR_IDENT_INTR_BAR1_WR_IDENT BIT(2) > +#define ICPU_PCIE_INTR_IDENT_INTR_BAR1_RD_IDENT BIT(1) > +#define ICPU_PCIE_INTR_IDENT_INTR_PM_STATE_IDENT BIT(0) > + > +#define ICPU_PCIE_INTR_COMMON_CFG 0x3a8 > + > +#define ICPU_PCIE_INTR_COMMON_CFG_WAKEUP_ON_INTR_DIS BIT(2) > +#define ICPU_PCIE_INTR_COMMON_CFG_LEGACY_MODE_INTR_SEL BIT(1) > +#define ICPU_PCIE_INTR_COMMON_CFG_PCIE_INTR_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_CFG 0x3ac > +#define ICPU_PCIE_INTR_CFG_RSZ 0x4 > + > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER(x) (((x) << 15) & GENMASK(17, 15)) > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER_M GENMASK(17, 15) > +#define ICPU_PCIE_INTR_CFG_FUNCTION_NUMBER_X(x) (((x) & GENMASK(17, 15)) >> 15) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS(x) (((x) << 12) & GENMASK(14, 12)) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS_M GENMASK(14, 12) > +#define ICPU_PCIE_INTR_CFG_TRAFFIC_CLASS_X(x) (((x) & GENMASK(14, 12)) >> 12) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL(x) (((x) << 7) & GENMASK(11, 7)) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL_M GENMASK(11, 7) > +#define ICPU_PCIE_INTR_CFG_FALLING_VECTOR_VAL_X(x) (((x) & GENMASK(11, 7)) >> 7) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL(x) (((x) << 2) & GENMASK(6, 2)) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL_M GENMASK(6, 2) > +#define ICPU_PCIE_INTR_CFG_RISING_VECTOR_VAL_X(x) (((x) & GENMASK(6, 2)) >> 2) > +#define ICPU_PCIE_INTR_CFG_INTR_FALLING_ENA BIT(1) > +#define ICPU_PCIE_INTR_CFG_INTR_RISING_ENA BIT(0) > + > +#define ICPU_PCIE_INTR_STAT 0x3b4 > +#define ICPU_PCIE_INTR_STAT_RSZ 0x4 > + > +#define ICPU_PCIE_INTR_STAT_INTR_PENDING_FALLING BIT(1) > +#define ICPU_PCIE_INTR_STAT_INTR_PENDING_RISING BIT(0) > + > +#define ICPU_MANUAL_XTR 0x4000 > + > +#define ICPU_MANUAL_INJ 0x8000 > + > +#define ICPU_MANUAL_CFG 0xc000 > + > +#define ICPU_MANUAL_CFG_XTR_FLUSH_DIS BIT(4) > +#define ICPU_MANUAL_CFG_INJ_SWAP_ENA BIT(3) > +#define ICPU_MANUAL_CFG_XTR_SWAP_ENA BIT(2) > +#define ICPU_MANUAL_CFG_INJ_ENA BIT(1) > +#define ICPU_MANUAL_CFG_XTR_ENA BIT(0) > + > +#define ICPU_MANUAL_INTR 0xc004 > + > +#define ICPU_MANUAL_INTR_INTR_INJ_RDY BIT(2) > +#define ICPU_MANUAL_INTR_INTR_XTR_ANY_RDY BIT(1) > +#define ICPU_MANUAL_INTR_INTR_XTR_SOF_RDY BIT(0) > + > +#define ICPU_MANUAL_INTR_ENA 0xc008 > + > +#define ICPU_MANUAL_INTR_ENA_INTR_INJ_RDY_ENA BIT(2) > +#define ICPU_MANUAL_INTR_ENA_INTR_XTR_ANY_RDY_ENA BIT(1) > +#define ICPU_MANUAL_INTR_ENA_INTR_XTR_SOF_RDY_ENA BIT(0) > + > +#endif > diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h > new file mode 100644 > index 0000000000..4e95da28ce > --- /dev/null > +++ b/arch/mips/mach-mscc/include/mach/tlb.h > @@ -0,0 +1,65 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef __ASM_MACH_TLB_H > +#define __ASM_MACH_TLB_H > + > +#include > +#include > +#include > + > +#define TLB_HI_MASK 0xffffe000 > +#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */ > +#define TLB_LO_SHIFT 6 /* PFN Start bit */ > + > +#define PAGEMASK_SHIFT 13 > + > +#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */ > +#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */ > +#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */ > +#define MMU_PAGE_VALID BIT(1) > +#define MMU_PAGE_GLOBAL BIT(0) > +#define MMU_REGIO_RO_C (MMU_PAGE_CACHED|MMU_PAGE_VALID|MMU_PAGE_GLOBAL) > +#define MMU_REGIO_RO (MMU_PAGE_UNCACHED|MMU_PAGE_VALID|MMU_PAGE_GLOBAL) > +#define MMU_REGIO_RW (MMU_PAGE_DIRTY|MMU_REGIO_RO) > +#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL) > + > +#define TLB_COUNT_MASK GENMASK(5, 0) > +#define TLB_COUNT_OFF 25 > + > +static inline u32 get_tlb_count(void) > +{ > + register u32 config1; > + > + config1 = read_c0_config1(); > + config1 >>= TLB_COUNT_OFF; > + config1 &= TLB_COUNT_MASK; > + > + return 1 + config1; > +} > + > +static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1, > + u32 tlb_attrib2) > +{ > + register u32 tlb_mask, tlb_lo0, tlb_lo1; > + > + tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT; > + tlb_lo0 = tlb_attrib1 | ( offset >> TLB_LO_SHIFT); > + tlb_lo1 = tlb_attrib2 | ((offset + size ) >> TLB_LO_SHIFT); > + > + write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK, > + tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK); > +} > + > +static inline void init_tlb(void) > +{ > + register int i, max; > + > + max = get_tlb_count(); > + for(i = 0; i < max; i++) > + create_tlb(i, i * SZ_1M, SZ_4K, MMU_REGIO_INVAL, MMU_REGIO_INVAL); > +} again can't you leave the setup of MMU mappings to the kernel? > + > +#endif /* __ASM_MACH_TLB_H */ > diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S > new file mode 100644 > index 0000000000..87439439f0 > --- /dev/null > +++ b/arch/mips/mach-mscc/lowlevel_init.S > @@ -0,0 +1,29 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#include > +#include > + > + .text don't set .text in ASM files. The LEAF() and NODE() macros are hacked to place the code in .text.FUNCNAME to allow section garbage collect. > + .set noreorder > + .extern vcoreiii_tlb_init > +#ifdef CONFIG_SOC_LUTON > + .extern pll_init > +#endif > + > +LEAF(lowlevel_init) > + // As we have no stack yet, we can assume the restricted > + // luxury of the sX-registers without saving them > + move s0,ra various coding style issues like C++ comments and wrong indentation > + > + jal vcoreiii_tlb_init > + nop > +#ifdef CONFIG_SOC_LUTON > + jal pll_init > + nop > +#endif > + jr s0 > + nop please indent instructions in the delay slot by one space > +END(lowlevel_init) > diff --git a/arch/mips/mach-mscc/lowlevel_init_luton.S b/arch/mips/mach-mscc/lowlevel_init_luton.S > new file mode 100644 > index 0000000000..5e1b4442d9 > --- /dev/null > +++ b/arch/mips/mach-mscc/lowlevel_init_luton.S > @@ -0,0 +1,63 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#include > +#include > + > +#define BASE_MACRO 0x600a0000 > +#define REG_OFFSET(t, o) (t + (o*4)) > +#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x) > +#define BIT(nr) (1 << (nr)) > + > +#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6) > +#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0) > +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2) > +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0) > +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6) > +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6) > + > + .text > + .set noreorder > +LEAF(pll_init) > + # Make sure PLL is locked > + lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 > + andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS > + bne v1, zero, 1f > + nop > + > + # Black magic from frontend > + li v1, 0x00610400 > + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 > + > + li v1, 0x00610c00 > + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 > + > + li v1, 0x00610800 > + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 > + > + li v1, 0x00610000 > + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 > + > + # Wait for lock > +2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 > + andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS > + # Keep looping if zero (no lock bit yet) > + beq v1, zero, 2b > + nop > + > + # Setup PLL CPU clock divider for 416MHz > +1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 > + > + # Keep reserved bits > + li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV > + and v0, v0, v1 > + > + # Set code 6 ~ 416.66 MHz > + ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6) > + > + sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 > + jr ra > + nop > +END(pll_init) > diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c > new file mode 100644 > index 0000000000..85768cbdf0 > --- /dev/null > +++ b/arch/mips/mach-mscc/reset.c > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#include > + > +#include > +#include > + > +#include > + > +void _machine_restart(void) > +{ > + register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; > + (void) readl(REG_GCB(PERF_SOFT_RST)); > + > + /* > + * Make sure VCore is NOT protected from reset > + */ > + writel(readl(REG_CFG(ICPU_RESET)) & ~ICPU_RESET_CORE_RST_PROTECT, > + REG_CFG(ICPU_RESET)); > + > + /* > + * Change to SPI bitbang for SPI reset workaround... > + */ > + writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | > + ICPU_SW_MODE_SW_PIN_CTRL_MODE, REG_CFG(ICPU_SW_MODE)); > + > + /* > + * Do the global reset > + */ > + writel(resetbits, REG_GCB(PERF_SOFT_RST)); > + > + while (1) > + /* NOP */; > +} > -- - Daniel -------------- next part -------------- A non-text attachment was scrubbed... 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