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Thu, 19 Aug 2021 10:23:52 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id c16sm4083387pfb.196.2021.08.19.10.23.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Aug 2021 10:23:51 -0700 (PDT) Subject: Re: [PATCH v3 02/21] target/riscv: Clean up division helpers To: Bin Meng References: <20210819090502.428068-1-richard.henderson@linaro.org> <20210819090502.428068-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <00ab6885-12b6-9c1a-cb7b-b6df770eabd4@linaro.org> Date: Thu, 19 Aug 2021 07:23:48 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.591, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/19/21 1:00 AM, Bin Meng wrote: >> static void gen_rem(TCGv ret, TCGv source1, TCGv source2) >> { >> - TCGv cond1, cond2, zeroreg, resultopt1; >> + TCGv temp1, temp2, zero, one, mone, min; >> >> - cond1 = tcg_temp_new(); >> - cond2 = tcg_temp_new(); >> - zeroreg = tcg_constant_tl(0); >> - resultopt1 = tcg_temp_new(); >> + temp1 = tcg_temp_new(); >> + temp2 = tcg_temp_new(); >> + zero = tcg_constant_tl(0); >> + one = tcg_constant_tl(1); >> + mone = tcg_constant_tl(-1); >> + min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); >> >> - tcg_gen_movi_tl(resultopt1, 1L); >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, >> - (target_ulong)1 << (TARGET_LONG_BITS - 1)); >> - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ >> - /* if overflow or div by zero, set source2 to 1, else don't change */ >> - tcg_gen_or_tl(cond2, cond1, cond2); >> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, >> - resultopt1); >> - tcg_gen_rem_tl(resultopt1, source1, source2); >> - /* if div by zero, just return the original dividend */ >> - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, >> - source1); >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); >> + tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */ >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */ >> + tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */ >> >> - tcg_temp_free(cond1); >> - tcg_temp_free(cond2); >> - tcg_temp_free(resultopt1); >> + /* >> + * if overflow or div by zero, set temp2 to 1, else source2 >> + * this automatically takes care of returning the original >> + * dividend for div by zero. >> + */ >> + tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2); > > What about the overflow case? The return value should be 0. Hmm. I see that in the table, yes, but I don't see that the original code got that correct either. I'll send a follow-up patch. r~ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mGllm-00009v-8Y for mharc-qemu-riscv@gnu.org; Thu, 19 Aug 2021 13:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGllk-00007U-OI for qemu-riscv@nongnu.org; Thu, 19 Aug 2021 13:23:56 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:39720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGlli-0006lq-1Z for qemu-riscv@nongnu.org; Thu, 19 Aug 2021 13:23:56 -0400 Received: by mail-pg1-x531.google.com with SMTP id q2so6516097pgt.6 for ; Thu, 19 Aug 2021 10:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; 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Thu, 19 Aug 2021 10:23:52 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id c16sm4083387pfb.196.2021.08.19.10.23.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Aug 2021 10:23:51 -0700 (PDT) Subject: Re: [PATCH v3 02/21] target/riscv: Clean up division helpers To: Bin Meng Cc: "qemu-devel@nongnu.org Developers" , Alistair Francis , Bin Meng , "open list:RISC-V" References: <20210819090502.428068-1-richard.henderson@linaro.org> <20210819090502.428068-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <00ab6885-12b6-9c1a-cb7b-b6df770eabd4@linaro.org> Date: Thu, 19 Aug 2021 07:23:48 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.591, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Aug 2021 17:23:57 -0000 On 8/19/21 1:00 AM, Bin Meng wrote: >> static void gen_rem(TCGv ret, TCGv source1, TCGv source2) >> { >> - TCGv cond1, cond2, zeroreg, resultopt1; >> + TCGv temp1, temp2, zero, one, mone, min; >> >> - cond1 = tcg_temp_new(); >> - cond2 = tcg_temp_new(); >> - zeroreg = tcg_constant_tl(0); >> - resultopt1 = tcg_temp_new(); >> + temp1 = tcg_temp_new(); >> + temp2 = tcg_temp_new(); >> + zero = tcg_constant_tl(0); >> + one = tcg_constant_tl(1); >> + mone = tcg_constant_tl(-1); >> + min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); >> >> - tcg_gen_movi_tl(resultopt1, 1L); >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, >> - (target_ulong)1 << (TARGET_LONG_BITS - 1)); >> - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ >> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ >> - /* if overflow or div by zero, set source2 to 1, else don't change */ >> - tcg_gen_or_tl(cond2, cond1, cond2); >> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, >> - resultopt1); >> - tcg_gen_rem_tl(resultopt1, source1, source2); >> - /* if div by zero, just return the original dividend */ >> - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, >> - source1); >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); >> + tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */ >> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */ >> + tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */ >> >> - tcg_temp_free(cond1); >> - tcg_temp_free(cond2); >> - tcg_temp_free(resultopt1); >> + /* >> + * if overflow or div by zero, set temp2 to 1, else source2 >> + * this automatically takes care of returning the original >> + * dividend for div by zero. >> + */ >> + tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2); > > What about the overflow case? The return value should be 0. Hmm. I see that in the table, yes, but I don't see that the original code got that correct either. I'll send a follow-up patch. r~