From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756050Ab2CHJR6 (ORCPT ); Thu, 8 Mar 2012 04:17:58 -0500 Received: from LGEMRELSE6Q.lge.com ([156.147.1.121]:47301 "EHLO LGEMRELSE6Q.lge.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755148Ab2CHJRy (ORCPT ); Thu, 8 Mar 2012 04:17:54 -0500 X-Greylist: delayed 903 seconds by postgrey-1.27 at vger.kernel.org; Thu, 08 Mar 2012 04:17:53 EST X-AuditID: 9c930179-b7c4fae0000073fb-0a-4f5875b854c1 From: "Kim, Jong-Sung" To: "'Chanho Min'" , "'Russell King'" , "'Alan Cox'" , "'Greg Kroah-Hartman'" , "'Linus Walleij'" , "'Shreshtha Kumar Sahu'" Cc: , References: In-Reply-To: Subject: RE: [PATCH] Clear previous interrupts after fifo is disabled Date: Thu, 8 Mar 2012 18:02:48 +0900 Organization: LG Electronics Message-ID: <00d901ccfd0a$3c268740$b47395c0$@lge.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-Index: AQIncI9SqTNPd0fm4fZPB+aBpvBgGpWrLkmQ Content-Language: ko X-Brightmail-Tracker: AAAAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Chanho Min [mailto:chanho0207@gmail.com] > Sent: Monday, February 27, 2012 6:30 PM > To: Russell King; Alan Cox; Greg Kroah-Hartman; Linus Walleij; Shreshtha > Kumar Sahu; Kim, Jong-Sung > Cc: linux-kernel@vger.kernel.org; linux-serial@vger.kernel.org > Subject: [PATCH] Clear previous interrupts after fifo is disabled > > This is another workaroud of 'https://lkml.org/lkml/2012/1/17/104' > with additional analysis.Bootloader can transfer control to kernel and there > are some pending interrupts. In this case, RXFE of the flag register is set > by clearing FEN(LCRH) even if rx data remains in the fifo. It seems that the > fifo's status is initiailized. Interrupt handler can not get any data from > data register because of the below break condtion. > > pl011_fifo_to_tty > while (max_count--) { > if (status & UART01x_FR_RXFE) > break; > > Then, Rx interrupt is never cleared. cpu is looping in ISR. System is hang. > If we don't guarantee that no interrupt is pended until fifo is disabled by > calling 'writew(0, uap->port.membase + uap->lcrh_rx)', this misbehave of the > interrupt handelr can be occurred. So, All pending interrupts should be > cleared just after fifo is disabled under the protection from interrupt. > Also,'clear error interrupts' routine can be removed becuase all interrupts > are cleared before. > > Signed-off-by: Chanho Min May I suggest another approach at this point? The problematic condition you reported could be considered as an exceptional Rx interrupt status. So, we can handle it in the Rx ISR. Simply: diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 6800f5f..5b5358705 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -224,6 +224,10 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap) uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); } + /* RXIS but RXFE? Just clear the interrupt */ + if(unlikely(fifotaken == 0)) + writew(UART011_RXIS, uap->port.membase + UART01x_ICR); + return fifotaken; } From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kim, Jong-Sung" Subject: RE: [PATCH] Clear previous interrupts after fifo is disabled Date: Thu, 8 Mar 2012 18:02:48 +0900 Message-ID: <00d901ccfd0a$3c268740$b47395c0$@lge.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: Received: from LGEMRELSE6Q.lge.com ([156.147.1.121]:47301 "EHLO LGEMRELSE6Q.lge.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755148Ab2CHJRy (ORCPT ); Thu, 8 Mar 2012 04:17:54 -0500 In-Reply-To: Content-Language: ko Sender: linux-serial-owner@vger.kernel.org List-Id: linux-serial@vger.kernel.org To: 'Chanho Min' , 'Russell King' , 'Alan Cox' , 'Greg Kroah-Hartman' , 'Linus Walleij' , 'Shreshtha Kumar Sahu' Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org > -----Original Message----- > From: Chanho Min [mailto:chanho0207@gmail.com] > Sent: Monday, February 27, 2012 6:30 PM > To: Russell King; Alan Cox; Greg Kroah-Hartman; Linus Walleij; Shreshtha > Kumar Sahu; Kim, Jong-Sung > Cc: linux-kernel@vger.kernel.org; linux-serial@vger.kernel.org > Subject: [PATCH] Clear previous interrupts after fifo is disabled > > This is another workaroud of 'https://lkml.org/lkml/2012/1/17/104' > with additional analysis.Bootloader can transfer control to kernel and there > are some pending interrupts. In this case, RXFE of the flag register is set > by clearing FEN(LCRH) even if rx data remains in the fifo. It seems that the > fifo's status is initiailized. Interrupt handler can not get any data from > data register because of the below break condtion. > > pl011_fifo_to_tty > while (max_count--) { > if (status & UART01x_FR_RXFE) > break; > > Then, Rx interrupt is never cleared. cpu is looping in ISR. System is hang. > If we don't guarantee that no interrupt is pended until fifo is disabled by > calling 'writew(0, uap->port.membase + uap->lcrh_rx)', this misbehave of the > interrupt handelr can be occurred. So, All pending interrupts should be > cleared just after fifo is disabled under the protection from interrupt. > Also,'clear error interrupts' routine can be removed becuase all interrupts > are cleared before. > > Signed-off-by: Chanho Min May I suggest another approach at this point? The problematic condition you reported could be considered as an exceptional Rx interrupt status. So, we can handle it in the Rx ISR. Simply: diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 6800f5f..5b5358705 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -224,6 +224,10 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap) uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); } + /* RXIS but RXFE? Just clear the interrupt */ + if(unlikely(fifotaken == 0)) + writew(UART011_RXIS, uap->port.membase + UART01x_ICR); + return fifotaken; }