From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:33900)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <p.fedin@samsung.com>) id 1ZotQ3-0006rH-6R
	for qemu-devel@nongnu.org; Wed, 21 Oct 2015 09:27:08 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <p.fedin@samsung.com>) id 1ZotPz-0002tI-9R
	for qemu-devel@nongnu.org; Wed, 21 Oct 2015 09:27:07 -0400
Received: from mailout1.w1.samsung.com ([210.118.77.11]:46263)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <p.fedin@samsung.com>) id 1ZotPz-0002t8-2y
	for qemu-devel@nongnu.org; Wed, 21 Oct 2015 09:27:03 -0400
Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244])
	by mailout1.w1.samsung.com
	(Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5
	2014)) with ESMTP id <0NWK007VVO10YT40@mailout1.w1.samsung.com> for
	qemu-devel@nongnu.org; Wed, 21 Oct 2015 14:27:00 +0100 (BST)
From: Pavel Fedin <p.fedin@samsung.com>
References: <1445361732-16257-1-git-send-email-shlomopongratz@gmail.com>
	<1445361732-16257-10-git-send-email-shlomopongratz@gmail.com>
	<00a301d10bce$7bc0daa0$73428fe0$@samsung.com>
	<CAHzK-V23HbJFCWHX6qHNeWRB3P=0RUQ5RrFWD0ry1HrFe-4C1g@mail.gmail.com>
	<00f501d10beb$94d12690$be7373b0$@samsung.com>
	<CAHzK-V1QfNpVd_LvgpcLwohgNa=Mx6BR_v+BEq1vFofnwyhfVQ@mail.gmail.com>
	<CAFEAcA-rHW4ESbrHoXrjXAAPf_tkeJLfQyy4z6s28-hRxy5u9g@mail.gmail.com>
	<CAHzK-V3E9HwqijW99JZmT8MaKaXW+E+qXOmqHB8aRSr+7iq8vw@mail.gmail.com>
In-reply-to: <CAHzK-V3E9HwqijW99JZmT8MaKaXW+E+qXOmqHB8aRSr+7iq8vw@mail.gmail.com>
Date: Wed, 21 Oct 2015 16:26:59 +0300
Message-id: <015901d10c04$2aa7fd70$7ff7f850$@samsung.com>
MIME-version: 1.0
Content-type: text/plain; charset=UTF-8
Content-transfer-encoding: quoted-printable
Content-language: ru
Subject: Re: [Qemu-devel] [PATCH RFC V5 9/9] hw/arm: Add virt-v3 machine
	that uses GIC-500
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: 'Shlomo Pongratz' <shlomopongratz@gmail.com>, 'Peter Maydell' <peter.maydell@linaro.org>
Cc: eric.auger@linaro.org, 'Shlomo Pongratz' <shlomo.pongratz@huawei.com>, qemu-devel@nongnu.org, shannon.zhao@linaro.org, ashoks@broadcom.com, imammedo@redhat.com

 Hello!

>> The system register implementation belongs in the gic code, not
>> target-arm/. We already have support for devices that say
>> "I have some system registers, please add them to this CPU".

> I don't understand.
> The system registers are defined in ARM Architecture reference Manual.
> It is true that the real implementation is in arm_gicv3_interrupts.c
> But the crn, crm, op0, and op1 of the instructions are in CPU domain.

 Not really. If you take a closer look, you'll see that crn, crm, op1, =
op2 are the same for both ARM64 and ARM32. The only difference is that =
ARM64 uses op0 =3D 3, and ARM32 uses cp =3D 15. Both of these specifiers =
can coexist in the descriptor table.
 I think Peter wants to tell that you should not insert your register =
table and registration function into target-arm/cpu64.c. This code =
should go to hw/intc/arm_gicv3_cpu_interface.c, add .cp =3D 15, and - =
voila - it magically works with both ARM32 and ARM64.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia