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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5458.17 via Frontend Transport; Wed, 20 Jul 2022 13:42:01 +0000 Received: from [10.254.241.52] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 20 Jul 2022 08:41:56 -0500 Message-ID: <0168318c-02b0-c591-190e-770035879b4b@amd.com> Date: Wed, 20 Jul 2022 15:41:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' Content-Language: en-US To: "Datta, Shubhrajyoti" , Krzysztof Kozlowski , Michal Simek , Shubhrajyoti Datta , Rob Herring , Krzysztof Kozlowski CC: Shubhrajyoti Datta , "linux-serial@vger.kernel.org" , "devicetree@vger.kernel.org" , "gregkh@linuxfoundation.org" , Srinivas Goud References: <50bfd52b-6fe0-546f-9121-0145aac91289@xilinx.com> <9d9067f3-5b2d-6434-ec2f-93b4a97a6588@linaro.org> From: Michal Simek In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 13:42:01.2021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eebc1913-f51e-42e2-230d-08da6a559fdc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5112 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 7/14/22 14:14, Datta, Shubhrajyoti wrote: > [AMD Official Use Only - General] > > > >> -----Original Message----- >> From: Krzysztof Kozlowski >> Sent: Thursday, July 14, 2022 5:29 PM >> To: Michal Simek ; Shubhrajyoti Datta >> ; Rob Herring ; Krzysztof >> Kozlowski >> Cc: Shubhrajyoti Datta ; linux-serial@vger.kernel.org; >> devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud >> >> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' >> >> CAUTION: This message has originated from an External Source. Please use >> proper judgment and caution when opening attachments, clicking links, or >> responding to this email. >> >> >> On 14/07/2022 12:55, Michal Simek wrote: >>> Hi Rob and Krzysztof, >>> >>> On 6/14/22 14:21, Shubhrajyoti Datta wrote: >>>>>> >>>> >>>> >>>>> >>>>> No, I don't know what the differences are in your h/w. You have ID >>>>> registers, but changed the IP and didn't change the ID registers? >>>>> How has the IP changed? >>>>> >>>> >>>> The IP is not changed and the ID registers are not updated. >>>> The limitation is coming from the AXI port that the IP is connected to. >>>> The axi port is allowing only the 32 bit access. >>>> The same information will be updated in the Versal TRM. >>> >>> Can you please give us your recommendation how to process with this? >> >> Unfortunately I don't think that anyone remembers context from last year, >> especially me who was not Cced. Rob responded at end of March and it took >> two months to get back any answer. Such slow response time from submitter >> does not help to stay in the context. :( > > I had to contact the hardware team and get the details on the issue it took me sometime to get a response. > > I will summarize > > We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses. > > So to tide over the and differentiate I am adding a new compatible arm,xlnx-uart. ok. Shubhrajyoti: Please send this series again with updated commit message in 1/2 which contains information you provided here. That means it will be v2 version. Thanks, Michal