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[91.12.104.151]) by smtp.gmail.com with ESMTPSA id f14sm3283479wre.69.2021.01.11.23.47.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 23:47:29 -0800 (PST) From: David Hildenbrand Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v3 4/5] tests/tcg/s390x: Fix EXRL tests Date: Tue, 12 Jan 2021 08:47:28 +0100 Message-Id: <0171718F-8768-49AB-8018-E1307AB19292@redhat.com> References: In-Reply-To: To: Thomas Huth X-Mailer: iPhone Mail (18C66) Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , qemu-devel@nongnu.org, David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > Am 12.01.2021 um 08:41 schrieb Thomas Huth : >=20 > =EF=BB=BFOn 11/01/2021 17.38, David Hildenbrand wrote: >> The current EXRL tests crash on real machines: we must not use r0 as a b= ase >> register for trt/trtr, otherwise the content gets ignored. Also, we must >> not use r0 for exrl, otherwise it gets ignored. >> Let's use the "a" constraint so we get a general purpose register !=3D r= 0. >> For op2, we can simply specify a memory operand directly via "Q" (Memory >> reference without index register and with short displacement). >> Fixes: ad8c851d2e77 ("target/s390x: add EX support for TRT and TRTR") >> Signed-off-by: David Hildenbrand >> --- >> tests/tcg/s390x/exrl-trt.c | 8 ++++---- >> tests/tcg/s390x/exrl-trtr.c | 8 ++++---- >> 2 files changed, 8 insertions(+), 8 deletions(-) >> diff --git a/tests/tcg/s390x/exrl-trt.c b/tests/tcg/s390x/exrl-trt.c >> index 3c5323aecb..16711a3181 100644 >> --- a/tests/tcg/s390x/exrl-trt.c >> +++ b/tests/tcg/s390x/exrl-trt.c >> @@ -19,7 +19,7 @@ int main(void) >> } >> asm volatile( >> " j 2f\n" >> - "1: trt 0(1,%[op1]),0(%[op2])\n" >> + "1: trt 0(1,%[op1]),%[op2]\n" >> "2: exrl %[op1_len],1b\n" >> " lgr %[r1],%%r1\n" >> " lgr %[r2],%%r2\n" >> @@ -27,9 +27,9 @@ int main(void) >> : [r1] "+r" (r1), >> [r2] "+r" (r2), >> [cc] "=3Dr" (cc) >> - : [op1] "r" (&op1), >> - [op1_len] "r" (5), >> - [op2] "r" (&op2) >> + : [op1] "a" (&op1), >> + [op1_len] "a" (5), >=20 > I think op1_len could still stay with "r" instead of "a" ... OTOH "a" als= o does not hurt here, so: >=20 No, otherwise exrl ignores the register content if it ends up being r0. Thanks! > Reviewed-by: Thomas Huth