From mboxrd@z Thu Jan  1 00:00:00 1970
From: Madhav Chauhan <madhav.chauhan@intel.com>
Subject: Re: [PATCH v5 06/13] drm/i915/icl: Define data/clock
 lanes dphy timing registers
Date: Wed, 12 Sep 2018 14:41:16 +0530
Message-ID: <01a06e02-cfb2-f257-0e14-56cfe2554c36@intel.com>
References: <1531215614-6828-1-git-send-email-madhav.chauhan@intel.com>
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 <875zzbetii.fsf@intel.com>
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