From: Michal Simek <michal.simek@xilinx.com> To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com, Viresh Kumar <viresh.kumar@linaro.org> Cc: Krzysztof Kozlowski <krzk@kernel.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Quanyang Wang <quanyang.wang@windriver.com>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 25/33] arm64: zynqmp: Wire qspi on multiple boards Date: Mon, 14 Jun 2021 17:25:33 +0200 [thread overview] Message-ID: <01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com> (raw) In-Reply-To: <cover.1623684253.git.michal.simek@xilinx.com> Couple of boards have qspi on the board that's why enable controller and describe them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- Changes in v2: None .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++- .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 14 ++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 14 ++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++ 9 files changed, 121 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 2e05fa416955..f1598527e5ec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -19,6 +19,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -36,6 +37,19 @@ &dcc { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3d0aaa02f184..04efa1683eaa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> @@ -20,6 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -37,6 +38,19 @@ &dcc { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index cd406947ec34..9f176307b62a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -26,6 +26,7 @@ aliases { mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; + spi0 = &qspi; }; chosen { @@ -339,6 +340,19 @@ conf { }; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 8046f0df0f35..05a2b79738af 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -26,6 +26,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + spi0 = &qspi; }; chosen { @@ -161,6 +162,19 @@ &i2c1 { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 3cbc51b4587d..becfc23a5610 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -30,6 +30,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -934,6 +935,20 @@ &psgtr { clock-names = "ref0", "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 4c328569c3ac..84c4a9003e2e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -28,6 +28,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -427,6 +428,19 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 99d172867f6a..fb8d76b5c27f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -28,6 +28,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -435,6 +436,9 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 464a76a13c24..d2219373580a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -30,6 +30,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -928,6 +929,20 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index c9d41d16c3f0..4dc315ee91b7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -29,6 +29,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -772,6 +773,20 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Michal Simek <michal.simek@xilinx.com> To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com, Viresh Kumar <viresh.kumar@linaro.org> Cc: Krzysztof Kozlowski <krzk@kernel.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Quanyang Wang <quanyang.wang@windriver.com>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 25/33] arm64: zynqmp: Wire qspi on multiple boards Date: Mon, 14 Jun 2021 17:25:33 +0200 [thread overview] Message-ID: <01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com> (raw) In-Reply-To: <cover.1623684253.git.michal.simek@xilinx.com> Couple of boards have qspi on the board that's why enable controller and describe them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- Changes in v2: None .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++- .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 14 ++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 14 ++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++ 9 files changed, 121 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 2e05fa416955..f1598527e5ec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -19,6 +19,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -36,6 +37,19 @@ &dcc { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3d0aaa02f184..04efa1683eaa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> @@ -20,6 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -37,6 +38,19 @@ &dcc { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index cd406947ec34..9f176307b62a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -26,6 +26,7 @@ aliases { mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; + spi0 = &qspi; }; chosen { @@ -339,6 +340,19 @@ conf { }; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 8046f0df0f35..05a2b79738af 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -26,6 +26,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + spi0 = &qspi; }; chosen { @@ -161,6 +162,19 @@ &i2c1 { status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 3cbc51b4587d..becfc23a5610 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -30,6 +30,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -934,6 +935,20 @@ &psgtr { clock-names = "ref0", "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 4c328569c3ac..84c4a9003e2e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -28,6 +28,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -427,6 +428,19 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 99d172867f6a..fb8d76b5c27f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -28,6 +28,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -435,6 +436,9 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 464a76a13c24..d2219373580a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -30,6 +30,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; }; chosen { @@ -928,6 +929,20 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index c9d41d16c3f0..4dc315ee91b7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -29,6 +29,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -772,6 +773,20 @@ &psgtr { clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; -- 2.32.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-14 15:27 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-14 15:25 [PATCH v2 00/33] arm64: zynqmp: Extend board description Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 01/33] arm64: zynqmp: Disable CCI by default Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 02/33] arm64: zynqmp: Do not duplicate flash partition label property Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 03/33] arm64: zynqmp: Enable fpd_dma for zcu104 platforms Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 04/33] arm64: zynqmp: Fix irps5401 device nodes Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 05/33] arm64: zynqmp: Add pinctrl description for all boards Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 06/33] arm64: zynqmp: Correct zcu111 psgtr description Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 07/33] arm64: zynqmp: Wire psgtr for zc1751-xm015 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 08/33] arm64: zynqmp: Correct psgtr description for zcu100-revC Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 09/33] arm64: zynqmp: Add phy description for usb3.0 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 10/33] arm64: zynqmp: Disable WP on zcu111 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 11/33] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 12/33] arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 13/33] arm64: zynqmp: Wire DP and DPDMA for dc1/dc4 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 14/33] arm64: zynqmp: Enable nand driver for dc2 and dc3 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 15/33] arm64: zynqmp: Remove additional newline Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 16/33] arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 17/33] arm64: zynqmp: Add nvmem alises for eeproms Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 18/33] arm64: zynqmp: List reset property for ethernet phy Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 19/33] arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 20/33] arm64: zynqmp: Remove can aliases from zc1751 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 21/33] arm64: zynqmp: Move DP nodes to the end of file on zcu106 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 22/33] arm64: zynqmp: Add note about UHS mode on some boards Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 23/33] arm64: zynqmp: Update rtc calibration value Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 24/33] arm64: zynqmp: Remove information about dma clock on zcu106 Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` Michal Simek [this message] 2021-06-14 15:25 ` [PATCH v2 25/33] arm64: zynqmp: Wire qspi on multiple boards Michal Simek 2021-06-14 15:25 ` [PATCH v2 26/33] arm64: zynqmp: Move rtc to different location on zcu104-revA Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 27/33] arm64: zynqmp: Add reset description for sata Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 28/33] arm64: zynqmp: Sync psgtr node location with zcu104-revA Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 29/33] arm64: zynqmp: Remove description for 8T49N287 and si5382 chips Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 30/33] arm64: zynqmp: Add support for zcu102-rev1.1 board Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-24 20:29 ` Rob Herring 2021-06-24 20:29 ` Rob Herring 2021-06-14 15:25 ` [PATCH v2 31/33] arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards Michal Simek 2021-06-14 15:25 ` [PATCH v2 31/33] arm64: zynqmp: Enable xlnx, zynqmp-dwc3 " Michal Simek 2021-06-16 10:07 ` Michael Tretter 2021-06-16 10:07 ` Michael Tretter 2021-06-16 10:24 ` Michal Simek 2021-06-16 10:24 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 32/33] arm64: zynqmp: Add psgtr description to zc1751 dc1 board Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-14 15:25 ` [PATCH v2 33/33] arm64: zynqmp: Add support for Xilinx Kria SOM board Michal Simek 2021-06-14 15:25 ` Michal Simek 2021-06-24 20:36 ` Rob Herring 2021-06-24 20:36 ` Rob Herring 2021-06-25 8:58 ` Michal Simek 2021-06-25 8:58 ` Michal Simek 2021-08-06 8:23 ` [PATCH v2 00/33] arm64: zynqmp: Extend board description Michal Simek 2021-08-06 8:23 ` Michal Simek
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