From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z06Go-0003Vy-OU for qemu-devel@nongnu.org; Wed, 03 Jun 2015 06:51:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z06Gj-0000NJ-QA for qemu-devel@nongnu.org; Wed, 03 Jun 2015 06:51:38 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:59085) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z06Gj-0008WN-Jd for qemu-devel@nongnu.org; Wed, 03 Jun 2015 06:51:33 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NPD00D8W7HSB490@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Wed, 03 Jun 2015 11:51:28 +0100 (BST) From: Pavel Fedin References: <1430921082-16779-1-git-send-email-shlomopongratz@gmail.com> <1430921082-16779-2-git-send-email-shlomopongratz@gmail.com> <20150527181202.2ef26ca6@nial.brq.redhat.com> <20150528113027.3b6fb291@nial.brq.redhat.com> <20150602174412.431a576a@nial.brq.redhat.com> In-reply-to: <20150602174412.431a576a@nial.brq.redhat.com> Date: Wed, 03 Jun 2015 13:51:27 +0300 Message-id: <01c401d09deb$3e775df0$bb6619d0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit Content-language: ru Subject: Re: [Qemu-devel] [PATCH RFC V2 1/4] Use Aff1 with mpidr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: 'Igor Mammedov' , 'Shlomo Pongratz' Cc: peter.maydell@linaro.org, 'Eric Auger' , shlomopongratz@gmail.com, qemu-devel@nongnu.org, 'Shannon Zhao' , ashoks@broadcom.com Hello! > the input parameter i.e. CPUARMState doesn't has the #cores-in-soc nor any other useful > information. We can add this field and initialize it in virt.c Why does it have to be a part of CPUARMState ? Isn't it a global parameter? > on x86 APIC ID used to be derived for cpu_index as well like it is done in ARM for mpidr, but it > has been decoupled form it, converted to property and > set by board code now which is topology aware. Can you point at the code? I'm not familiar with x86 stuff. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia