From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 554E4C433DB for ; Tue, 5 Jan 2021 08:48:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D24F2256F for ; Tue, 5 Jan 2021 08:48:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727664AbhAEIsi (ORCPT ); Tue, 5 Jan 2021 03:48:38 -0500 Received: from mail.kernel.org ([198.145.29.99]:43306 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727557AbhAEIsi (ORCPT ); Tue, 5 Jan 2021 03:48:38 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 16F8B22525; Tue, 5 Jan 2021 08:47:57 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kwi0Q-005OF7-JS; Tue, 05 Jan 2021 08:47:54 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 05 Jan 2021 08:47:54 +0000 From: Marc Zyngier To: David Lechner Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Suman Anna , Grzegorz Jaszczyk , Sekhar Nori , Bartosz Golaszewski , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] irqchip/irq-pruss-intc: implement set_type() callback In-Reply-To: <20210104183656.333256-1-david@lechnology.com> References: <20210104183656.333256-1-david@lechnology.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <02075e85faa562e19b3aeccd53635cbc@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: david@lechnology.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, s-anna@ti.com, grzegorz.jaszczyk@linaro.org, nsekhar@ti.com, bgolaszewski@baylibre.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-01-04 18:36, David Lechner wrote: > This implements the irqchip set_type() callback for the TI PRUSS > interrupt controller. This is needed for cases where an event needs > to be active low. > > According to the technical reference manual, the polarity should always > be set to high, however in practice, the polarity needs to be set low > for the McASP Tx/Rx system event in conjunction with soft UART PRU > firmware for TI AM18XX SoCs, otherwise it doesn't work. I remember asking about this when I reviewed the patch series, and was told that there was no need to handle anything *but* level high. As a consequence, the DT binding doesn't have any way to express the trigger configuration. Now this? What is going to drive the configuration? > > Signed-off-by: David Lechner > --- > drivers/irqchip/irq-pruss-intc.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/irqchip/irq-pruss-intc.c > b/drivers/irqchip/irq-pruss-intc.c > index 5409016e6ca0..f882af8a7ded 100644 > --- a/drivers/irqchip/irq-pruss-intc.c > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -334,6 +334,32 @@ static void pruss_intc_irq_unmask(struct irq_data > *data) > pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq); > } > > +static int pruss_intc_irq_set_type(struct irq_data *data, unsigned int > type) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + u32 reg, bit, val; > + > + if (type & IRQ_TYPE_LEVEL_MASK) { > + /* polarity register */ > + reg = PRU_INTC_SIPR(data->hwirq / 32); > + bit = BIT(data->hwirq % 32); > + val = pruss_intc_read_reg(intc, reg); > + > + /* > + * This check also ensures that IRQ_TYPE_DEFAULT will result > + * in setting the level to high. > + */ > + if (type & IRQ_TYPE_LEVEL_HIGH) > + val |= bit; > + else > + val &= ~bit; > + > + pruss_intc_write_reg(intc, reg, val); RMW of a shared register without locking? > + } > + > + return 0; What happens when this is passed an edge configuration? It should at least return an error. > +} > + > static int pruss_intc_irq_reqres(struct irq_data *data) > { > if (!try_module_get(THIS_MODULE)) > @@ -389,6 +415,7 @@ static struct irq_chip pruss_irqchip = { > .irq_ack = pruss_intc_irq_ack, > .irq_mask = pruss_intc_irq_mask, > .irq_unmask = pruss_intc_irq_unmask, > + .irq_set_type = pruss_intc_irq_set_type, > .irq_request_resources = pruss_intc_irq_reqres, > .irq_release_resources = pruss_intc_irq_relres, > .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state, Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CC86C433DB for ; Tue, 5 Jan 2021 08:49:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A345D22525 for ; Tue, 5 Jan 2021 08:49:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A345D22525 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=40ckT/N12ThY1RMrLpWJp6czp/s80jpLy4Ia650r12g=; b=QvlnYl8+pH+VoZ+ceXArRLiQs MZ9vTrRaRi3m2b0x4TU6OD5VPzB/rijPDSW+6AFMDQjlB6pdEGPfHjG+iCCVUgGWajOLwm8sFeD6T KRNKD+r7HvgPzYUm13Bw1DmeZ0yJUXD1HFqe0xCXn+TAtvqp/NMQ92T3qj+IJHMiu8aZlnngJOuU6 KhRGhw3fNNGQA5b4t8RfzWVhwRaEZi1jrnuGZ6MsI7MA6gSBGHW7R7JENxzmUDKC69mwkwXj2DahT JHJ7yGV8LKO0LiSQRWAcMTujHQa6BevgowsOUl3fqbqMOuCAjdDJAVZJKbpRsuxIRwiYE6C2nZm1I UQJ+FgkJw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwi0X-0002Hc-FB; Tue, 05 Jan 2021 08:48:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwi0U-0002HB-Cd for linux-arm-kernel@lists.infradead.org; Tue, 05 Jan 2021 08:47:59 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 16F8B22525; Tue, 5 Jan 2021 08:47:57 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kwi0Q-005OF7-JS; Tue, 05 Jan 2021 08:47:54 +0000 MIME-Version: 1.0 Date: Tue, 05 Jan 2021 08:47:54 +0000 From: Marc Zyngier To: David Lechner Subject: Re: [PATCH] irqchip/irq-pruss-intc: implement set_type() callback In-Reply-To: <20210104183656.333256-1-david@lechnology.com> References: <20210104183656.333256-1-david@lechnology.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <02075e85faa562e19b3aeccd53635cbc@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: david@lechnology.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, s-anna@ti.com, grzegorz.jaszczyk@linaro.org, nsekhar@ti.com, bgolaszewski@baylibre.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210105_034758_643169_A9B2FC1B X-CRM114-Status: GOOD ( 26.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Grzegorz Jaszczyk , Sekhar Nori , linux-kernel@vger.kernel.org, Bartosz Golaszewski , Thomas Gleixner , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-01-04 18:36, David Lechner wrote: > This implements the irqchip set_type() callback for the TI PRUSS > interrupt controller. This is needed for cases where an event needs > to be active low. > > According to the technical reference manual, the polarity should always > be set to high, however in practice, the polarity needs to be set low > for the McASP Tx/Rx system event in conjunction with soft UART PRU > firmware for TI AM18XX SoCs, otherwise it doesn't work. I remember asking about this when I reviewed the patch series, and was told that there was no need to handle anything *but* level high. As a consequence, the DT binding doesn't have any way to express the trigger configuration. Now this? What is going to drive the configuration? > > Signed-off-by: David Lechner > --- > drivers/irqchip/irq-pruss-intc.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/irqchip/irq-pruss-intc.c > b/drivers/irqchip/irq-pruss-intc.c > index 5409016e6ca0..f882af8a7ded 100644 > --- a/drivers/irqchip/irq-pruss-intc.c > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -334,6 +334,32 @@ static void pruss_intc_irq_unmask(struct irq_data > *data) > pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq); > } > > +static int pruss_intc_irq_set_type(struct irq_data *data, unsigned int > type) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + u32 reg, bit, val; > + > + if (type & IRQ_TYPE_LEVEL_MASK) { > + /* polarity register */ > + reg = PRU_INTC_SIPR(data->hwirq / 32); > + bit = BIT(data->hwirq % 32); > + val = pruss_intc_read_reg(intc, reg); > + > + /* > + * This check also ensures that IRQ_TYPE_DEFAULT will result > + * in setting the level to high. > + */ > + if (type & IRQ_TYPE_LEVEL_HIGH) > + val |= bit; > + else > + val &= ~bit; > + > + pruss_intc_write_reg(intc, reg, val); RMW of a shared register without locking? > + } > + > + return 0; What happens when this is passed an edge configuration? It should at least return an error. > +} > + > static int pruss_intc_irq_reqres(struct irq_data *data) > { > if (!try_module_get(THIS_MODULE)) > @@ -389,6 +415,7 @@ static struct irq_chip pruss_irqchip = { > .irq_ack = pruss_intc_irq_ack, > .irq_mask = pruss_intc_irq_mask, > .irq_unmask = pruss_intc_irq_unmask, > + .irq_set_type = pruss_intc_irq_set_type, > .irq_request_resources = pruss_intc_irq_reqres, > .irq_release_resources = pruss_intc_irq_relres, > .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state, Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel