From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Date: Thu, 12 Dec 2019 04:39:08 +0300 Message-ID: <02109d70-2747-c246-5401-69a2d5c84771@gmail.com> References: <1575600535-26877-1-git-send-email-skomatineni@nvidia.com> <1575600535-26877-4-git-send-email-skomatineni@nvidia.com> <7cf4ff77-2f33-4ee5-0e09-5aa6aef3e8be@gmail.com> <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <8eb792ad-cded-05cc-93fc-763be7ee66aa@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, sboyd@kernel.org, pdeschrijver@nvidia.com Cc: gregkh@linuxfoundation.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, allison@lohutok.net, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alexios.zavras@intel.com, alsa-devel@alsa-project.org List-Id: linux-tegra@vger.kernel.org 11.12.2019 21:50, Sowjanya Komatineni пишет: > > On 12/10/19 5:06 PM, Sowjanya Komatineni wrote: >> >> On 12/10/19 9:41 AM, Dmitry Osipenko wrote: >>> 10.12.2019 19:53, Sowjanya Komatineni пишет: >>>> On 12/9/19 3:03 PM, Sowjanya Komatineni wrote: >>>>> On 12/9/19 12:46 PM, Sowjanya Komatineni wrote: >>>>>> On 12/9/19 12:12 PM, Dmitry Osipenko wrote: >>>>>>> 08.12.2019 00:36, Sowjanya Komatineni пишет: >>>>>>>> On 12/7/19 11:59 AM, Sowjanya Komatineni wrote: >>>>>>>>> On 12/7/19 8:00 AM, Dmitry Osipenko wrote: >>>>>>>>>> 07.12.2019 18:53, Dmitry Osipenko пишет: >>>>>>>>>>> 07.12.2019 18:47, Dmitry Osipenko пишет: >>>>>>>>>>>> 07.12.2019 17:28, Dmitry Osipenko пишет: >>>>>>>>>>>>> 06.12.2019 05:48, Sowjanya Komatineni пишет: >>>>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, >>>>>>>>>>>>>> clk_out_3 >>>>>>>>>>>>>> with >>>>>>>>>>>>>> mux and gate for each of these clocks. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock >>>>>>>>>>>>>> driver >>>>>>>>>>>>>> using >>>>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base >>>>>>>>>>>>>> address >>>>>>>>>>>>>> and register offsets and PMC programming for these clocks >>>>>>>>>>>>>> happens >>>>>>>>>>>>>> through direct PMC access by the clock driver. >>>>>>>>>>>>>> >>>>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access >>>>>>>>>>>>>> from the >>>>>>>>>>>>>> non-secure world does not go through and these clocks will >>>>>>>>>>>>>> not be >>>>>>>>>>>>>> functional. >>>>>>>>>>>>>> >>>>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock >>>>>>>>>>>>>> provider >>>>>>>>>>>>>> for these clocks. clk_ops callback implementations for these >>>>>>>>>>>>>> clocks >>>>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC >>>>>>>>>>>>>> programming >>>>>>>>>>>>>> in secure mode and non-secure mode. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni >>>>>>>>>>>>>> --- >>>>>>>>>>>> [snip] >>>>>>>>>>>> >>>>>>>>>>>>>> + >>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = { >>>>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled, >>>>>>>>>>>>>> +    .enable = pmc_clk_enable, >>>>>>>>>>>>>> +    .disable = pmc_clk_disable, >>>>>>>>>>>>>> +}; >>>>>>>>>>>>> What's the benefit of separating GATE from the MUX? >>>>>>>>>>>>> >>>>>>>>>>>>> I think it could be a single clock. >>>>>>>>>>>> According to TRM: >>>>>>>>>>>> >>>>>>>>>>>> 1. GATE and MUX are separate entities. >>>>>>>>>>>> >>>>>>>>>>>> 2. GATE is the parent of MUX (see PMC's CLK_OUT paths diagram >>>>>>>>>>>> in TRM). >>>>>>>>>>>> >>>>>>>>>>>> 3. PMC doesn't gate EXTPERIPH clock but could "force-enable" >>>>>>>>>>>> it, >>>>>>>>>>>> correct? >>>>>>>> Was following existing clk-tegra-pmc as I am not sure of reason for >>>>>>>> having these clocks registered as separate mux and gate clocks. >>>>>>>> >>>>>>>> Yes, PMC clocks can be registered as single clock and can use >>>>>>>> clk_ops >>>>>>>> for set/get parent and enable/disable. >>>>>>>> >>>>>>>> enable/disable of PMC clocks is for force-enable to force the >>>>>>>> clock to >>>>>>>> run regardless of ACCEPT_REQ or INVERT_REQ. >>>>>>>> >>>>>>>>>>> 4. clk_m_div2/4 are internal PMC OSC dividers and thus these >>>>>>>>>>> clocks >>>>>>>>>>> should belong to PMC. >>>>>>>>>> Also, it should be "osc" and not "clk_m". >>>>>>>>> I followed the same parents as it were in existing clk-tegra-pmc >>>>>>>>> driver. >>>>>>>>> >>>>>>>>> Yeah they are wrong and they should be from osc and not clk_m. >>>>>>>>> >>>>>>>>> Will fix in next version. >>>>>>>>> >>>>> Reg clk_m_div2/3, they are dividers at OSC pad and not really internal >>>>> to PMC block. >>>>> >>>>> current clock driver creates clk_m_div clocks which should actually be >>>>> osc_div2/osc_div4 clocks with osc as parent. >>>>> >>>>> There are no clk_m_div2 and clk_m_div4 from clk_m >>>>> >>>>> Will fix this in next version. >>>>> >>>>>>> Could you please describe the full EXTPERIPH clock topology and >>>>>>> how the >>>>>>> pinmux configuration is related to it all? >>>>>>> >>>>>>> What is internal to the Tegra chip and what are the external >>>>>>> outputs? >>>>>>> >>>>>>> Is it possible to bypass PMC on T30+ for the EXTPERIPH clocks? >>>>>> PMC CLK1/2/3 possible sources are OSC_DIV1, OSC_DIV2, OSC_DIV4, >>>>>> EXTPERIPH from CAR. >>>>>> >>>>>> OSC_DIV1/2/4 are with internal dividers at the OSC Pads >>>>>> >>>>>> EXTPERIPH is from CAR and it has reset and enable controls along with >>>>>> clock source selections to choose one of the PLLA_OUT0, CLK_S, >>>>>> PLLP_OUT0, CLK_M, PLLE_OUT0 >>>>>> >>>>>> So, PMC CLK1/2/4 possible parents are OSC_DIV1, OSC_DIV2, OSC_DIV4, >>>>>> EXTERN. >>>>>> >>>>>> >>>>>> CLK1/2/3 also has Pinmux to route EXTPERIPH output on to these pins. >>>>>> >>>>>> >>>>>> When EXTERN output clock is selected for these PMC clocks thru >>>>>> CLKx_SRC_SEL, output clock is from driver by EXTPERIPH from CAR via >>>>>> Pinmux logic or driven as per CLKx_SRC_SEL bypassing pinmux based on >>>>>> CLKx_ACCEPT_REQ bit. >>>>>> >>>>>> >>>>>> PMC Clock control register has bit CLKx_ACCEPT_REQ >>>>>> When CLKx_ACCEPT_REQ = 0, output clock driver is from by EXTPERIPH >>>>>> through the pinmux >>>>>> When CLKx_ACCEPT_REQ = 1, output clock is based on CLKx_SRC_SEL bits >>>>>> (OSC_DIV1/2/4 and EXTPERIPH clock bypassing the pinmux) >>>>>> >>>>>> FORCE_EN bit in PMC CLock control register forces the clock to run >>>>>> regardless of this. >>>> PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN >>>> like explained above. >>>> >>>> CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to >>>> enable/disable >>>> EXTPERIPH clock output to PMC CLK_OUT_1/2/3. >>> [and to enable OSC as well] >>> >>>> So I believe we need to register as MUX and Gate rather than as a >>>> single >>>> clock. Please confirm. >>> 1. The force-enabling is applied to both OSC and EXTERN sources of >>> PMC_CLK_OUT_x by PMC at once. >>> >>> 2. Both of PMC's force-enabling and OSC/EXTERN selection is internal >>> to PMC. >>> >>> Should be better to define it as a single "pmc_clk_out_x". I don't see >>> any good reasons for differentiating PMC's Gate from the MUX, it's a >>> single hardware unit from a point of view of the rest of the system. >>> >>> Peter, do you have any objections? >> >> We added fallback option for audio mclk and also added check for >> assigned-clock-parents dt property in audio driver and if its not then >> we do parent init configuration in audio driver. >> >> Current clock driver creates 2 separate clocks clk_out_1_mux and >> clk_out_1 for each pmc clock in clock driver and uses extern1 as >> parent to clk_out_1_mux and clk_out_1_mux is parent to clk_out_1. >> >> With change of registering each pmc clock as a single clock, when we >> do parent init assignment in audio driver when >> assigned-clock-properties are not used in DT (as we removed parent >> inits for extern and clk_outs from clock driver), we should still try >> to get clock based on clk_out_1_mux as parent assignment of extern1 is >> for clk_out_1_mux as per existing clock tree. >> >> clk_out_1_mux clock retrieve will fail with this change of single >> clock when any new platform device tree doesn't specify >> assigned-clock-parents properties and tegra_asoc_utils_init fails. You made the PMC/CaR changes before the audio changes, the clk_out_1_mux won't exist for the audio driver patches. If you care about bisect-ability of the patches, then the clock and audio changes need to be done in a single patch. But I don't think that it's worthwhile. >> With single clock, extern1 is the parent for clk_out_1 and with >> separate clocks for mux and gate, extern1 is the parent for >> clk_out_1_mux. > > If we move to single clock now, it need one more additional fallback > implementation in audio driver during parent configuration as > clk_out_1_mux will not be there with single clock change and old/current > kernel has it as it uses separate clocks for pmc mux and gate. Why additional fallback? Additional to what? > Also, with single clock for both PMC mux and gate now, new DT should use > extern1 as parent to CLK_OUT_1 as CLK_OUT_1_MUX will not be there old > PMC dt-bindings has separate clocks for MUX (CLK_OUT_1_MUX) and gate > (CLK_OUT_1) > > DT bindings will not be compatible b/w old and new changes if we move to > Single PMC clock now. Sorry, I don't understand what you're meaning by the "new changes". > Should we go with same separate clocks to have it compatible to avoid > all this? > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0305AC43603 for ; Thu, 12 Dec 2019 14:22:10 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7EDBB2077B for ; Thu, 12 Dec 2019 14:22:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="tfWu2XSo"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="czfeMlbA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7EDBB2077B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id C0B4716E6; Thu, 12 Dec 2019 15:21:17 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz C0B4716E6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1576160527; bh=buwgsgaZP9KT3tvh12V7YiVjdB5AVpQU9+oSmDXi9/g=; h=To:References:From:Date:In-Reply-To:Cc:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=tfWu2XSoqin8VNXDNcvOe+9l4qY74cYhwZho/xnDbtlHoEJmFsp4OkcwTEvVyGbZD cAk49oBQ96GMnqTxGmd2UmAVdLCNGexfORWJZZQKizH0XpH4tc3JKxJqr4ry/6i/vU 96gHg6EavSGuWjc5atPZnV4ag41CQlSItQ1ux3+M= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id C035BF80255; Thu, 12 Dec 2019 15:19:37 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 336DFF801F4; Thu, 12 Dec 2019 02:39:15 +0100 (CET) Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 4504AF800EC for ; Thu, 12 Dec 2019 02:39:11 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 4504AF800EC Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="czfeMlbA" Received: by mail-lj1-x243.google.com with SMTP id e28so329179ljo.9 for ; Wed, 11 Dec 2019 17:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=bqxzhgdGZNhkxunyYQSbh59QLtmloCd3WtfRiMYQPto=; b=czfeMlbAEYXz0vXlbVuxjrr8ubv4YllExI80yT2QzsMEhV2uFBBEoeHfovOHINDCeG k469H0iJdV3K/cifYPToJF+dp8cuyiKTVujK6Qd9oIstv/b5YIYD89LrVyQoTAY1cRwl gsNbAqJXOXP5hkPm/tVB2bPbfmQnvRUtM9uYgysLmKyATf4Mogg9Hs19J1FZJL7FP9mi pHLHlyT5wFGjE/Ke0FidgJfc2KG3mzPUNDsHCSwyznK6UWXnz1MhRnCx8etNt1Od+S/b ujeK4L+aXeoO0tdy/eeL00sPH6vZK9b7o10bLXukpiWmJsPE4C1kS+AodU3GPyAfET3c rxtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=bqxzhgdGZNhkxunyYQSbh59QLtmloCd3WtfRiMYQPto=; b=TDk8Br76RNJ0QpYaBgt00eJT8Z9tGB/T4nGAGMEZvx9zwIaYxOB8ZRYIwVeARTS7sD lGKNZaODwnWvsDOm052ByM2SO+9mfuaEsNFueVS55yEzRy7Mk1+rHnfjgMOh/SDWtmrb OgMqswkiMXIOHGwNDCDVST4TrjrqZyjlvJP+WgKenrRRTnS7IqgPYGWv8a2nZgHemvQl my2qqrN5CUGPk6XFfpOwCgtZ1nVw+iiJqzocDHzRRoQC9exyRzMQInyIc8PLnAon9ON6 eYQ86ke3iMwGc/ywIdg/crJG0a+Bs9pO/p4An2kX1ZkTh8mpf5XqGPzZv2ikSQxy8o1D BHkQ== X-Gm-Message-State: APjAAAXE6LnjyxrQpVXAPwgEvICSSIwckaH0E9VCFBvdqltUAyLmu2NP Cd6ZTsi/ax5534+ACuxBtecRFNM8 X-Google-Smtp-Source: APXvYqycflaulLJPW1gce2m3mrKE/XyE11yqkOAzLcbpcf5sIe3xLgXDDn9ICItxJURgoMhBxRGf4A== X-Received: by 2002:a2e:81c7:: with SMTP id s7mr3592515ljg.3.1576114750634; Wed, 11 Dec 2019 17:39:10 -0800 (PST) Received: from [192.168.2.145] (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.googlemail.com with ESMTPSA id c8sm1959778lfm.65.2019.12.11.17.39.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 17:39:09 -0800 (PST) To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, sboyd@kernel.org, pdeschrijver@nvidia.com References: <1575600535-26877-1-git-send-email-skomatineni@nvidia.com> <1575600535-26877-4-git-send-email-skomatineni@nvidia.com> <7cf4ff77-2f33-4ee5-0e09-5aa6aef3e8be@gmail.com> <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <8eb792ad-cded-05cc-93fc-763be7ee66aa@nvidia.com> From: Dmitry Osipenko Message-ID: <02109d70-2747-c246-5401-69a2d5c84771@gmail.com> Date: Thu, 12 Dec 2019 04:39:08 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mailman-Approved-At: Thu, 12 Dec 2019 15:19:28 +0100 Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org, pgaikwad@nvidia.com, mturquette@baylibre.com, lgirdwood@gmail.com, josephl@nvidia.com, linux-clk@vger.kernel.org, arnd@arndb.de, daniel.lezcano@linaro.org, krzk@kernel.org, spujar@nvidia.com, devicetree@vger.kernel.org, mmaddireddy@nvidia.com, markz@nvidia.com, alexios.zavras@intel.com, robh+dt@kernel.org, tiwai@suse.com, linux-tegra@vger.kernel.org, horms+renesas@verge.net.au, tglx@linutronix.de, allison@lohutok.net, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, vidyas@nvidia.com, Jisheng.Zhang@synaptics.com, broonie@kernel.org Subject: Re: [alsa-devel] [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - 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cnkgT3NpcGVua28gd3JvdGU6Cj4+Pj4+Pj4+Pj4gMDcuMTIuMjAxOSAxODo1MywgRG1pdHJ5IE9z aXBlbmtvINC/0LjRiNC10YI6Cj4+Pj4+Pj4+Pj4+IDA3LjEyLjIwMTkgMTg6NDcsIERtaXRyeSBP c2lwZW5rbyDQv9C40YjQtdGCOgo+Pj4+Pj4+Pj4+Pj4gMDcuMTIuMjAxOSAxNzoyOCwgRG1pdHJ5 IE9zaXBlbmtvINC/0LjRiNC10YI6Cj4+Pj4+Pj4+Pj4+Pj4gMDYuMTIuMjAxOSAwNTo0OCwgU293 amFueWEgS29tYXRpbmVuaSDQv9C40YjQtdGCOgo+Pj4+Pj4+Pj4+Pj4+PiBUZWdyYTIxMCBhbmQg cHJpb3IgVGVncmEgUE1DIGhhcyBjbGtfb3V0XzEsIGNsa19vdXRfMiwKPj4+Pj4+Pj4+Pj4+Pj4g Y2xrX291dF8zCj4+Pj4+Pj4+Pj4+Pj4+IHdpdGgKPj4+Pj4+Pj4+Pj4+Pj4gbXV4IGFuZCBnYXRl IGZvciBlYWNoIG9mIHRoZXNlIGNsb2Nrcy4KPj4+Pj4+Pj4+Pj4+Pj4KPj4+Pj4+Pj4+Pj4+Pj4g Q3VycmVudGx5IHRoZXNlIFBNQyBjbG9ja3MgYXJlIHJlZ2lzdGVyZWQgYnkgVGVncmEgY2xvY2sK Pj4+Pj4+Pj4+Pj4+Pj4gZHJpdmVyCj4+Pj4+Pj4+Pj4+Pj4+IHVzaW5nCj4+Pj4+Pj4+Pj4+Pj4+ IGNsa19yZWdpc3Rlcl9tdXggYW5kIGNsa19yZWdpc3Rlcl9nYXRlIGJ5IHBhc3NpbmcgUE1DIGJh c2UKPj4+Pj4+Pj4+Pj4+Pj4gYWRkcmVzcwo+Pj4+Pj4+Pj4+Pj4+PiBhbmQgcmVnaXN0ZXIgb2Zm c2V0cyBhbmQgUE1DIHByb2dyYW1taW5nIGZvciB0aGVzZSBjbG9ja3MKPj4+Pj4+Pj4+Pj4+Pj4g aGFwcGVucwo+Pj4+Pj4+Pj4+Pj4+PiB0aHJvdWdoIGRpcmVjdCBQTUMgYWNjZXNzIGJ5IHRoZSBj bG9jayBkcml2ZXIuCj4+Pj4+Pj4+Pj4+Pj4+Cj4+Pj4+Pj4+Pj4+Pj4+IFdpdGggdGhpcywgd2hl biBQTUMgaXMgaW4gc2VjdXJlIG1vZGUgYW55IGRpcmVjdCBQTUMgYWNjZXNzCj4+Pj4+Pj4+Pj4+ Pj4+IGZyb20gdGhlCj4+Pj4+Pj4+Pj4+Pj4+IG5vbi1zZWN1cmUgd29ybGQgZG9lcyBub3QgZ28g dGhyb3VnaCBhbmQgdGhlc2UgY2xvY2tzIHdpbGwKPj4+Pj4+Pj4+Pj4+Pj4gbm90IGJlCj4+Pj4+ Pj4+Pj4+Pj4+IGZ1bmN0aW9uYWwuCj4+Pj4+Pj4+Pj4+Pj4+Cj4+Pj4+Pj4+Pj4+Pj4+IFRoaXMg cGF0Y2ggYWRkcyB0aGVzZSBjbG9ja3MgcmVnaXN0cmF0aW9uIHdpdGggUE1DIGFzIGEgY2xvY2sK Pj4+Pj4+Pj4+Pj4+Pj4gcHJvdmlkZXIKPj4+Pj4+Pj4+Pj4+Pj4gZm9yIHRoZXNlIGNsb2Nrcy4g Y2xrX29wcyBjYWxsYmFjayBpbXBsZW1lbnRhdGlvbnMgZm9yIHRoZXNlCj4+Pj4+Pj4+Pj4+Pj4+ IGNsb2Nrcwo+Pj4+Pj4+Pj4+Pj4+PiB1c2VzIHRlZ3JhX3BtY19yZWFkbCBhbmQgdGVncmFfcG1j X3dyaXRlbCB3aGljaCBzdXBwb3J0cyBQTUMKPj4+Pj4+Pj4+Pj4+Pj4gcHJvZ3JhbW1pbmcKPj4+ Pj4+Pj4+Pj4+Pj4gaW4gc2VjdXJlIG1vZGUgYW5kIG5vbi1zZWN1cmUgbW9kZS4KPj4+Pj4+Pj4+ Pj4+Pj4KPj4+Pj4+Pj4+Pj4+Pj4gU2lnbmVkLW9mZi1ieTogU293amFueWEgS29tYXRpbmVuaSA8 c2tvbWF0aW5lbmlAbnZpZGlhLmNvbT4KPj4+Pj4+Pj4+Pj4+Pj4gLS0tCj4+Pj4+Pj4+Pj4+PiBb c25pcF0KPj4+Pj4+Pj4+Pj4+Cj4+Pj4+Pj4+Pj4+Pj4+ICsKPj4+Pj4+Pj4+Pj4+Pj4gK3N0YXRp YyBjb25zdCBzdHJ1Y3QgY2xrX29wcyBwbWNfY2xrX2dhdGVfb3BzID0gewo+Pj4+Pj4+Pj4+Pj4+ PiArwqDCoMKgIC5pc19lbmFibGVkID0gcG1jX2Nsa19pc19lbmFibGVkLAo+Pj4+Pj4+Pj4+Pj4+ PiArwqDCoMKgIC5lbmFibGUgPSBwbWNfY2xrX2VuYWJsZSwKPj4+Pj4+Pj4+Pj4+Pj4gK8KgwqDC oCAuZGlzYWJsZSA9IHBtY19jbGtfZGlzYWJsZSwKPj4+Pj4+Pj4+Pj4+Pj4gK307Cj4+Pj4+Pj4+ Pj4+Pj4gV2hhdCdzIHRoZSBiZW5lZml0IG9mIHNlcGFyYXRpbmcgR0FURSBmcm9tIHRoZSBNVVg/ Cj4+Pj4+Pj4+Pj4+Pj4KPj4+Pj4+Pj4+Pj4+PiBJIHRoaW5rIGl0IGNvdWxkIGJlIGEgc2luZ2xl IGNsb2NrLgo+Pj4+Pj4+Pj4+Pj4gQWNjb3JkaW5nIHRvIFRSTToKPj4+Pj4+Pj4+Pj4+Cj4+Pj4+ Pj4+Pj4+PiAxLiBHQVRFIGFuZCBNVVggYXJlIHNlcGFyYXRlIGVudGl0aWVzLgo+Pj4+Pj4+Pj4+ Pj4KPj4+Pj4+Pj4+Pj4+IDIuIEdBVEUgaXMgdGhlIHBhcmVudCBvZiBNVVggKHNlZSBQTUMncyBD TEtfT1VUIHBhdGhzIGRpYWdyYW0KPj4+Pj4+Pj4+Pj4+IGluIFRSTSkuCj4+Pj4+Pj4+Pj4+Pgo+ Pj4+Pj4+Pj4+Pj4gMy4gUE1DIGRvZXNuJ3QgZ2F0ZSBFWFRQRVJJUEggY2xvY2sgYnV0IGNvdWxk ICJmb3JjZS1lbmFibGUiCj4+Pj4+Pj4+Pj4+PiBpdCwKPj4+Pj4+Pj4+Pj4+IGNvcnJlY3Q/Cj4+ Pj4+Pj4+IFdhcyBmb2xsb3dpbmcgZXhpc3RpbmcgY2xrLXRlZ3JhLXBtYyBhcyBJIGFtIG5vdCBz dXJlIG9mIHJlYXNvbiBmb3IKPj4+Pj4+Pj4gaGF2aW5nIHRoZXNlIGNsb2NrcyByZWdpc3RlcmVk IGFzIHNlcGFyYXRlIG11eCBhbmQgZ2F0ZSBjbG9ja3MuCj4+Pj4+Pj4+Cj4+Pj4+Pj4+IFllcywg UE1DIGNsb2NrcyBjYW4gYmUgcmVnaXN0ZXJlZCBhcyBzaW5nbGUgY2xvY2sgYW5kIGNhbiB1c2UK Pj4+Pj4+Pj4gY2xrX29wcwo+Pj4+Pj4+PiBmb3Igc2V0L2dldCBwYXJlbnQgYW5kIGVuYWJsZS9k aXNhYmxlLgo+Pj4+Pj4+Pgo+Pj4+Pj4+PiBlbmFibGUvZGlzYWJsZSBvZiBQTUMgY2xvY2tzIGlz IGZvciBmb3JjZS1lbmFibGUgdG8gZm9yY2UgdGhlCj4+Pj4+Pj4+IGNsb2NrIHRvCj4+Pj4+Pj4+ IHJ1biByZWdhcmRsZXNzIG9mIEFDQ0VQVF9SRVEgb3IgSU5WRVJUX1JFUS4KPj4+Pj4+Pj4KPj4+ Pj4+Pj4+Pj4gNC4gY2xrX21fZGl2Mi80IGFyZSBpbnRlcm5hbCBQTUMgT1NDIGRpdmlkZXJzIGFu ZCB0aHVzIHRoZXNlCj4+Pj4+Pj4+Pj4+IGNsb2Nrcwo+Pj4+Pj4+Pj4+PiBzaG91bGQgYmVsb25n IHRvIFBNQy4KPj4+Pj4+Pj4+PiBBbHNvLCBpdCBzaG91bGQgYmUgIm9zYyIgYW5kIG5vdCAiY2xr X20iLgo+Pj4+Pj4+Pj4gSSBmb2xsb3dlZCB0aGUgc2FtZSBwYXJlbnRzIGFzIGl0IHdlcmUgaW4g ZXhpc3RpbmcgY2xrLXRlZ3JhLXBtYwo+Pj4+Pj4+Pj4gZHJpdmVyLgo+Pj4+Pj4+Pj4KPj4+Pj4+ Pj4+IFllYWggdGhleSBhcmUgd3JvbmcgYW5kIHRoZXkgc2hvdWxkIGJlIGZyb20gb3NjIGFuZCBu b3QgY2xrX20uCj4+Pj4+Pj4+Pgo+Pj4+Pj4+Pj4gV2lsbCBmaXggaW4gbmV4dCB2ZXJzaW9uLgo+ Pj4+Pj4+Pj4KPj4+Pj4gUmVnIGNsa19tX2RpdjIvMywgdGhleSBhcmUgZGl2aWRlcnMgYXQgT1ND IHBhZCBhbmQgbm90IHJlYWxseSBpbnRlcm5hbAo+Pj4+PiB0byBQTUMgYmxvY2suCj4+Pj4+Cj4+ Pj4+IGN1cnJlbnQgY2xvY2sgZHJpdmVyIGNyZWF0ZXMgY2xrX21fZGl2IGNsb2NrcyB3aGljaCBz aG91bGQgYWN0dWFsbHkgYmUKPj4+Pj4gb3NjX2RpdjIvb3NjX2RpdjQgY2xvY2tzIHdpdGggb3Nj IGFzIHBhcmVudC4KPj4+Pj4KPj4+Pj4gVGhlcmUgYXJlIG5vIGNsa19tX2RpdjIgYW5kIGNsa19t X2RpdjQgZnJvbSBjbGtfbQo+Pj4+Pgo+Pj4+PiBXaWxsIGZpeCB0aGlzIGluIG5leHQgdmVyc2lv bi4KPj4+Pj4KPj4+Pj4+PiBDb3VsZCB5b3UgcGxlYXNlIGRlc2NyaWJlIHRoZSBmdWxsIEVYVFBF UklQSCBjbG9jayB0b3BvbG9neSBhbmQKPj4+Pj4+PiBob3cgdGhlCj4+Pj4+Pj4gcGlubXV4IGNv bmZpZ3VyYXRpb24gaXMgcmVsYXRlZCB0byBpdCBhbGw/Cj4+Pj4+Pj4KPj4+Pj4+PiBXaGF0IGlz IGludGVybmFsIHRvIHRoZSBUZWdyYSBjaGlwIGFuZCB3aGF0IGFyZSB0aGUgZXh0ZXJuYWwKPj4+ Pj4+PiBvdXRwdXRzPwo+Pj4+Pj4+Cj4+Pj4+Pj4gSXMgaXQgcG9zc2libGUgdG8gYnlwYXNzIFBN QyBvbiBUMzArIGZvciB0aGUgRVhUUEVSSVBIIGNsb2Nrcz8KPj4+Pj4+IFBNQyBDTEsxLzIvMyBw b3NzaWJsZSBzb3VyY2VzIGFyZSBPU0NfRElWMSwgT1NDX0RJVjIsIE9TQ19ESVY0LAo+Pj4+Pj4g RVhUUEVSSVBIIGZyb20gQ0FSLgo+Pj4+Pj4KPj4+Pj4+IE9TQ19ESVYxLzIvNCBhcmUgd2l0aCBp bnRlcm5hbCBkaXZpZGVycyBhdCB0aGUgT1NDIFBhZHMKPj4+Pj4+Cj4+Pj4+PiBFWFRQRVJJUEgg aXMgZnJvbSBDQVIgYW5kIGl0IGhhcyByZXNldCBhbmQgZW5hYmxlIGNvbnRyb2xzIGFsb25nIHdp dGgKPj4+Pj4+IGNsb2NrIHNvdXJjZSBzZWxlY3Rpb25zIHRvIGNob29zZSBvbmUgb2YgdGhlIFBM TEFfT1VUMCwgQ0xLX1MsCj4+Pj4+PiBQTExQX09VVDAsIENMS19NLCBQTExFX09VVDAKPj4+Pj4+ Cj4+Pj4+PiBTbywgUE1DIENMSzEvMi80IHBvc3NpYmxlIHBhcmVudHMgYXJlIE9TQ19ESVYxLCBP U0NfRElWMiwgT1NDX0RJVjQsCj4+Pj4+PiBFWFRFUk4uCj4+Pj4+Pgo+Pj4+Pj4KPj4+Pj4+IENM SzEvMi8zIGFsc28gaGFzIFBpbm11eCB0byByb3V0ZSBFWFRQRVJJUEggb3V0cHV0IG9uIHRvIHRo ZXNlIHBpbnMuCj4+Pj4+Pgo+Pj4+Pj4KPj4+Pj4+IFdoZW4gRVhURVJOIG91dHB1dCBjbG9jayBp cyBzZWxlY3RlZCBmb3IgdGhlc2UgUE1DIGNsb2NrcyB0aHJ1Cj4+Pj4+PiBDTEt4X1NSQ19TRUws IG91dHB1dCBjbG9jayBpcyBmcm9tIGRyaXZlciBieSBFWFRQRVJJUEggZnJvbSBDQVIgdmlhCj4+ Pj4+PiBQaW5tdXggbG9naWMgb3IgZHJpdmVuIGFzIHBlciBDTEt4X1NSQ19TRUwgYnlwYXNzaW5n IHBpbm11eCBiYXNlZCBvbgo+Pj4+Pj4gQ0xLeF9BQ0NFUFRfUkVRIGJpdC4KPj4+Pj4+Cj4+Pj4+ Pgo+Pj4+Pj4gUE1DIENsb2NrIGNvbnRyb2wgcmVnaXN0ZXIgaGFzIGJpdCBDTEt4X0FDQ0VQVF9S RVEKPj4+Pj4+IFdoZW4gQ0xLeF9BQ0NFUFRfUkVRID0gMCwgb3V0cHV0IGNsb2NrIGRyaXZlciBp cyBmcm9tIGJ5IEVYVFBFUklQSAo+Pj4+Pj4gdGhyb3VnaCB0aGUgcGlubXV4Cj4+Pj4+PiBXaGVu IENMS3hfQUNDRVBUX1JFUSA9IDEsIG91dHB1dCBjbG9jayBpcyBiYXNlZCBvbiBDTEt4X1NSQ19T RUwgYml0cwo+Pj4+Pj4gKE9TQ19ESVYxLzIvNCBhbmQgRVhUUEVSSVBIIGNsb2NrIGJ5cGFzc2lu ZyB0aGUgcGlubXV4KQo+Pj4+Pj4KPj4+Pj4+IEZPUkNFX0VOIGJpdCBpbiBQTUMgQ0xvY2sgY29u dHJvbCByZWdpc3RlciBmb3JjZXMgdGhlIGNsb2NrIHRvIHJ1bgo+Pj4+Pj4gcmVnYXJkbGVzcyBv ZiB0aGlzLgo+Pj4+IFBNQyBjbG9jayBnYXRlIGlzIGJhc2VkIG9uIHRoZSBzdGF0ZSBvZiBDTEt4 X0FDQ0VQVF9SRVEgYW5kIEZPUkNFX0VOCj4+Pj4gbGlrZSBleHBsYWluZWQgYWJvdmUuCj4+Pj4K Pj4+PiBDTEt4X0FDQ0VQVF9SRVEgaXMgMCBkZWZhdWx0IGFuZCBGT1JDRV9FTiBhY3RzIGFzIGdh dGUgdG8KPj4+PiBlbmFibGUvZGlzYWJsZQo+Pj4+IEVYVFBFUklQSCBjbG9jayBvdXRwdXQgdG8g UE1DIENMS19PVVRfMS8yLzMuCj4+PiBbYW5kIHRvIGVuYWJsZSBPU0MgYXMgd2VsbF0KPj4+Cj4+ Pj4gU28gSSBiZWxpZXZlIHdlIG5lZWQgdG8gcmVnaXN0ZXIgYXMgTVVYIGFuZCBHYXRlIHJhdGhl ciB0aGFuIGFzIGEKPj4+PiBzaW5nbGUKPj4+PiBjbG9jay4gUGxlYXNlIGNvbmZpcm0uCj4+PiAx LiBUaGUgZm9yY2UtZW5hYmxpbmcgaXMgYXBwbGllZCB0byBib3RoIE9TQyBhbmQgRVhURVJOIHNv dXJjZXMgb2YKPj4+IFBNQ19DTEtfT1VUX3ggYnkgUE1DIGF0IG9uY2UuCj4+Pgo+Pj4gMi4gQm90 aCBvZiBQTUMncyBmb3JjZS1lbmFibGluZyBhbmQgT1NDL0VYVEVSTiBzZWxlY3Rpb24gaXMgaW50 ZXJuYWwKPj4+IHRvIFBNQy4KPj4+Cj4+PiBTaG91bGQgYmUgYmV0dGVyIHRvIGRlZmluZSBpdCBh cyBhIHNpbmdsZSAicG1jX2Nsa19vdXRfeCIuIEkgZG9uJ3Qgc2VlCj4+PiBhbnkgZ29vZCByZWFz b25zIGZvciBkaWZmZXJlbnRpYXRpbmcgUE1DJ3MgR2F0ZSBmcm9tIHRoZSBNVVgsIGl0J3MgYQo+ Pj4gc2luZ2xlIGhhcmR3YXJlIHVuaXQgZnJvbSBhIHBvaW50IG9mIHZpZXcgb2YgdGhlIHJlc3Qg b2YgdGhlIHN5c3RlbS4KPj4+Cj4+PiBQZXRlciwgZG8geW91IGhhdmUgYW55IG9iamVjdGlvbnM/ Cj4+Cj4+IFdlIGFkZGVkIGZhbGxiYWNrIG9wdGlvbiBmb3IgYXVkaW8gbWNsayBhbmQgYWxzbyBh ZGRlZCBjaGVjayBmb3IKPj4gYXNzaWduZWQtY2xvY2stcGFyZW50cyBkdCBwcm9wZXJ0eSBpbiBh dWRpbyBkcml2ZXIgYW5kIGlmIGl0cyBub3QgdGhlbgo+PiB3ZSBkbyBwYXJlbnQgaW5pdCBjb25m aWd1cmF0aW9uIGluIGF1ZGlvIGRyaXZlci4KPj4KPj4gQ3VycmVudCBjbG9jayBkcml2ZXIgY3Jl YXRlcyAyIHNlcGFyYXRlIGNsb2NrcyBjbGtfb3V0XzFfbXV4IGFuZAo+PiBjbGtfb3V0XzEgZm9y IGVhY2ggcG1jIGNsb2NrIGluIGNsb2NrIGRyaXZlciBhbmQgdXNlcyBleHRlcm4xIGFzCj4+IHBh cmVudCB0byBjbGtfb3V0XzFfbXV4IGFuZCBjbGtfb3V0XzFfbXV4IGlzIHBhcmVudCB0byBjbGtf b3V0XzEuCj4+Cj4+IFdpdGggY2hhbmdlIG9mIHJlZ2lzdGVyaW5nIGVhY2ggcG1jIGNsb2NrIGFz IGEgc2luZ2xlIGNsb2NrLCB3aGVuIHdlCj4+IGRvIHBhcmVudCBpbml0IGFzc2lnbm1lbnQgaW4g YXVkaW8gZHJpdmVyIHdoZW4KPj4gYXNzaWduZWQtY2xvY2stcHJvcGVydGllcyBhcmUgbm90IHVz ZWQgaW4gRFQgKGFzIHdlIHJlbW92ZWQgcGFyZW50Cj4+IGluaXRzIGZvciBleHRlcm4gYW5kIGNs a19vdXRzIGZyb20gY2xvY2sgZHJpdmVyKSwgd2Ugc2hvdWxkIHN0aWxsIHRyeQo+PiB0byBnZXQg Y2xvY2sgYmFzZWQgb24gY2xrX291dF8xX211eCBhcyBwYXJlbnQgYXNzaWdubWVudCBvZiBleHRl cm4xIGlzCj4+IGZvciBjbGtfb3V0XzFfbXV4IGFzIHBlciBleGlzdGluZyBjbG9jayB0cmVlLgo+ Pgo+PiBjbGtfb3V0XzFfbXV4IGNsb2NrIHJldHJpZXZlIHdpbGwgZmFpbCB3aXRoIHRoaXMgY2hh bmdlIG9mIHNpbmdsZQo+PiBjbG9jayB3aGVuIGFueSBuZXcgcGxhdGZvcm0gZGV2aWNlIHRyZWUg ZG9lc24ndCBzcGVjaWZ5Cj4+IGFzc2lnbmVkLWNsb2NrLXBhcmVudHMgcHJvcGVydGllcyBhbmQg dGVncmFfYXNvY191dGlsc19pbml0IGZhaWxzLgoKWW91IG1hZGUgdGhlIFBNQy9DYVIgY2hhbmdl cyBiZWZvcmUgdGhlIGF1ZGlvIGNoYW5nZXMsIHRoZSBjbGtfb3V0XzFfbXV4Cndvbid0IGV4aXN0 IGZvciB0aGUgYXVkaW8gZHJpdmVyIHBhdGNoZXMuCgpJZiB5b3UgY2FyZSBhYm91dCBiaXNlY3Qt YWJpbGl0eSBvZiB0aGUgcGF0Y2hlcywgdGhlbiB0aGUgY2xvY2sgYW5kCmF1ZGlvIGNoYW5nZXMg bmVlZCB0byBiZSBkb25lIGluIGEgc2luZ2xlIHBhdGNoLiBCdXQgSSBkb24ndCB0aGluayB0aGF0 Cml0J3Mgd29ydGh3aGlsZS4KCj4+IFdpdGggc2luZ2xlIGNsb2NrLCBleHRlcm4xIGlzIHRoZSBw YXJlbnQgZm9yIGNsa19vdXRfMSBhbmQgd2l0aAo+PiBzZXBhcmF0ZSBjbG9ja3MgZm9yIG11eCBh bmQgZ2F0ZSwgZXh0ZXJuMSBpcyB0aGUgcGFyZW50IGZvcgo+PiBjbGtfb3V0XzFfbXV4Lgo+IAo+ IElmIHdlIG1vdmUgdG8gc2luZ2xlIGNsb2NrIG5vdywgaXQgbmVlZCBvbmUgbW9yZSBhZGRpdGlv bmFsIGZhbGxiYWNrCj4gaW1wbGVtZW50YXRpb24gaW4gYXVkaW8gZHJpdmVyIGR1cmluZyBwYXJl bnQgY29uZmlndXJhdGlvbiBhcwo+IGNsa19vdXRfMV9tdXggd2lsbCBub3QgYmUgdGhlcmUgd2l0 aCBzaW5nbGUgY2xvY2sgY2hhbmdlIGFuZCBvbGQvY3VycmVudAo+IGtlcm5lbCBoYXMgaXQgYXMg aXQgdXNlcyBzZXBhcmF0ZSBjbG9ja3MgZm9yIHBtYyBtdXggYW5kIGdhdGUuCgpXaHkgYWRkaXRp b25hbCBmYWxsYmFjaz8gQWRkaXRpb25hbCB0byB3aGF0PwoKPiBBbHNvLCB3aXRoIHNpbmdsZSBj bG9jayBmb3IgYm90aCBQTUMgbXV4IGFuZCBnYXRlIG5vdywgbmV3IERUIHNob3VsZCB1c2UKPiBl eHRlcm4xIGFzIHBhcmVudCB0byBDTEtfT1VUXzEgYXMgQ0xLX09VVF8xX01VWCB3aWxsIG5vdCBi ZSB0aGVyZSBvbGQKPiBQTUMgZHQtYmluZGluZ3MgaGFzIHNlcGFyYXRlIGNsb2NrcyBmb3IgTVVY IChDTEtfT1VUXzFfTVVYKSBhbmQgZ2F0ZQo+IChDTEtfT1VUXzEpCj4gCj4gRFQgYmluZGluZ3Mg d2lsbCBub3QgYmUgY29tcGF0aWJsZSBiL3cgb2xkIGFuZCBuZXcgY2hhbmdlcyBpZiB3ZSBtb3Zl IHRvCj4gU2luZ2xlIFBNQyBjbG9jayBub3cuCgpTb3JyeSwgSSBkb24ndCB1bmRlcnN0YW5kIHdo YXQgeW91J3JlIG1lYW5pbmcgYnkgdGhlICJuZXcgY2hhbmdlcyIuCgo+IFNob3VsZCB3ZSBnbyB3 aXRoIHNhbWUgc2VwYXJhdGUgY2xvY2tzIHRvIGhhdmUgaXQgY29tcGF0aWJsZSB0byBhdm9pZAo+ IGFsbCB0aGlzPwo+IApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpBbHNhLWRldmVsIG1haWxpbmcgbGlzdApBbHNhLWRldmVsQGFsc2EtcHJvamVjdC5vcmcK aHR0cHM6Ly9tYWlsbWFuLmFsc2EtcHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbHNhLWRl dmVsCg==