From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxTry-0004q8-NW for qemu-devel@nongnu.org; Thu, 11 Jul 2013 23:18:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UxTrx-00045S-GU for qemu-devel@nongnu.org; Thu, 11 Jul 2013 23:18:06 -0400 References: <51C75FA6.6080903@reactos.org> <51C7E21A.9090005@web.de> <8A36D64D-0625-49E1-9E59-391DAEEBD1FC@suse.de> <51DEA91B.40903@suse.de> <3FAA7DE1-06A0-45C5-885C-0433BCC0CFE8@suse.de> <5D205309-1154-4730-902E-BF07F5D3B4EB@suse.de> <1373581960.19894.109.camel@pasglop> Mime-Version: 1.0 (1.0) In-Reply-To: <1373581960.19894.109.camel@pasglop> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Message-Id: <02433CA4-954D-4C56-A4A4-7BC0D62638C0@suse.de> From: Alexander Graf Date: Fri, 12 Jul 2013 05:18:00 +0200 Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Liu Ping Fan , qemu-devel Developers , "qemu-ppc@nongnu.org list:PowerPC" , Paolo Bonzini , Jan Kiszka , =?utf-8?Q?Andreas_F=C3=A4rber?= , =?utf-8?Q?Herv=C3=A9_Poussineau?= Am 12.07.2013 um 00:32 schrieb Benjamin Herrenschmidt : > On Thu, 2013-07-11 at 15:28 +0200, Alexander Graf wrote: >>=20 >> Semantically having your PCI host bridge do the endianness conversion >> is the correct way of handling it, as that's where the conversion >> happens. If it makes life easier to do it in the isa bridging code, >> that's fine for me too though. But then we'll have to get rid of all >> endianness swaps that already happen in PCI bridges. >=20 > BTW. Why would IOs to a PCI VGA device go through an "ISA bridge" of any > kind ? PCI IO space is PCI IO space... whether there is an ISA bridge or > not is a separate thing and PCI VGA cards certainly don't sit behind > one. We model a single system wide io space today and access to that one happens t= hrough you pci host controller. I just messed up the terminology here. Alex >=20 > Ben. >=20 >=20