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* [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-10  5:18 ` Matt Atwood
  0 siblings, 0 replies; 17+ messages in thread
From: Matt Atwood @ 2022-03-10  5:18 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Ashutosh Dixit, Matt Atwood

Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.

v2: fix white space errors

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
 include/uapi/drm/i915_drm.h       | 24 +++++++----
 2 files changed, 65 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 2dfbc22857a3..e4f35da28642 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_perf.h"
 #include "i915_query.h"
+#include "gt/intel_engine_user.h"
 #include <uapi/drm/i915_drm.h>
 
 static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
 	return 0;
 }
 
-static int query_topology_info(struct drm_i915_private *dev_priv,
-			       struct drm_i915_query_item *query_item)
+static int fill_topology_info(const struct sseu_dev_info *sseu,
+			      struct drm_i915_query_item *query_item,
+			      const u8 *subslice_mask)
 {
-	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
 	int ret;
 
-	if (query_item->flags != 0)
-		return -EINVAL;
+	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	if (sseu->max_slices == 0)
 		return -ENODEV;
 
-	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
-
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
 	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
-	ret = copy_query_item(&topo, sizeof(topo), total_length,
-			      query_item);
+	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
+
 	if (ret != 0)
 		return ret;
 
-	if (topo.flags != 0)
-		return -EINVAL;
-
 	memset(&topo, 0, sizeof(topo));
 	topo.max_slices = sseu->max_slices;
 	topo.max_subslices = sseu->max_subslices;
@@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.eu_stride = sseu->eu_stride;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
-			   &topo, sizeof(topo)))
+			 &topo, sizeof(topo)))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
-			   &sseu->slice_mask, slice_length))
+			 &sseu->slice_mask, slice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) + slice_length),
-			   sseu->subslice_mask, subslice_length))
+					 sizeof(topo) + slice_length),
+			 subslice_mask, subslice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) +
-					   slice_length + subslice_length),
-			   sseu->eu_mask, eu_length))
+					 sizeof(topo) +
+					 slice_length + subslice_length),
+			 sseu->eu_mask, eu_length))
 		return -EFAULT;
 
 	return total_length;
 }
 
+static int query_topology_info(struct drm_i915_private *dev_priv,
+			       struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
+
+	if (query_item->flags != 0)
+		return -EINVAL;
+
+	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
+}
+
+static int query_geometry_subslices(struct drm_i915_private *i915,
+				    struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu;
+	struct intel_engine_cs *engine;
+	u8 engine_class, engine_instance;
+
+	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+		return -ENODEV;
+
+	engine_class = query_item->flags & 0xFF;
+	engine_instance = (query_item->flags >> 8) & 0xFF;
+
+	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
+
+	if (!engine)
+		return -EINVAL;
+
+	sseu = &engine->gt->info.sseu;
+
+	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
+}
+
 static int
 query_engine_info(struct drm_i915_private *i915,
 		  struct drm_i915_query_item *query_item)
@@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 	query_engine_info,
 	query_perf_config,
 	query_memregion_info,
+	query_geometry_subslices,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 05c3642aaece..1fa6022e1558 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	/** @query_id: The id for this query */
 	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-#define DRM_I915_QUERY_ENGINE_INFO	2
-#define DRM_I915_QUERY_PERF_CONFIG      3
-#define DRM_I915_QUERY_MEMORY_REGIONS   4
+#define DRM_I915_QUERY_TOPOLOGY_INFO		1
+#define DRM_I915_QUERY_ENGINE_INFO		2
+#define DRM_I915_QUERY_PERF_CONFIG		3
+#define DRM_I915_QUERY_MEMORY_REGIONS		4
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
 /* Must be kept compact -- no holes and well documented */
 
 	/**
@@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
 	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
 	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
 	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *
+	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
+	 * as a valid engine class, and bits 8:15 must have a valid engine instance.
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
@@ -2772,16 +2776,20 @@ struct drm_i915_query {
 };
 
 /*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
+ * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
  *
  * data: contains the 3 pieces of information :
  *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
+ * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
+ *   telling whether a slice is available. The availability of slice X can be
+ *   queried with the following formula :
  *
  *           (data[X / 8] >> (X % 8)) & 1
  *
+ * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
+ *   is not used.
+ *
  * - the subslice mask for each slice with one bit per subslice telling
  *   whether a subslice is available. Gen12 has dual-subslices, which are
  *   similar to two gen11 subslices. For gen12, this array represents dual-
-- 
2.21.3


^ permalink raw reply related	[flat|nested] 17+ messages in thread

* [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-10  5:18 ` Matt Atwood
  0 siblings, 0 replies; 17+ messages in thread
From: Matt Atwood @ 2022-03-10  5:18 UTC (permalink / raw)
  To: intel-gfx, dri-devel

Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.

v2: fix white space errors

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
 include/uapi/drm/i915_drm.h       | 24 +++++++----
 2 files changed, 65 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 2dfbc22857a3..e4f35da28642 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_perf.h"
 #include "i915_query.h"
+#include "gt/intel_engine_user.h"
 #include <uapi/drm/i915_drm.h>
 
 static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
 	return 0;
 }
 
-static int query_topology_info(struct drm_i915_private *dev_priv,
-			       struct drm_i915_query_item *query_item)
+static int fill_topology_info(const struct sseu_dev_info *sseu,
+			      struct drm_i915_query_item *query_item,
+			      const u8 *subslice_mask)
 {
-	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
 	int ret;
 
-	if (query_item->flags != 0)
-		return -EINVAL;
+	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	if (sseu->max_slices == 0)
 		return -ENODEV;
 
-	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
-
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
 	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
-	ret = copy_query_item(&topo, sizeof(topo), total_length,
-			      query_item);
+	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
+
 	if (ret != 0)
 		return ret;
 
-	if (topo.flags != 0)
-		return -EINVAL;
-
 	memset(&topo, 0, sizeof(topo));
 	topo.max_slices = sseu->max_slices;
 	topo.max_subslices = sseu->max_subslices;
@@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.eu_stride = sseu->eu_stride;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
-			   &topo, sizeof(topo)))
+			 &topo, sizeof(topo)))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
-			   &sseu->slice_mask, slice_length))
+			 &sseu->slice_mask, slice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) + slice_length),
-			   sseu->subslice_mask, subslice_length))
+					 sizeof(topo) + slice_length),
+			 subslice_mask, subslice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) +
-					   slice_length + subslice_length),
-			   sseu->eu_mask, eu_length))
+					 sizeof(topo) +
+					 slice_length + subslice_length),
+			 sseu->eu_mask, eu_length))
 		return -EFAULT;
 
 	return total_length;
 }
 
+static int query_topology_info(struct drm_i915_private *dev_priv,
+			       struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
+
+	if (query_item->flags != 0)
+		return -EINVAL;
+
+	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
+}
+
+static int query_geometry_subslices(struct drm_i915_private *i915,
+				    struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu;
+	struct intel_engine_cs *engine;
+	u8 engine_class, engine_instance;
+
+	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+		return -ENODEV;
+
+	engine_class = query_item->flags & 0xFF;
+	engine_instance = (query_item->flags >> 8) & 0xFF;
+
+	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
+
+	if (!engine)
+		return -EINVAL;
+
+	sseu = &engine->gt->info.sseu;
+
+	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
+}
+
 static int
 query_engine_info(struct drm_i915_private *i915,
 		  struct drm_i915_query_item *query_item)
@@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 	query_engine_info,
 	query_perf_config,
 	query_memregion_info,
+	query_geometry_subslices,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 05c3642aaece..1fa6022e1558 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	/** @query_id: The id for this query */
 	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-#define DRM_I915_QUERY_ENGINE_INFO	2
-#define DRM_I915_QUERY_PERF_CONFIG      3
-#define DRM_I915_QUERY_MEMORY_REGIONS   4
+#define DRM_I915_QUERY_TOPOLOGY_INFO		1
+#define DRM_I915_QUERY_ENGINE_INFO		2
+#define DRM_I915_QUERY_PERF_CONFIG		3
+#define DRM_I915_QUERY_MEMORY_REGIONS		4
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
 /* Must be kept compact -- no holes and well documented */
 
 	/**
@@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
 	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
 	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
 	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *
+	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
+	 * as a valid engine class, and bits 8:15 must have a valid engine instance.
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
@@ -2772,16 +2776,20 @@ struct drm_i915_query {
 };
 
 /*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
+ * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
  *
  * data: contains the 3 pieces of information :
  *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
+ * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
+ *   telling whether a slice is available. The availability of slice X can be
+ *   queried with the following formula :
  *
  *           (data[X / 8] >> (X % 8)) & 1
  *
+ * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
+ *   is not used.
+ *
  * - the subslice mask for each slice with one bit per subslice telling
  *   whether a subslice is available. Gen12 has dual-subslices, which are
  *   similar to two gen11 subslices. For gen12, this array represents dual-
-- 
2.21.3


^ permalink raw reply related	[flat|nested] 17+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
  2022-03-10  5:18 ` [Intel-gfx] " Matt Atwood
  (?)
@ 2022-03-10  5:47 ` Patchwork
  -1 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-03-10  5:47 UTC (permalink / raw)
  To: Matt Atwood; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
URL   : https://patchwork.freedesktop.org/series/101219/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 17+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
  2022-03-10  5:18 ` [Intel-gfx] " Matt Atwood
  (?)
  (?)
@ 2022-03-10  6:19 ` Patchwork
  -1 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-03-10  6:19 UTC (permalink / raw)
  To: Matt Atwood; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 6910 bytes --]

== Series Details ==

Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
URL   : https://patchwork.freedesktop.org/series/101219/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11347 -> Patchwork_22529
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/index.html

Participating hosts (40 -> 36)
------------------------------

  Additional (2): fi-bxt-dsi fi-icl-u2 
  Missing    (6): bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-rpls-2 bat-jsl-2 bat-jsl-1 

Known issues
------------

  Here are the changes found in Patchwork_22529 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html
    - fi-icl-u2:          NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-bxt-dsi/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [PASS][6] -> [DMESG-FAIL][7] ([i915#2927] / [i915#4528])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][11] ([fdo#109271]) +31 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html
    - fi-icl-u2:          NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-icl-u2:          NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][15] ([i915#3301])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-pnv-d510:        NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2403] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-pnv-d510/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [DMESG-WARN][17] ([i915#295]) -> [PASS][18] +11 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-kbl-guc:         [FAIL][19] ([i915#3049]) -> [SKIP][20] ([fdo#109271])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11347 -> Patchwork_22529

  CI-20190529: 20190529
  CI_DRM_11347: 99965da17d037dcf0bf0c2ebb34804217ab9c018 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6373: 82306f1903c0fee8371f43a156d8b63163ca61c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22529: 762701c3f4e284d685fdb7e24ab08037528c54d8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

762701c3f4e2 drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/index.html

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^ permalink raw reply	[flat|nested] 17+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
  2022-03-10  5:18 ` [Intel-gfx] " Matt Atwood
                   ` (2 preceding siblings ...)
  (?)
@ 2022-03-10 11:45 ` Patchwork
  -1 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-03-10 11:45 UTC (permalink / raw)
  To: Matt Atwood; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30283 bytes --]

== Series Details ==

Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
URL   : https://patchwork.freedesktop.org/series/101219/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11347_full -> Patchwork_22529_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22529_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@mock@vma:
    - {shard-rkl}:        NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-5/igt@i915_selftest@mock@vma.html

  * {igt@kms_setmode@basic@pipe-b-vga-1}:
    - shard-snb:          [FAIL][2] ([i915#31]) -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-snb7/igt@kms_setmode@basic@pipe-b-vga-1.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-snb4/igt@kms_setmode@basic@pipe-b-vga-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_22529_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-4x:
    - shard-apl:          NOTRUN -> [SKIP][4] ([fdo#109271]) +157 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@feature_discovery@display-4x.html

  * igt@gem_ctx_shared@q-smoketest@bcs0:
    - shard-glk:          [PASS][5] -> [DMESG-WARN][6] ([i915#118])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk4/igt@gem_ctx_shared@q-smoketest@bcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk5/igt@gem_ctx_shared@q-smoketest@bcs0.html

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         NOTRUN -> [SKIP][7] ([i915#4525])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-apl6/igt@gem_exec_suspend@basic-s3@smem.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl4/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-skl:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@random:
    - shard-apl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@gem_lmem_swapping@random.html

  * igt@gem_softpin@allocator-evict-all-engines:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#4171])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk5/igt@gem_softpin@allocator-evict-all-engines.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk1/igt@gem_softpin@allocator-evict-all-engines.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][17] ([i915#3297])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-skl:          NOTRUN -> [FAIL][18] ([i915#3318])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#2527] / [i915#2856])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-apl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#658])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-skl:          NOTRUN -> [FAIL][21] ([i915#454])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([i915#5286])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglb:         NOTRUN -> [SKIP][23] ([i915#5286])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][25] ([i915#3743])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +6 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([fdo#111615] / [i915#3689]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +4 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-skl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +16 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][32] ([fdo#109278] / [fdo#109279])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([fdo#109279] / [i915#3359])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#109274] / [fdo#111825]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([i915#2346])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled:
    - shard-tglb:         NOTRUN -> [SKIP][37] ([i915#5287])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#109274])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          NOTRUN -> [FAIL][39] ([i915#2122])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
    - shard-skl:          [PASS][40] -> [FAIL][41] ([i915#2122]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][42] ([fdo#109271]) +189 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109280]) +4 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#109280] / [fdo#111825]) +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([i915#1188])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl4/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl1/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-skl:          NOTRUN -> [FAIL][49] ([fdo#108145] / [i915#265])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#658]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][51] -> [SKIP][52] ([fdo#109441]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb5/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([fdo#109278]) +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html

  * igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([i915#2530])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html

  * igt@perf@mi-rpc:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#109289]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@perf@mi-rpc.html

  * igt@prime_nv_pcopy@test1_macro:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#109291])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@prime_nv_pcopy@test1_macro.html

  * igt@prime_nv_pcopy@test_semaphore:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#109291])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb2/igt@prime_nv_pcopy@test_semaphore.html

  * igt@syncobj_timeline@invalid-transfer-non-existent-point:
    - shard-skl:          NOTRUN -> [DMESG-WARN][58] ([i915#5098])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl7/igt@syncobj_timeline@invalid-transfer-non-existent-point.html

  * igt@syncobj_timeline@transfer-timeline-point:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][59] ([i915#5098])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@syncobj_timeline@transfer-timeline-point.html

  * igt@sysfs_clients@fair-0:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2994])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl4/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@fair-7:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([i915#2994])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@split-25:
    - shard-skl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2994])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@sysfs_clients@split-25.html

  
#### Possible fixes ####

  * igt@fbdev@unaligned-read:
    - {shard-rkl}:        [SKIP][63] ([i915#2582]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@fbdev@unaligned-read.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][65] ([i915#658]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb7/igt@feature_discovery@psr2.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [TIMEOUT][67] ([i915#2481] / [i915#3070]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb3/igt@gem_eio@unwedge-stress.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb8/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_capture@pi@bcs0:
    - {shard-rkl}:        [INCOMPLETE][69] ([i915#3371]) -> ([PASS][70], [PASS][71])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@gem_exec_capture@pi@bcs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-4/igt@gem_exec_capture@pi@bcs0.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-5/igt@gem_exec_capture@pi@bcs0.html
    - shard-iclb:         [INCOMPLETE][72] ([i915#3371]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb5/igt@gem_exec_capture@pi@bcs0.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb7/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][74] ([i915#2846]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk1/igt@gem_exec_fair@basic-deadline.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-kbl:          [FAIL][76] ([i915#2842]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][78] ([i915#2842]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - {shard-tglu}:       [FAIL][80] ([i915#2842]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-apl:          [FAIL][82] ([i915#2842]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-apl8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-glk:          [FAIL][84] ([i915#2842]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk4/igt@gem_exec_fair@basic-pace@rcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_mmap_offset@open-flood:
    - {shard-rkl}:        [INCOMPLETE][86] ([i915#5080]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@gem_mmap_offset@open-flood.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-2/igt@gem_mmap_offset@open-flood.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][88] ([i915#1373] / [i915#4939] / [i915#5230]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl6/igt@gem_softpin@noreloc-s3.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-snb:          [TIMEOUT][90] ([i915#4995]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-snb5/igt@gem_workarounds@suspend-resume-context.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-snb2/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_backlight@fade:
    - {shard-rkl}:        [SKIP][92] ([i915#3012]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@i915_pm_backlight@fade.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@i915_pm_backlight@fade.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][94] ([i915#454]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
    - {shard-tglu}:       [FAIL][96] ([i915#454]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-tglu-5/igt@i915_pm_dc@dc6-dpms.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - {shard-dg1}:        [SKIP][98] ([i915#1397]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-dg1-13/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_selftest@live@hangcheck:
    - shard-skl:          [INCOMPLETE][100] -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl10/igt@i915_selftest@live@hangcheck.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl8/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - {shard-tglu}:       [DMESG-WARN][102] ([i915#402]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-tglu-4/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-tglu-1/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][104] ([i915#1845] / [i915#4098]) -> [PASS][105] +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs.html

  * igt@kms_color@pipe-a-ctm-max:
    - {shard-rkl}:        [SKIP][106] ([i915#1149] / [i915#1849]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@kms_color@pipe-a-ctm-max.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_color@pipe-a-ctm-max.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - {shard-rkl}:        [SKIP][108] ([fdo#112022] / [i915#4070]) -> [PASS][109] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
    - {shard-rkl}:        [SKIP][110] ([fdo#112022]) -> [PASS][111] +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +2 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
    - {shard-rkl}:        [SKIP][114] ([i915#1849] / [i915#4070]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html

  * igt@kms_cursor_legacy@all-pipes-torture-bo:
    - shard-skl:          [INCOMPLETE][116] ([i915#1373]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl10/igt@kms_cursor_legacy@all-pipes-torture-bo.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl9/igt@kms_cursor_legacy@all-pipes-torture-bo.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - {shard-rkl}:        [SKIP][118] ([fdo#111825] / [i915#4070]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_cursor_legacy@pipe-c-forked-move:
    - {shard-rkl}:        [SKIP][120] ([i915#4070]) -> ([PASS][121], [PASS][122])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_cursor_legacy@pipe-c-forked-move.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-4/igt@kms_cursor_legacy@pipe-c-forked-move.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-forked-move.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled:
    - {shard-rkl}:        [SKIP][123] ([fdo#111314] / [i915#4369]) -> [PASS][124] +1 similar issue
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][125] ([i915#79]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
    - shard-skl:          [FAIL][127] ([i915#2122]) -> [PASS][128] +2 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][129] ([i915#79]) -> [PASS][130] +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-iclb:         [SKIP][131] ([i915#3701]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - {shard-rkl}:        [SKIP][133] ([i915#1849]) -> [PASS][134] +10 similar issues
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
    - shard-skl:          [FAIL][135] ([i915#1188]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl4/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl5/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html

  * igt@kms_invalid_mode@zero-clock:
    - {shard-rkl}:        [SKIP][137] ([i915#4278]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-5/igt@kms_invalid_mode@zero-clock.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - {shard-rkl}:        [SKIP][139] ([i915#1849] / [i915#3558]) -> [PASS][140] +1 similar issue
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][141] ([fdo#108145] / [i915#265]) -> [PASS][142]
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_cursor@pipe-b-viewport-size-128:
    - {shard-rkl}:        ([SKIP][143], [SKIP][144]) ([i915#1845]) -> [PASS][145]
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-rkl-2/igt@kms_plane_cursor@pipe-b-viewport-size-128.html
   [144]: https://intel-gfx-ci.01.org/tree/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22529/index.html

[-- Attachment #2: Type: text/html, Size: 33364 bytes --]

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-10  5:18 ` [Intel-gfx] " Matt Atwood
                   ` (3 preceding siblings ...)
  (?)
@ 2022-03-10 12:26 ` Tvrtko Ursulin
  2022-03-12  4:16   ` Matt Atwood
  -1 siblings, 1 reply; 17+ messages in thread
From: Tvrtko Ursulin @ 2022-03-10 12:26 UTC (permalink / raw)
  To: Matt Atwood, intel-gfx, dri-devel


On 10/03/2022 05:18, Matt Atwood wrote:
> Newer platforms have DSS that aren't necessarily available for both
> geometry and compute, two queries will need to exist. This introduces
> the first, when passing a valid engine class and engine instance in the
> flags returns a topology describing geometry.
> 
> v2: fix white space errors
> 
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
>   include/uapi/drm/i915_drm.h       | 24 +++++++----
>   2 files changed, 65 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 2dfbc22857a3..e4f35da28642 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -9,6 +9,7 @@
>   #include "i915_drv.h"
>   #include "i915_perf.h"
>   #include "i915_query.h"
> +#include "gt/intel_engine_user.h"
>   #include <uapi/drm/i915_drm.h>
>   
>   static int copy_query_item(void *query_hdr, size_t query_sz,
> @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>   	return 0;
>   }
>   
> -static int query_topology_info(struct drm_i915_private *dev_priv,
> -			       struct drm_i915_query_item *query_item)
> +static int fill_topology_info(const struct sseu_dev_info *sseu,
> +			      struct drm_i915_query_item *query_item,
> +			      const u8 *subslice_mask)
>   {
> -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>   	struct drm_i915_query_topology_info topo;
>   	u32 slice_length, subslice_length, eu_length, total_length;
>   	int ret;
>   
> -	if (query_item->flags != 0)
> -		return -EINVAL;
> +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>   
>   	if (sseu->max_slices == 0)
>   		return -ENODEV;
>   
> -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> -
>   	slice_length = sizeof(sseu->slice_mask);
>   	subslice_length = sseu->max_slices * sseu->ss_stride;
>   	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>   	total_length = sizeof(topo) + slice_length + subslice_length +
>   		       eu_length;
>   
> -	ret = copy_query_item(&topo, sizeof(topo), total_length,
> -			      query_item);
> +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
> +
>   	if (ret != 0)
>   		return ret;
>   
> -	if (topo.flags != 0)
> -		return -EINVAL;
> -
>   	memset(&topo, 0, sizeof(topo));
>   	topo.max_slices = sseu->max_slices;
>   	topo.max_subslices = sseu->max_subslices;
> @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>   	topo.eu_stride = sseu->eu_stride;
>   
>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> -			   &topo, sizeof(topo)))
> +			 &topo, sizeof(topo)))
>   		return -EFAULT;
>   
>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
> -			   &sseu->slice_mask, slice_length))
> +			 &sseu->slice_mask, slice_length))
>   		return -EFAULT;
>   
>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> -					   sizeof(topo) + slice_length),
> -			   sseu->subslice_mask, subslice_length))
> +					 sizeof(topo) + slice_length),
> +			 subslice_mask, subslice_length))
>   		return -EFAULT;
>   
>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> -					   sizeof(topo) +
> -					   slice_length + subslice_length),
> -			   sseu->eu_mask, eu_length))
> +					 sizeof(topo) +
> +					 slice_length + subslice_length),
> +			 sseu->eu_mask, eu_length))
>   		return -EFAULT;
>   
>   	return total_length;
>   }
>   
> +static int query_topology_info(struct drm_i915_private *dev_priv,
> +			       struct drm_i915_query_item *query_item)
> +{
> +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> +
> +	if (query_item->flags != 0)
> +		return -EINVAL;
> +
> +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
> +}
> +
> +static int query_geometry_subslices(struct drm_i915_private *i915,
> +				    struct drm_i915_query_item *query_item)
> +{
> +	const struct sseu_dev_info *sseu;
> +	struct intel_engine_cs *engine;
> +	u8 engine_class, engine_instance;
> +
> +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> +		return -ENODEV;
> +
> +	engine_class = query_item->flags & 0xFF;
> +	engine_instance = (query_item->flags >> 8) & 0xFF;
> +
> +	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
> +
> +	if (!engine)
> +		return -EINVAL;
> +
> +	sseu = &engine->gt->info.sseu;
> +
> +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> +}
> +
>   static int
>   query_engine_info(struct drm_i915_private *i915,
>   		  struct drm_i915_query_item *query_item)
> @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   	query_engine_info,
>   	query_perf_config,
>   	query_memregion_info,
> +	query_geometry_subslices,
>   };
>   
>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 05c3642aaece..1fa6022e1558 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
>   struct drm_i915_query_item {
>   	/** @query_id: The id for this query */
>   	__u64 query_id;
> -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> -#define DRM_I915_QUERY_ENGINE_INFO	2
> -#define DRM_I915_QUERY_PERF_CONFIG      3
> -#define DRM_I915_QUERY_MEMORY_REGIONS   4
> +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
> +#define DRM_I915_QUERY_ENGINE_INFO		2
> +#define DRM_I915_QUERY_PERF_CONFIG		3
> +#define DRM_I915_QUERY_MEMORY_REGIONS		4
> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
>   /* Must be kept compact -- no holes and well documented */
>   
>   	/**
> @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
>   	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
>   	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
>   	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> +	 *
> +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
> +	 * as a valid engine class, and bits 8:15 must have a valid engine instance.

Alternatively, all other uapi uses struct i915_engine_class_instance to 
address engines which uses u16:u16.

How ugly it is to stuff a struct into u32 flags is the question... But 
you could at least use u16:u16 for consistency. Unless you wanted to 
leave some bits free for the future?

Regards,

Tvrtko

>   	 */
>   	__u32 flags;
>   #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
> @@ -2772,16 +2776,20 @@ struct drm_i915_query {
>   };
>   
>   /*
> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
> + * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
>    *
>    * data: contains the 3 pieces of information :
>    *
> - * - the slice mask with one bit per slice telling whether a slice is
> - *   available. The availability of slice X can be queried with the following
> - *   formula :
> + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
> + *   telling whether a slice is available. The availability of slice X can be
> + *   queried with the following formula :
>    *
>    *           (data[X / 8] >> (X % 8)) & 1
>    *
> + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
> + *   is not used.
> + *
>    * - the subslice mask for each slice with one bit per subslice telling
>    *   whether a subslice is available. Gen12 has dual-subslices, which are
>    *   similar to two gen11 subslices. For gen12, this array represents dual-

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-10 12:26 ` [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES Tvrtko Ursulin
@ 2022-03-12  4:16   ` Matt Atwood
  2022-03-14 15:35     ` Tvrtko Ursulin
  0 siblings, 1 reply; 17+ messages in thread
From: Matt Atwood @ 2022-03-12  4:16 UTC (permalink / raw)
  To: Tvrtko Ursulin

On Thu, Mar 10, 2022 at 12:26:12PM +0000, Tvrtko Ursulin wrote:
> 
> On 10/03/2022 05:18, Matt Atwood wrote:
> > Newer platforms have DSS that aren't necessarily available for both
> > geometry and compute, two queries will need to exist. This introduces
> > the first, when passing a valid engine class and engine instance in the
> > flags returns a topology describing geometry.
> > 
> > v2: fix white space errors
> > 
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
> >   include/uapi/drm/i915_drm.h       | 24 +++++++----
> >   2 files changed, 65 insertions(+), 27 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > index 2dfbc22857a3..e4f35da28642 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -9,6 +9,7 @@
> >   #include "i915_drv.h"
> >   #include "i915_perf.h"
> >   #include "i915_query.h"
> > +#include "gt/intel_engine_user.h"
> >   #include <uapi/drm/i915_drm.h>
> >   static int copy_query_item(void *query_hdr, size_t query_sz,
> > @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> >   	return 0;
> >   }
> > -static int query_topology_info(struct drm_i915_private *dev_priv,
> > -			       struct drm_i915_query_item *query_item)
> > +static int fill_topology_info(const struct sseu_dev_info *sseu,
> > +			      struct drm_i915_query_item *query_item,
> > +			      const u8 *subslice_mask)
> >   {
> > -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> >   	struct drm_i915_query_topology_info topo;
> >   	u32 slice_length, subslice_length, eu_length, total_length;
> >   	int ret;
> > -	if (query_item->flags != 0)
> > -		return -EINVAL;
> > +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> >   	if (sseu->max_slices == 0)
> >   		return -ENODEV;
> > -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> > -
> >   	slice_length = sizeof(sseu->slice_mask);
> >   	subslice_length = sseu->max_slices * sseu->ss_stride;
> >   	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
> >   	total_length = sizeof(topo) + slice_length + subslice_length +
> >   		       eu_length;
> > -	ret = copy_query_item(&topo, sizeof(topo), total_length,
> > -			      query_item);
> > +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
> > +
> >   	if (ret != 0)
> >   		return ret;
> > -	if (topo.flags != 0)
> > -		return -EINVAL;
> > -
> >   	memset(&topo, 0, sizeof(topo));
> >   	topo.max_slices = sseu->max_slices;
> >   	topo.max_subslices = sseu->max_subslices;
> > @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
> >   	topo.eu_stride = sseu->eu_stride;
> >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> > -			   &topo, sizeof(topo)))
> > +			 &topo, sizeof(topo)))
> >   		return -EFAULT;
> >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
> > -			   &sseu->slice_mask, slice_length))
> > +			 &sseu->slice_mask, slice_length))
> >   		return -EFAULT;
> >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > -					   sizeof(topo) + slice_length),
> > -			   sseu->subslice_mask, subslice_length))
> > +					 sizeof(topo) + slice_length),
> > +			 subslice_mask, subslice_length))
> >   		return -EFAULT;
> >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > -					   sizeof(topo) +
> > -					   slice_length + subslice_length),
> > -			   sseu->eu_mask, eu_length))
> > +					 sizeof(topo) +
> > +					 slice_length + subslice_length),
> > +			 sseu->eu_mask, eu_length))
> >   		return -EFAULT;
> >   	return total_length;
> >   }
> > +static int query_topology_info(struct drm_i915_private *dev_priv,
> > +			       struct drm_i915_query_item *query_item)
> > +{
> > +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> > +
> > +	if (query_item->flags != 0)
> > +		return -EINVAL;
> > +
> > +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
> > +}
> > +
> > +static int query_geometry_subslices(struct drm_i915_private *i915,
> > +				    struct drm_i915_query_item *query_item)
> > +{
> > +	const struct sseu_dev_info *sseu;
> > +	struct intel_engine_cs *engine;
> > +	u8 engine_class, engine_instance;
> > +
> > +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > +		return -ENODEV;
> > +
> > +	engine_class = query_item->flags & 0xFF;
> > +	engine_instance = (query_item->flags >> 8) & 0xFF;
> > +
> > +	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
> > +
> > +	if (!engine)
> > +		return -EINVAL;
> > +
> > +	sseu = &engine->gt->info.sseu;
> > +
> > +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> > +}
> > +
> >   static int
> >   query_engine_info(struct drm_i915_private *i915,
> >   		  struct drm_i915_query_item *query_item)
> > @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> >   	query_engine_info,
> >   	query_perf_config,
> >   	query_memregion_info,
> > +	query_geometry_subslices,
> >   };
> >   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 05c3642aaece..1fa6022e1558 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
> >   struct drm_i915_query_item {
> >   	/** @query_id: The id for this query */
> >   	__u64 query_id;
> > -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> > -#define DRM_I915_QUERY_ENGINE_INFO	2
> > -#define DRM_I915_QUERY_PERF_CONFIG      3
> > -#define DRM_I915_QUERY_MEMORY_REGIONS   4
> > +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
> > +#define DRM_I915_QUERY_ENGINE_INFO		2
> > +#define DRM_I915_QUERY_PERF_CONFIG		3
> > +#define DRM_I915_QUERY_MEMORY_REGIONS		4
> > +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
> >   /* Must be kept compact -- no holes and well documented */
> >   	/**
> > @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
> >   	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
> >   	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> >   	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> > +	 *
> > +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
> > +	 * as a valid engine class, and bits 8:15 must have a valid engine instance.
> 
> Alternatively, all other uapi uses struct i915_engine_class_instance to
> address engines which uses u16:u16.
> 
> How ugly it is to stuff a struct into u32 flags is the question... But you
> could at least use u16:u16 for consistency. Unless you wanted to leave some
> bits free for the future?
Originally when I wrote this I was wanting to leave space in case it was
ever needed. I'm not particularly for or against keeping the space now. 
MattA
> 
> Regards,
> 
> Tvrtko
> 
> >   	 */
> >   	__u32 flags;
> >   #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
> > @@ -2772,16 +2776,20 @@ struct drm_i915_query {
> >   };
> >   /*
> > - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> > + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
> > + * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
> >    *
> >    * data: contains the 3 pieces of information :
> >    *
> > - * - the slice mask with one bit per slice telling whether a slice is
> > - *   available. The availability of slice X can be queried with the following
> > - *   formula :
> > + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
> > + *   telling whether a slice is available. The availability of slice X can be
> > + *   queried with the following formula :
> >    *
> >    *           (data[X / 8] >> (X % 8)) & 1
> >    *
> > + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
> > + *   is not used.
> > + *
> >    * - the subslice mask for each slice with one bit per subslice telling
> >    *   whether a subslice is available. Gen12 has dual-subslices, which are
> >    *   similar to two gen11 subslices. For gen12, this array represents dual-

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-12  4:16   ` Matt Atwood
@ 2022-03-14 15:35     ` Tvrtko Ursulin
  2022-03-14 17:50         ` Dixit, Ashutosh
  2022-03-16 11:30       ` Joonas Lahtinen
  0 siblings, 2 replies; 17+ messages in thread
From: Tvrtko Ursulin @ 2022-03-14 15:35 UTC (permalink / raw)
  To: Matt Atwood, intel-gfx, dri-devel


On 12/03/2022 04:16, Matt Atwood wrote:
> On Thu, Mar 10, 2022 at 12:26:12PM +0000, Tvrtko Ursulin wrote:
>>
>> On 10/03/2022 05:18, Matt Atwood wrote:
>>> Newer platforms have DSS that aren't necessarily available for both
>>> geometry and compute, two queries will need to exist. This introduces
>>> the first, when passing a valid engine class and engine instance in the
>>> flags returns a topology describing geometry.
>>>
>>> v2: fix white space errors
>>>
>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
>>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
>>>    include/uapi/drm/i915_drm.h       | 24 +++++++----
>>>    2 files changed, 65 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
>>> index 2dfbc22857a3..e4f35da28642 100644
>>> --- a/drivers/gpu/drm/i915/i915_query.c
>>> +++ b/drivers/gpu/drm/i915/i915_query.c
>>> @@ -9,6 +9,7 @@
>>>    #include "i915_drv.h"
>>>    #include "i915_perf.h"
>>>    #include "i915_query.h"
>>> +#include "gt/intel_engine_user.h"
>>>    #include <uapi/drm/i915_drm.h>
>>>    static int copy_query_item(void *query_hdr, size_t query_sz,
>>> @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>>>    	return 0;
>>>    }
>>> -static int query_topology_info(struct drm_i915_private *dev_priv,
>>> -			       struct drm_i915_query_item *query_item)
>>> +static int fill_topology_info(const struct sseu_dev_info *sseu,
>>> +			      struct drm_i915_query_item *query_item,
>>> +			      const u8 *subslice_mask)
>>>    {
>>> -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>>>    	struct drm_i915_query_topology_info topo;
>>>    	u32 slice_length, subslice_length, eu_length, total_length;
>>>    	int ret;
>>> -	if (query_item->flags != 0)
>>> -		return -EINVAL;
>>> +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>>>    	if (sseu->max_slices == 0)
>>>    		return -ENODEV;
>>> -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>>> -
>>>    	slice_length = sizeof(sseu->slice_mask);
>>>    	subslice_length = sseu->max_slices * sseu->ss_stride;
>>>    	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>>>    	total_length = sizeof(topo) + slice_length + subslice_length +
>>>    		       eu_length;
>>> -	ret = copy_query_item(&topo, sizeof(topo), total_length,
>>> -			      query_item);
>>> +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
>>> +
>>>    	if (ret != 0)
>>>    		return ret;
>>> -	if (topo.flags != 0)
>>> -		return -EINVAL;
>>> -
>>>    	memset(&topo, 0, sizeof(topo));
>>>    	topo.max_slices = sseu->max_slices;
>>>    	topo.max_subslices = sseu->max_subslices;
>>> @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>>>    	topo.eu_stride = sseu->eu_stride;
>>>    	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>>> -			   &topo, sizeof(topo)))
>>> +			 &topo, sizeof(topo)))
>>>    		return -EFAULT;
>>>    	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
>>> -			   &sseu->slice_mask, slice_length))
>>> +			 &sseu->slice_mask, slice_length))
>>>    		return -EFAULT;
>>>    	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>>> -					   sizeof(topo) + slice_length),
>>> -			   sseu->subslice_mask, subslice_length))
>>> +					 sizeof(topo) + slice_length),
>>> +			 subslice_mask, subslice_length))
>>>    		return -EFAULT;
>>>    	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>>> -					   sizeof(topo) +
>>> -					   slice_length + subslice_length),
>>> -			   sseu->eu_mask, eu_length))
>>> +					 sizeof(topo) +
>>> +					 slice_length + subslice_length),
>>> +			 sseu->eu_mask, eu_length))
>>>    		return -EFAULT;
>>>    	return total_length;
>>>    }
>>> +static int query_topology_info(struct drm_i915_private *dev_priv,
>>> +			       struct drm_i915_query_item *query_item)
>>> +{
>>> +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>>> +
>>> +	if (query_item->flags != 0)
>>> +		return -EINVAL;
>>> +
>>> +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
>>> +}
>>> +
>>> +static int query_geometry_subslices(struct drm_i915_private *i915,
>>> +				    struct drm_i915_query_item *query_item)
>>> +{
>>> +	const struct sseu_dev_info *sseu;
>>> +	struct intel_engine_cs *engine;
>>> +	u8 engine_class, engine_instance;
>>> +
>>> +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>>> +		return -ENODEV;
>>> +
>>> +	engine_class = query_item->flags & 0xFF;
>>> +	engine_instance = (query_item->flags >> 8) & 0xFF;
>>> +
>>> +	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
>>> +
>>> +	if (!engine)
>>> +		return -EINVAL;
>>> +
>>> +	sseu = &engine->gt->info.sseu;
>>> +
>>> +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
>>> +}
>>> +
>>>    static int
>>>    query_engine_info(struct drm_i915_private *i915,
>>>    		  struct drm_i915_query_item *query_item)
>>> @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>>>    	query_engine_info,
>>>    	query_perf_config,
>>>    	query_memregion_info,
>>> +	query_geometry_subslices,
>>>    };
>>>    int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>>> index 05c3642aaece..1fa6022e1558 100644
>>> --- a/include/uapi/drm/i915_drm.h
>>> +++ b/include/uapi/drm/i915_drm.h
>>> @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
>>>    struct drm_i915_query_item {
>>>    	/** @query_id: The id for this query */
>>>    	__u64 query_id;
>>> -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
>>> -#define DRM_I915_QUERY_ENGINE_INFO	2
>>> -#define DRM_I915_QUERY_PERF_CONFIG      3
>>> -#define DRM_I915_QUERY_MEMORY_REGIONS   4
>>> +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
>>> +#define DRM_I915_QUERY_ENGINE_INFO		2
>>> +#define DRM_I915_QUERY_PERF_CONFIG		3
>>> +#define DRM_I915_QUERY_MEMORY_REGIONS		4
>>> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
>>>    /* Must be kept compact -- no holes and well documented */
>>>    	/**
>>> @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
>>>    	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
>>>    	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
>>>    	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
>>> +	 *
>>> +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
>>> +	 * as a valid engine class, and bits 8:15 must have a valid engine instance.
>>
>> Alternatively, all other uapi uses struct i915_engine_class_instance to
>> address engines which uses u16:u16.
>>
>> How ugly it is to stuff a struct into u32 flags is the question... But you
>> could at least use u16:u16 for consistency. Unless you wanted to leave some
>> bits free for the future?
> Originally when I wrote this I was wanting to leave space in case it was
> ever needed. I'm not particularly for or against keeping the space now.

Yes, shrug... Neither I can't guess if we are ever likely to hit a 
problem by having fewer bits for class:instance here compared to other 
uapi, or if stuffing struct i915_engine_class_instance into flags would 
just be too ugly. I mean there is option to define a new struct and not 
use flags at all but that's probably to complicated for what it is.

Anyone else with an opinion? Consistency or should be fine even like it is?

Regards,

Tvrtko

> MattA
>>
>> Regards,
>>
>> Tvrtko
>>
>>>    	 */
>>>    	__u32 flags;
>>>    #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
>>> @@ -2772,16 +2776,20 @@ struct drm_i915_query {
>>>    };
>>>    /*
>>> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
>>> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
>>> + * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
>>>     *
>>>     * data: contains the 3 pieces of information :
>>>     *
>>> - * - the slice mask with one bit per slice telling whether a slice is
>>> - *   available. The availability of slice X can be queried with the following
>>> - *   formula :
>>> + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
>>> + *   telling whether a slice is available. The availability of slice X can be
>>> + *   queried with the following formula :
>>>     *
>>>     *           (data[X / 8] >> (X % 8)) & 1
>>>     *
>>> + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
>>> + *   is not used.
>>> + *
>>>     * - the subslice mask for each slice with one bit per subslice telling
>>>     *   whether a subslice is available. Gen12 has dual-subslices, which are
>>>     *   similar to two gen11 subslices. For gen12, this array represents dual-

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-14 15:35     ` Tvrtko Ursulin
@ 2022-03-14 17:50         ` Dixit, Ashutosh
  2022-03-16 11:30       ` Joonas Lahtinen
  1 sibling, 0 replies; 17+ messages in thread
From: Dixit, Ashutosh @ 2022-03-14 17:50 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx, Matt Atwood, dri-devel

On Mon, 14 Mar 2022 08:35:17 -0700, Tvrtko Ursulin wrote:
>
> >> Alternatively, all other uapi uses struct i915_engine_class_instance to
> >> address engines which uses u16:u16.
> >>
> >> How ugly it is to stuff a struct into u32 flags is the question... But you
> >> could at least use u16:u16 for consistency. Unless you wanted to leave some
> >> bits free for the future?
> > Originally when I wrote this I was wanting to leave space in case it was
> > ever needed. I'm not particularly for or against keeping the space now.
>
> Yes, shrug... Neither I can't guess if we are ever likely to hit a problem
> by having fewer bits for class:instance here compared to other uapi, or if
> stuffing struct i915_engine_class_instance into flags would just be too
> ugly. I mean there is option to define a new struct and not use flags at
> all but that's probably to complicated for what it is.
>
> Anyone else with an opinion? Consistency or should be fine even like it is?

Consistency. I'd prefer to stuff struct i915_engine_class_instance into
flags, fwiw.

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-14 17:50         ` Dixit, Ashutosh
  0 siblings, 0 replies; 17+ messages in thread
From: Dixit, Ashutosh @ 2022-03-14 17:50 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel

On Mon, 14 Mar 2022 08:35:17 -0700, Tvrtko Ursulin wrote:
>
> >> Alternatively, all other uapi uses struct i915_engine_class_instance to
> >> address engines which uses u16:u16.
> >>
> >> How ugly it is to stuff a struct into u32 flags is the question... But you
> >> could at least use u16:u16 for consistency. Unless you wanted to leave some
> >> bits free for the future?
> > Originally when I wrote this I was wanting to leave space in case it was
> > ever needed. I'm not particularly for or against keeping the space now.
>
> Yes, shrug... Neither I can't guess if we are ever likely to hit a problem
> by having fewer bits for class:instance here compared to other uapi, or if
> stuffing struct i915_engine_class_instance into flags would just be too
> ugly. I mean there is option to define a new struct and not use flags at
> all but that's probably to complicated for what it is.
>
> Anyone else with an opinion? Consistency or should be fine even like it is?

Consistency. I'd prefer to stuff struct i915_engine_class_instance into
flags, fwiw.

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-14 15:35     ` Tvrtko Ursulin
  2022-03-14 17:50         ` Dixit, Ashutosh
@ 2022-03-16 11:30       ` Joonas Lahtinen
  1 sibling, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2022-03-16 11:30 UTC (permalink / raw)
  To: Matt Atwood, Tvrtko Ursulin, dri-devel, intel-gfx

Quoting Tvrtko Ursulin (2022-03-14 17:35:17)
> 
> On 12/03/2022 04:16, Matt Atwood wrote:
> > On Thu, Mar 10, 2022 at 12:26:12PM +0000, Tvrtko Ursulin wrote:
> >>
> >> On 10/03/2022 05:18, Matt Atwood wrote:
> >>> Newer platforms have DSS that aren't necessarily available for both
> >>> geometry and compute, two queries will need to exist. This introduces
> >>> the first, when passing a valid engine class and engine instance in the
> >>> flags returns a topology describing geometry.
> >>>
> >>> v2: fix white space errors
> >>>
> >>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >>> Cc: Matt Roper <matthew.d.roper@intel.com>
> >>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >>> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> >>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>

<SNIP>

> >>> @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
> >>>      *      - DRM_I915_QUERY_PERF_CONFIG_LIST
> >>>      *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> >>>      *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> >>> +    *
> >>> +    * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
> >>> +    * as a valid engine class, and bits 8:15 must have a valid engine instance.
> >>
> >> Alternatively, all other uapi uses struct i915_engine_class_instance to
> >> address engines which uses u16:u16.
> >>
> >> How ugly it is to stuff a struct into u32 flags is the question... But you
> >> could at least use u16:u16 for consistency. Unless you wanted to leave some
> >> bits free for the future?
> > Originally when I wrote this I was wanting to leave space in case it was
> > ever needed. I'm not particularly for or against keeping the space now.
> 
> Yes, shrug... Neither I can't guess if we are ever likely to hit a 
> problem by having fewer bits for class:instance here compared to other 
> uapi, or if stuffing struct i915_engine_class_instance into flags would 
> just be too ugly. I mean there is option to define a new struct and not 
> use flags at all but that's probably to complicated for what it is.
> 
> Anyone else with an opinion? Consistency or should be fine even like it is?

Stuffing a full i915_engine_class_instance was definitely intended when
putting it into the flags was suggested.

If that is hit with a complication, the next proposed alternative was a
new struct. That's why the query interface was made easily extensible,
after all...

Regards, Joonas

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-28  8:44   ` Tvrtko Ursulin
@ 2022-03-28 16:01       ` Matt Roper
  0 siblings, 0 replies; 17+ messages in thread
From: Matt Roper @ 2022-03-28 16:01 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx, Matt Atwood, dri-devel

On Mon, Mar 28, 2022 at 09:44:36AM +0100, Tvrtko Ursulin wrote:
> 
> + Joonas
> 
> On 25/03/2022 23:03, Francisco Jerez wrote:
> > Matt Atwood <matthew.s.atwood@intel.com> writes:
> > 
> > > Newer platforms have DSS that aren't necessarily available for both
> > > geometry and compute, two queries will need to exist. This introduces
> > > the first, when passing a valid engine class and engine instance in the
> > > flags returns a topology describing geometry.
> > > 
> > > v2: fix white space errors
> > > v3: change flags from hosting 2 8 bit numbers to holding a
> > > i915_engine_class_instance struct
> > > 
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
> > >   include/uapi/drm/i915_drm.h       | 24 +++++++----
> > >   2 files changed, 65 insertions(+), 27 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > > index 2dfbc22857a3..fcb374201edb 100644
> > > --- a/drivers/gpu/drm/i915/i915_query.c
> > > +++ b/drivers/gpu/drm/i915/i915_query.c
> > > @@ -9,6 +9,7 @@
> > >   #include "i915_drv.h"
> > >   #include "i915_perf.h"
> > >   #include "i915_query.h"
> > > +#include "gt/intel_engine_user.h"
> > >   #include <uapi/drm/i915_drm.h>
> > >   static int copy_query_item(void *query_hdr, size_t query_sz,
> > > @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> > >   	return 0;
> > >   }
> > > -static int query_topology_info(struct drm_i915_private *dev_priv,
> > > -			       struct drm_i915_query_item *query_item)
> > > +static int fill_topology_info(const struct sseu_dev_info *sseu,
> > > +			      struct drm_i915_query_item *query_item,
> > > +			      const u8 *subslice_mask)
> > >   {
> > > -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> > >   	struct drm_i915_query_topology_info topo;
> > >   	u32 slice_length, subslice_length, eu_length, total_length;
> > >   	int ret;
> > > -	if (query_item->flags != 0)
> > > -		return -EINVAL;
> > > +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> > >   	if (sseu->max_slices == 0)
> > >   		return -ENODEV;
> > > -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> > > -
> > >   	slice_length = sizeof(sseu->slice_mask);
> > >   	subslice_length = sseu->max_slices * sseu->ss_stride;
> > >   	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
> > >   	total_length = sizeof(topo) + slice_length + subslice_length +
> > >   		       eu_length;
> > > -	ret = copy_query_item(&topo, sizeof(topo), total_length,
> > > -			      query_item);
> > > +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
> > > +
> > >   	if (ret != 0)
> > >   		return ret;
> > > -	if (topo.flags != 0)
> > > -		return -EINVAL;
> > > -
> > >   	memset(&topo, 0, sizeof(topo));
> > >   	topo.max_slices = sseu->max_slices;
> > >   	topo.max_subslices = sseu->max_subslices;
> > > @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
> > >   	topo.eu_stride = sseu->eu_stride;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> > > -			   &topo, sizeof(topo)))
> > > +			 &topo, sizeof(topo)))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
> > > -			   &sseu->slice_mask, slice_length))
> > > +			 &sseu->slice_mask, slice_length))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > > -					   sizeof(topo) + slice_length),
> > > -			   sseu->subslice_mask, subslice_length))
> > > +					 sizeof(topo) + slice_length),
> > > +			 subslice_mask, subslice_length))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > > -					   sizeof(topo) +
> > > -					   slice_length + subslice_length),
> > > -			   sseu->eu_mask, eu_length))
> > > +					 sizeof(topo) +
> > > +					 slice_length + subslice_length),
> > > +			 sseu->eu_mask, eu_length))
> > >   		return -EFAULT;
> > >   	return total_length;
> > >   }
> > > +static int query_topology_info(struct drm_i915_private *dev_priv,
> > > +			       struct drm_i915_query_item *query_item)
> > > +{
> > > +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> > > +
> > > +	if (query_item->flags != 0)
> > > +		return -EINVAL;
> > > +
> > > +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
> > > +}
> > > +
> > > +static int query_geometry_subslices(struct drm_i915_private *i915,
> > > +				    struct drm_i915_query_item *query_item)
> > > +{
> > > +	const struct sseu_dev_info *sseu;
> > > +	struct intel_engine_cs *engine;
> > > +	struct i915_engine_class_instance classinstance;
> > > +
> > > +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > > +		return -ENODEV;
> > > +
> > > +	classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
> > > +
> > > +	engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class,
> > > +					  (u8) classinstance.engine_instance);
> > > +
> > > +	if (!engine)
> > > +		return -EINVAL;
> > > +
> > > +	sseu = &engine->gt->info.sseu;
> > > +
> > > +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> > > +}
> > > +
> > >   static int
> > >   query_engine_info(struct drm_i915_private *i915,
> > >   		  struct drm_i915_query_item *query_item)
> > > @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> > >   	query_engine_info,
> > >   	query_perf_config,
> > >   	query_memregion_info,
> > > +	query_geometry_subslices,
> > >   };
> > >   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index 05c3642aaece..b539c83a4034 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
> > >   struct drm_i915_query_item {
> > >   	/** @query_id: The id for this query */
> > >   	__u64 query_id;
> > > -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> > > -#define DRM_I915_QUERY_ENGINE_INFO	2
> > > -#define DRM_I915_QUERY_PERF_CONFIG      3
> > > -#define DRM_I915_QUERY_MEMORY_REGIONS   4
> > > +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
> > > +#define DRM_I915_QUERY_ENGINE_INFO		2
> > > +#define DRM_I915_QUERY_PERF_CONFIG		3
> > > +#define DRM_I915_QUERY_MEMORY_REGIONS		4
> > > +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
> > >   /* Must be kept compact -- no holes and well documented */
> > >   	/**
> > > @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
> > >   	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
> > >   	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> > >   	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> > > +	 *
> > > +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
> > > +	 * i915_engine_class_instance struct.
> > 
> > To get back to our previous discussion off-list, I find this interface
> > kind of confusing, since it's expecting an engine ID as argument, but it
> > returns the set of subslices available to the *render* engine regardless
> > of the engine class specified.  I think it would make sense to rename
> > this to DRM_I915_QUERY_ENGINE_SUBSLICES or similar and have the mask
> > returned be the set of subslices actually available to the engine that
> > was specified (e.g. the compute subslice mask if a compute engine is
> > specified, or an error if the engine specified doesn't have any
> > connection to subslices).  Alternatively, if this is really only meant
> > to work for the render engine, maybe the engine class should be dropped
> > from "flags", only the engine instance is necessary -- I think that
> > would prevent programming errors and would leave additional room in
> > "flags" for future expansion.
> 
> I have asked a similar question and AFAIR Matt explained it was an arch
> level direction to have it like it is. Not sure of the reasoning.
> 
> I wouldn't take the option of implying render and only having instance in
> flags, but returning error for engines not applicable sounds good to me. If
> there isn't a good reason not to do it.

GEOMETRY_SUBSLICES doesn't really have any meaning for non-RCS engines,
so returning an error if the query is performed against a media,
blitter, or compute engine is probably fine.

MattA also has a COMPUTE_SUBSLICES query coming as well, and I believe
the compute subslices query would be relevant to both render and compute
engines since gpgpu workloads can be submitted to either.  So keeping
the engine type (and maintaining a consistent signature for the two
queries) is probably the way to go.


Matt

> 
> Regards,
> 
> Tvrtko

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-28 16:01       ` Matt Roper
  0 siblings, 0 replies; 17+ messages in thread
From: Matt Roper @ 2022-03-28 16:01 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel

On Mon, Mar 28, 2022 at 09:44:36AM +0100, Tvrtko Ursulin wrote:
> 
> + Joonas
> 
> On 25/03/2022 23:03, Francisco Jerez wrote:
> > Matt Atwood <matthew.s.atwood@intel.com> writes:
> > 
> > > Newer platforms have DSS that aren't necessarily available for both
> > > geometry and compute, two queries will need to exist. This introduces
> > > the first, when passing a valid engine class and engine instance in the
> > > flags returns a topology describing geometry.
> > > 
> > > v2: fix white space errors
> > > v3: change flags from hosting 2 8 bit numbers to holding a
> > > i915_engine_class_instance struct
> > > 
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
> > >   include/uapi/drm/i915_drm.h       | 24 +++++++----
> > >   2 files changed, 65 insertions(+), 27 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > > index 2dfbc22857a3..fcb374201edb 100644
> > > --- a/drivers/gpu/drm/i915/i915_query.c
> > > +++ b/drivers/gpu/drm/i915/i915_query.c
> > > @@ -9,6 +9,7 @@
> > >   #include "i915_drv.h"
> > >   #include "i915_perf.h"
> > >   #include "i915_query.h"
> > > +#include "gt/intel_engine_user.h"
> > >   #include <uapi/drm/i915_drm.h>
> > >   static int copy_query_item(void *query_hdr, size_t query_sz,
> > > @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> > >   	return 0;
> > >   }
> > > -static int query_topology_info(struct drm_i915_private *dev_priv,
> > > -			       struct drm_i915_query_item *query_item)
> > > +static int fill_topology_info(const struct sseu_dev_info *sseu,
> > > +			      struct drm_i915_query_item *query_item,
> > > +			      const u8 *subslice_mask)
> > >   {
> > > -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> > >   	struct drm_i915_query_topology_info topo;
> > >   	u32 slice_length, subslice_length, eu_length, total_length;
> > >   	int ret;
> > > -	if (query_item->flags != 0)
> > > -		return -EINVAL;
> > > +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> > >   	if (sseu->max_slices == 0)
> > >   		return -ENODEV;
> > > -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> > > -
> > >   	slice_length = sizeof(sseu->slice_mask);
> > >   	subslice_length = sseu->max_slices * sseu->ss_stride;
> > >   	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
> > >   	total_length = sizeof(topo) + slice_length + subslice_length +
> > >   		       eu_length;
> > > -	ret = copy_query_item(&topo, sizeof(topo), total_length,
> > > -			      query_item);
> > > +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
> > > +
> > >   	if (ret != 0)
> > >   		return ret;
> > > -	if (topo.flags != 0)
> > > -		return -EINVAL;
> > > -
> > >   	memset(&topo, 0, sizeof(topo));
> > >   	topo.max_slices = sseu->max_slices;
> > >   	topo.max_subslices = sseu->max_subslices;
> > > @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
> > >   	topo.eu_stride = sseu->eu_stride;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> > > -			   &topo, sizeof(topo)))
> > > +			 &topo, sizeof(topo)))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
> > > -			   &sseu->slice_mask, slice_length))
> > > +			 &sseu->slice_mask, slice_length))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > > -					   sizeof(topo) + slice_length),
> > > -			   sseu->subslice_mask, subslice_length))
> > > +					 sizeof(topo) + slice_length),
> > > +			 subslice_mask, subslice_length))
> > >   		return -EFAULT;
> > >   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > > -					   sizeof(topo) +
> > > -					   slice_length + subslice_length),
> > > -			   sseu->eu_mask, eu_length))
> > > +					 sizeof(topo) +
> > > +					 slice_length + subslice_length),
> > > +			 sseu->eu_mask, eu_length))
> > >   		return -EFAULT;
> > >   	return total_length;
> > >   }
> > > +static int query_topology_info(struct drm_i915_private *dev_priv,
> > > +			       struct drm_i915_query_item *query_item)
> > > +{
> > > +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> > > +
> > > +	if (query_item->flags != 0)
> > > +		return -EINVAL;
> > > +
> > > +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
> > > +}
> > > +
> > > +static int query_geometry_subslices(struct drm_i915_private *i915,
> > > +				    struct drm_i915_query_item *query_item)
> > > +{
> > > +	const struct sseu_dev_info *sseu;
> > > +	struct intel_engine_cs *engine;
> > > +	struct i915_engine_class_instance classinstance;
> > > +
> > > +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > > +		return -ENODEV;
> > > +
> > > +	classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
> > > +
> > > +	engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class,
> > > +					  (u8) classinstance.engine_instance);
> > > +
> > > +	if (!engine)
> > > +		return -EINVAL;
> > > +
> > > +	sseu = &engine->gt->info.sseu;
> > > +
> > > +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> > > +}
> > > +
> > >   static int
> > >   query_engine_info(struct drm_i915_private *i915,
> > >   		  struct drm_i915_query_item *query_item)
> > > @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> > >   	query_engine_info,
> > >   	query_perf_config,
> > >   	query_memregion_info,
> > > +	query_geometry_subslices,
> > >   };
> > >   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index 05c3642aaece..b539c83a4034 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
> > >   struct drm_i915_query_item {
> > >   	/** @query_id: The id for this query */
> > >   	__u64 query_id;
> > > -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> > > -#define DRM_I915_QUERY_ENGINE_INFO	2
> > > -#define DRM_I915_QUERY_PERF_CONFIG      3
> > > -#define DRM_I915_QUERY_MEMORY_REGIONS   4
> > > +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
> > > +#define DRM_I915_QUERY_ENGINE_INFO		2
> > > +#define DRM_I915_QUERY_PERF_CONFIG		3
> > > +#define DRM_I915_QUERY_MEMORY_REGIONS		4
> > > +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
> > >   /* Must be kept compact -- no holes and well documented */
> > >   	/**
> > > @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
> > >   	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
> > >   	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> > >   	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> > > +	 *
> > > +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
> > > +	 * i915_engine_class_instance struct.
> > 
> > To get back to our previous discussion off-list, I find this interface
> > kind of confusing, since it's expecting an engine ID as argument, but it
> > returns the set of subslices available to the *render* engine regardless
> > of the engine class specified.  I think it would make sense to rename
> > this to DRM_I915_QUERY_ENGINE_SUBSLICES or similar and have the mask
> > returned be the set of subslices actually available to the engine that
> > was specified (e.g. the compute subslice mask if a compute engine is
> > specified, or an error if the engine specified doesn't have any
> > connection to subslices).  Alternatively, if this is really only meant
> > to work for the render engine, maybe the engine class should be dropped
> > from "flags", only the engine instance is necessary -- I think that
> > would prevent programming errors and would leave additional room in
> > "flags" for future expansion.
> 
> I have asked a similar question and AFAIR Matt explained it was an arch
> level direction to have it like it is. Not sure of the reasoning.
> 
> I wouldn't take the option of implying render and only having instance in
> flags, but returning error for engines not applicable sounds good to me. If
> there isn't a good reason not to do it.

GEOMETRY_SUBSLICES doesn't really have any meaning for non-RCS engines,
so returning an error if the query is performed against a media,
blitter, or compute engine is probably fine.

MattA also has a COMPUTE_SUBSLICES query coming as well, and I believe
the compute subslices query would be relevant to both render and compute
engines since gpgpu workloads can be submitted to either.  So keeping
the engine type (and maintaining a consistent signature for the two
queries) is probably the way to go.


Matt

> 
> Regards,
> 
> Tvrtko

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-25 23:03 ` Francisco Jerez
@ 2022-03-28  8:44   ` Tvrtko Ursulin
  2022-03-28 16:01       ` Matt Roper
  0 siblings, 1 reply; 17+ messages in thread
From: Tvrtko Ursulin @ 2022-03-28  8:44 UTC (permalink / raw)
  To: Francisco Jerez, Matt Atwood, intel-gfx, dri-devel, Joonas Lahtinen


+ Joonas

On 25/03/2022 23:03, Francisco Jerez wrote:
> Matt Atwood <matthew.s.atwood@intel.com> writes:
> 
>> Newer platforms have DSS that aren't necessarily available for both
>> geometry and compute, two queries will need to exist. This introduces
>> the first, when passing a valid engine class and engine instance in the
>> flags returns a topology describing geometry.
>>
>> v2: fix white space errors
>> v3: change flags from hosting 2 8 bit numbers to holding a
>> i915_engine_class_instance struct
>>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
>>   include/uapi/drm/i915_drm.h       | 24 +++++++----
>>   2 files changed, 65 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
>> index 2dfbc22857a3..fcb374201edb 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -9,6 +9,7 @@
>>   #include "i915_drv.h"
>>   #include "i915_perf.h"
>>   #include "i915_query.h"
>> +#include "gt/intel_engine_user.h"
>>   #include <uapi/drm/i915_drm.h>
>>   
>>   static int copy_query_item(void *query_hdr, size_t query_sz,
>> @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>>   	return 0;
>>   }
>>   
>> -static int query_topology_info(struct drm_i915_private *dev_priv,
>> -			       struct drm_i915_query_item *query_item)
>> +static int fill_topology_info(const struct sseu_dev_info *sseu,
>> +			      struct drm_i915_query_item *query_item,
>> +			      const u8 *subslice_mask)
>>   {
>> -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>>   	struct drm_i915_query_topology_info topo;
>>   	u32 slice_length, subslice_length, eu_length, total_length;
>>   	int ret;
>>   
>> -	if (query_item->flags != 0)
>> -		return -EINVAL;
>> +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>>   
>>   	if (sseu->max_slices == 0)
>>   		return -ENODEV;
>>   
>> -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>> -
>>   	slice_length = sizeof(sseu->slice_mask);
>>   	subslice_length = sseu->max_slices * sseu->ss_stride;
>>   	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>>   	total_length = sizeof(topo) + slice_length + subslice_length +
>>   		       eu_length;
>>   
>> -	ret = copy_query_item(&topo, sizeof(topo), total_length,
>> -			      query_item);
>> +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
>> +
>>   	if (ret != 0)
>>   		return ret;
>>   
>> -	if (topo.flags != 0)
>> -		return -EINVAL;
>> -
>>   	memset(&topo, 0, sizeof(topo));
>>   	topo.max_slices = sseu->max_slices;
>>   	topo.max_subslices = sseu->max_subslices;
>> @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>>   	topo.eu_stride = sseu->eu_stride;
>>   
>>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>> -			   &topo, sizeof(topo)))
>> +			 &topo, sizeof(topo)))
>>   		return -EFAULT;
>>   
>>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
>> -			   &sseu->slice_mask, slice_length))
>> +			 &sseu->slice_mask, slice_length))
>>   		return -EFAULT;
>>   
>>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> -					   sizeof(topo) + slice_length),
>> -			   sseu->subslice_mask, subslice_length))
>> +					 sizeof(topo) + slice_length),
>> +			 subslice_mask, subslice_length))
>>   		return -EFAULT;
>>   
>>   	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> -					   sizeof(topo) +
>> -					   slice_length + subslice_length),
>> -			   sseu->eu_mask, eu_length))
>> +					 sizeof(topo) +
>> +					 slice_length + subslice_length),
>> +			 sseu->eu_mask, eu_length))
>>   		return -EFAULT;
>>   
>>   	return total_length;
>>   }
>>   
>> +static int query_topology_info(struct drm_i915_private *dev_priv,
>> +			       struct drm_i915_query_item *query_item)
>> +{
>> +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>> +
>> +	if (query_item->flags != 0)
>> +		return -EINVAL;
>> +
>> +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
>> +}
>> +
>> +static int query_geometry_subslices(struct drm_i915_private *i915,
>> +				    struct drm_i915_query_item *query_item)
>> +{
>> +	const struct sseu_dev_info *sseu;
>> +	struct intel_engine_cs *engine;
>> +	struct i915_engine_class_instance classinstance;
>> +
>> +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>> +		return -ENODEV;
>> +
>> +	classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
>> +
>> +	engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class,
>> +					  (u8) classinstance.engine_instance);
>> +
>> +	if (!engine)
>> +		return -EINVAL;
>> +
>> +	sseu = &engine->gt->info.sseu;
>> +
>> +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
>> +}
>> +
>>   static int
>>   query_engine_info(struct drm_i915_private *i915,
>>   		  struct drm_i915_query_item *query_item)
>> @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>>   	query_engine_info,
>>   	query_perf_config,
>>   	query_memregion_info,
>> +	query_geometry_subslices,
>>   };
>>   
>>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 05c3642aaece..b539c83a4034 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
>>   struct drm_i915_query_item {
>>   	/** @query_id: The id for this query */
>>   	__u64 query_id;
>> -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
>> -#define DRM_I915_QUERY_ENGINE_INFO	2
>> -#define DRM_I915_QUERY_PERF_CONFIG      3
>> -#define DRM_I915_QUERY_MEMORY_REGIONS   4
>> +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
>> +#define DRM_I915_QUERY_ENGINE_INFO		2
>> +#define DRM_I915_QUERY_PERF_CONFIG		3
>> +#define DRM_I915_QUERY_MEMORY_REGIONS		4
>> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
>>   /* Must be kept compact -- no holes and well documented */
>>   
>>   	/**
>> @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
>>   	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
>>   	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
>>   	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
>> +	 *
>> +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
>> +	 * i915_engine_class_instance struct.
> 
> To get back to our previous discussion off-list, I find this interface
> kind of confusing, since it's expecting an engine ID as argument, but it
> returns the set of subslices available to the *render* engine regardless
> of the engine class specified.  I think it would make sense to rename
> this to DRM_I915_QUERY_ENGINE_SUBSLICES or similar and have the mask
> returned be the set of subslices actually available to the engine that
> was specified (e.g. the compute subslice mask if a compute engine is
> specified, or an error if the engine specified doesn't have any
> connection to subslices).  Alternatively, if this is really only meant
> to work for the render engine, maybe the engine class should be dropped
> from "flags", only the engine instance is necessary -- I think that
> would prevent programming errors and would leave additional room in
> "flags" for future expansion.

I have asked a similar question and AFAIR Matt explained it was an arch 
level direction to have it like it is. Not sure of the reasoning.

I wouldn't take the option of implying render and only having instance 
in flags, but returning error for engines not applicable sounds good to 
me. If there isn't a good reason not to do it.

Regards,

Tvrtko

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
  2022-03-16 22:49 Matt Atwood
@ 2022-03-25 23:03 ` Francisco Jerez
  2022-03-28  8:44   ` Tvrtko Ursulin
  0 siblings, 1 reply; 17+ messages in thread
From: Francisco Jerez @ 2022-03-25 23:03 UTC (permalink / raw)
  To: Matt Atwood, intel-gfx, dri-devel

Matt Atwood <matthew.s.atwood@intel.com> writes:

> Newer platforms have DSS that aren't necessarily available for both
> geometry and compute, two queries will need to exist. This introduces
> the first, when passing a valid engine class and engine instance in the
> flags returns a topology describing geometry.
>
> v2: fix white space errors
> v3: change flags from hosting 2 8 bit numbers to holding a
> i915_engine_class_instance struct
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
>  include/uapi/drm/i915_drm.h       | 24 +++++++----
>  2 files changed, 65 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 2dfbc22857a3..fcb374201edb 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -9,6 +9,7 @@
>  #include "i915_drv.h"
>  #include "i915_perf.h"
>  #include "i915_query.h"
> +#include "gt/intel_engine_user.h"
>  #include <uapi/drm/i915_drm.h>
>  
>  static int copy_query_item(void *query_hdr, size_t query_sz,
> @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>  	return 0;
>  }
>  
> -static int query_topology_info(struct drm_i915_private *dev_priv,
> -			       struct drm_i915_query_item *query_item)
> +static int fill_topology_info(const struct sseu_dev_info *sseu,
> +			      struct drm_i915_query_item *query_item,
> +			      const u8 *subslice_mask)
>  {
> -	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>  	struct drm_i915_query_topology_info topo;
>  	u32 slice_length, subslice_length, eu_length, total_length;
>  	int ret;
>  
> -	if (query_item->flags != 0)
> -		return -EINVAL;
> +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>  
>  	if (sseu->max_slices == 0)
>  		return -ENODEV;
>  
> -	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> -
>  	slice_length = sizeof(sseu->slice_mask);
>  	subslice_length = sseu->max_slices * sseu->ss_stride;
>  	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>  	total_length = sizeof(topo) + slice_length + subslice_length +
>  		       eu_length;
>  
> -	ret = copy_query_item(&topo, sizeof(topo), total_length,
> -			      query_item);
> +	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
> +
>  	if (ret != 0)
>  		return ret;
>  
> -	if (topo.flags != 0)
> -		return -EINVAL;
> -
>  	memset(&topo, 0, sizeof(topo));
>  	topo.max_slices = sseu->max_slices;
>  	topo.max_subslices = sseu->max_subslices;
> @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>  	topo.eu_stride = sseu->eu_stride;
>  
>  	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> -			   &topo, sizeof(topo)))
> +			 &topo, sizeof(topo)))
>  		return -EFAULT;
>  
>  	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
> -			   &sseu->slice_mask, slice_length))
> +			 &sseu->slice_mask, slice_length))
>  		return -EFAULT;
>  
>  	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> -					   sizeof(topo) + slice_length),
> -			   sseu->subslice_mask, subslice_length))
> +					 sizeof(topo) + slice_length),
> +			 subslice_mask, subslice_length))
>  		return -EFAULT;
>  
>  	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> -					   sizeof(topo) +
> -					   slice_length + subslice_length),
> -			   sseu->eu_mask, eu_length))
> +					 sizeof(topo) +
> +					 slice_length + subslice_length),
> +			 sseu->eu_mask, eu_length))
>  		return -EFAULT;
>  
>  	return total_length;
>  }
>  
> +static int query_topology_info(struct drm_i915_private *dev_priv,
> +			       struct drm_i915_query_item *query_item)
> +{
> +	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
> +
> +	if (query_item->flags != 0)
> +		return -EINVAL;
> +
> +	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
> +}
> +
> +static int query_geometry_subslices(struct drm_i915_private *i915,
> +				    struct drm_i915_query_item *query_item)
> +{
> +	const struct sseu_dev_info *sseu;
> +	struct intel_engine_cs *engine;
> +	struct i915_engine_class_instance classinstance;
> +
> +	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> +		return -ENODEV;
> +
> +	classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
> +
> +	engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class,
> +					  (u8) classinstance.engine_instance);
> +
> +	if (!engine)
> +		return -EINVAL;
> +
> +	sseu = &engine->gt->info.sseu;
> +
> +	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> +}
> +
>  static int
>  query_engine_info(struct drm_i915_private *i915,
>  		  struct drm_i915_query_item *query_item)
> @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>  	query_engine_info,
>  	query_perf_config,
>  	query_memregion_info,
> +	query_geometry_subslices,
>  };
>  
>  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 05c3642aaece..b539c83a4034 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
>  struct drm_i915_query_item {
>  	/** @query_id: The id for this query */
>  	__u64 query_id;
> -#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> -#define DRM_I915_QUERY_ENGINE_INFO	2
> -#define DRM_I915_QUERY_PERF_CONFIG      3
> -#define DRM_I915_QUERY_MEMORY_REGIONS   4
> +#define DRM_I915_QUERY_TOPOLOGY_INFO		1
> +#define DRM_I915_QUERY_ENGINE_INFO		2
> +#define DRM_I915_QUERY_PERF_CONFIG		3
> +#define DRM_I915_QUERY_MEMORY_REGIONS		4
> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
>  /* Must be kept compact -- no holes and well documented */
>  
>  	/**
> @@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
>  	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
>  	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
>  	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> +	 *
> +	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
> +	 * i915_engine_class_instance struct.

To get back to our previous discussion off-list, I find this interface
kind of confusing, since it's expecting an engine ID as argument, but it
returns the set of subslices available to the *render* engine regardless
of the engine class specified.  I think it would make sense to rename
this to DRM_I915_QUERY_ENGINE_SUBSLICES or similar and have the mask
returned be the set of subslices actually available to the engine that
was specified (e.g. the compute subslice mask if a compute engine is
specified, or an error if the engine specified doesn't have any
connection to subslices).  Alternatively, if this is really only meant
to work for the render engine, maybe the engine class should be dropped
from "flags", only the engine instance is necessary -- I think that
would prevent programming errors and would leave additional room in
"flags" for future expansion.

>  	 */
>  	__u32 flags;
>  #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
> @@ -2772,16 +2776,20 @@ struct drm_i915_query {
>  };
>  
>  /*
> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
> + * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
>   *
>   * data: contains the 3 pieces of information :
>   *
> - * - the slice mask with one bit per slice telling whether a slice is
> - *   available. The availability of slice X can be queried with the following
> - *   formula :
> + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
> + *   telling whether a slice is available. The availability of slice X can be
> + *   queried with the following formula :
>   *
>   *           (data[X / 8] >> (X % 8)) & 1
>   *
> + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
> + *   is not used.
> + *
>   * - the subslice mask for each slice with one bit per subslice telling
>   *   whether a subslice is available. Gen12 has dual-subslices, which are
>   *   similar to two gen11 subslices. For gen12, this array represents dual-
> -- 
> 2.21.3

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-16 22:49 Matt Atwood
  2022-03-25 23:03 ` Francisco Jerez
  0 siblings, 1 reply; 17+ messages in thread
From: Matt Atwood @ 2022-03-16 22:49 UTC (permalink / raw)
  To: intel-gfx, dri-devel

Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.

v2: fix white space errors
v3: change flags from hosting 2 8 bit numbers to holding a
i915_engine_class_instance struct

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
 include/uapi/drm/i915_drm.h       | 24 +++++++----
 2 files changed, 65 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 2dfbc22857a3..fcb374201edb 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_perf.h"
 #include "i915_query.h"
+#include "gt/intel_engine_user.h"
 #include <uapi/drm/i915_drm.h>
 
 static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
 	return 0;
 }
 
-static int query_topology_info(struct drm_i915_private *dev_priv,
-			       struct drm_i915_query_item *query_item)
+static int fill_topology_info(const struct sseu_dev_info *sseu,
+			      struct drm_i915_query_item *query_item,
+			      const u8 *subslice_mask)
 {
-	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
 	int ret;
 
-	if (query_item->flags != 0)
-		return -EINVAL;
+	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	if (sseu->max_slices == 0)
 		return -ENODEV;
 
-	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
-
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
 	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
-	ret = copy_query_item(&topo, sizeof(topo), total_length,
-			      query_item);
+	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
+
 	if (ret != 0)
 		return ret;
 
-	if (topo.flags != 0)
-		return -EINVAL;
-
 	memset(&topo, 0, sizeof(topo));
 	topo.max_slices = sseu->max_slices;
 	topo.max_subslices = sseu->max_subslices;
@@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.eu_stride = sseu->eu_stride;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
-			   &topo, sizeof(topo)))
+			 &topo, sizeof(topo)))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
-			   &sseu->slice_mask, slice_length))
+			 &sseu->slice_mask, slice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) + slice_length),
-			   sseu->subslice_mask, subslice_length))
+					 sizeof(topo) + slice_length),
+			 subslice_mask, subslice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) +
-					   slice_length + subslice_length),
-			   sseu->eu_mask, eu_length))
+					 sizeof(topo) +
+					 slice_length + subslice_length),
+			 sseu->eu_mask, eu_length))
 		return -EFAULT;
 
 	return total_length;
 }
 
+static int query_topology_info(struct drm_i915_private *dev_priv,
+			       struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
+
+	if (query_item->flags != 0)
+		return -EINVAL;
+
+	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
+}
+
+static int query_geometry_subslices(struct drm_i915_private *i915,
+				    struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu;
+	struct intel_engine_cs *engine;
+	struct i915_engine_class_instance classinstance;
+
+	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+		return -ENODEV;
+
+	classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
+
+	engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class,
+					  (u8) classinstance.engine_instance);
+
+	if (!engine)
+		return -EINVAL;
+
+	sseu = &engine->gt->info.sseu;
+
+	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
+}
+
 static int
 query_engine_info(struct drm_i915_private *i915,
 		  struct drm_i915_query_item *query_item)
@@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 	query_engine_info,
 	query_perf_config,
 	query_memregion_info,
+	query_geometry_subslices,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 05c3642aaece..b539c83a4034 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	/** @query_id: The id for this query */
 	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-#define DRM_I915_QUERY_ENGINE_INFO	2
-#define DRM_I915_QUERY_PERF_CONFIG      3
-#define DRM_I915_QUERY_MEMORY_REGIONS   4
+#define DRM_I915_QUERY_TOPOLOGY_INFO		1
+#define DRM_I915_QUERY_ENGINE_INFO		2
+#define DRM_I915_QUERY_PERF_CONFIG		3
+#define DRM_I915_QUERY_MEMORY_REGIONS		4
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
 /* Must be kept compact -- no holes and well documented */
 
 	/**
@@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
 	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
 	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
 	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *
+	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid
+	 * i915_engine_class_instance struct.
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
@@ -2772,16 +2776,20 @@ struct drm_i915_query {
 };
 
 /*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
+ * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
  *
  * data: contains the 3 pieces of information :
  *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
+ * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
+ *   telling whether a slice is available. The availability of slice X can be
+ *   queried with the following formula :
  *
  *           (data[X / 8] >> (X % 8)) & 1
  *
+ * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
+ *   is not used.
+ *
  * - the subslice mask for each slice with one bit per subslice telling
  *   whether a subslice is available. Gen12 has dual-subslices, which are
  *   similar to two gen11 subslices. For gen12, this array represents dual-
-- 
2.21.3


^ permalink raw reply related	[flat|nested] 17+ messages in thread

* [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
@ 2022-03-10  0:34 Matt Atwood
  0 siblings, 0 replies; 17+ messages in thread
From: Matt Atwood @ 2022-03-10  0:34 UTC (permalink / raw)
  To: intel-gfx, dri-devel

Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++---------
 include/uapi/drm/i915_drm.h       | 24 +++++++----
 2 files changed, 65 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 2dfbc22857a3..0cc2670ae09c 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_perf.h"
 #include "i915_query.h"
+#include "gt/intel_engine_user.h"
 #include <uapi/drm/i915_drm.h>
 
 static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
 	return 0;
 }
 
-static int query_topology_info(struct drm_i915_private *dev_priv,
-			       struct drm_i915_query_item *query_item)
+static int fill_topology_info(const struct sseu_dev_info *sseu,
+			      struct drm_i915_query_item *query_item,
+			      const u8 *subslice_mask)
 {
-	const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
 	int ret;
 
-	if (query_item->flags != 0)
-		return -EINVAL;
+	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	if (sseu->max_slices == 0)
 		return -ENODEV;
 
-	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
-
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
 	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
-	ret = copy_query_item(&topo, sizeof(topo), total_length,
-			      query_item);
+	ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
+
 	if (ret != 0)
 		return ret;
 
-	if (topo.flags != 0)
-		return -EINVAL;
-
 	memset(&topo, 0, sizeof(topo));
 	topo.max_slices = sseu->max_slices;
 	topo.max_subslices = sseu->max_subslices;
@@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.eu_stride = sseu->eu_stride;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
-			   &topo, sizeof(topo)))
+			 &topo, sizeof(topo)))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
-			   &sseu->slice_mask, slice_length))
+			 &sseu->slice_mask, slice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) + slice_length),
-			   sseu->subslice_mask, subslice_length))
+					 sizeof(topo) + slice_length),
+			 subslice_mask, subslice_length))
 		return -EFAULT;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					   sizeof(topo) +
-					   slice_length + subslice_length),
-			   sseu->eu_mask, eu_length))
+					 sizeof(topo) +
+					 slice_length + subslice_length),
+			 sseu->eu_mask, eu_length))
 		return -EFAULT;
 
 	return total_length;
 }
 
+static int query_topology_info(struct drm_i915_private *dev_priv,
+			       struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu = &to_gt(dev_priv )->info.sseu;
+
+	if (query_item->flags != 0)
+		return -EINVAL;
+
+	return fill_topology_info(sseu, query_item, sseu->subslice_mask);
+}
+
+static int query_geometry_subslices(struct drm_i915_private *i915,
+				    struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu;
+	struct intel_engine_cs *engine;
+	u8 engine_class, engine_instance;
+
+	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+		return -ENODEV;
+
+	engine_class = query_item->flags & 0xFF;
+	engine_instance = (query_item->flags >>8) & 0xFF;
+
+	engine = intel_engine_lookup_user(i915, engine_class, engine_instance);
+
+	if(!engine)
+		return -EINVAL;
+
+	sseu = &engine->gt->info.sseu;
+
+	return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
+}
+
 static int
 query_engine_info(struct drm_i915_private *i915,
 		  struct drm_i915_query_item *query_item)
@@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 	query_engine_info,
 	query_perf_config,
 	query_memregion_info,
+	query_geometry_subslices,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 05c3642aaece..ac75d8b85803 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	/** @query_id: The id for this query */
 	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-#define DRM_I915_QUERY_ENGINE_INFO	2
-#define DRM_I915_QUERY_PERF_CONFIG      3
-#define DRM_I915_QUERY_MEMORY_REGIONS   4
+#define DRM_I915_QUERY_TOPOLOGY_INFO    	1
+#define DRM_I915_QUERY_ENGINE_INFO		2
+#define DRM_I915_QUERY_PERF_CONFIG      	3
+#define DRM_I915_QUERY_MEMORY_REGIONS   	4
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	5
 /* Must be kept compact -- no holes and well documented */
 
 	/**
@@ -2714,6 +2715,9 @@ struct drm_i915_query_item {
 	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
 	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
 	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *
+	 * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have bits 0:7 set
+	 * as a valid engine class, and bits 8:15 must have a valid engine instance.
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
@@ -2772,16 +2776,20 @@ struct drm_i915_query {
 };
 
 /*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO,
+ * DRM_I915_QUERY_GEOMETRY_SUBSLICE:
  *
  * data: contains the 3 pieces of information :
  *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
+ * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice
+ *   telling whether a slice is available. The availability of slice X can be
+ *   queried with the following formula :
  *
  *           (data[X / 8] >> (X % 8)) & 1
  *
+ * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field
+ *   is not used.
+ *
  * - the subslice mask for each slice with one bit per subslice telling
  *   whether a subslice is available. Gen12 has dual-subslices, which are
  *   similar to two gen11 subslices. For gen12, this array represents dual-
-- 
2.21.3


^ permalink raw reply related	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2022-03-28 16:01 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-10  5:18 [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES Matt Atwood
2022-03-10  5:18 ` [Intel-gfx] " Matt Atwood
2022-03-10  5:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2) Patchwork
2022-03-10  6:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 11:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-10 12:26 ` [Intel-gfx] [PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES Tvrtko Ursulin
2022-03-12  4:16   ` Matt Atwood
2022-03-14 15:35     ` Tvrtko Ursulin
2022-03-14 17:50       ` Dixit, Ashutosh
2022-03-14 17:50         ` Dixit, Ashutosh
2022-03-16 11:30       ` Joonas Lahtinen
  -- strict thread matches above, loose matches on Subject: below --
2022-03-16 22:49 Matt Atwood
2022-03-25 23:03 ` Francisco Jerez
2022-03-28  8:44   ` Tvrtko Ursulin
2022-03-28 16:01     ` Matt Roper
2022-03-28 16:01       ` Matt Roper
2022-03-10  0:34 Matt Atwood

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