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Sun, 13 Dec 2020 19:25:11 +0100 (CET) Received: from [213.133.102.83] (ml.mymailcheap.com [213.133.102.83]) by mail20.mymailcheap.com (Postfix) with ESMTP id 0F6DA41A53; Sun, 13 Dec 2020 18:25:11 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=aosc.io header.i=@aosc.io header.b="MG8O1fCx"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from ice-e5v2.lan (unknown [59.41.162.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits)) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 9A10641A53; Sun, 13 Dec 2020 18:25:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1607883906; bh=+LGuRIW3w+rBMNLbodKIkSob5p2vS5X84LMEHhm63h4=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=MG8O1fCxMafOPgABaOZ210gqOOl3BAEDZGIbKRqO1gGi3r3HSBRcUoI/N8j/Ijfwx CtnituWlrJH+UQsS8nSfhxDBbxQdn0D2l0/IQLeQb0CqoLzDMn4jQ1U2tYF5YuV+SN EE6DrP/WhaxGhcbrquKgW9CHNjNiHLVM/FwuNCC8= Message-ID: <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io> Subject: Re: [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling From: Icenowy Zheng To: Andre Przywara , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Icenowy Zheng , Linus Walleij , Rob Herring , =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= , Shuosheng Huang , Yangtao Li , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Kishon Vijay Abraham I , Vinod Koul Date: Mon, 14 Dec 2020 02:24:58 +0800 In-Reply-To: <20201211011934.6171-15-andre.przywara@arm.com> References: <20201211011934.6171-1-andre.przywara@arm.com> <20201211011934.6171-15-andre.przywara@arm.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [1.40 / 20.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; MID_RHS_MATCH_FROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; TAGGED_RCPT(0.00)[]; MIME_GOOD(-0.10)[text/plain]; DMARC_NA(0.00)[aosc.io]; R_SPF_SOFTFAIL(0.00)[~all]; HFILTER_HELO_BAREIP(3.00)[213.133.102.83,1]; TO_MATCH_ENVRCPT_SOME(0.00)[]; ML_SERVERS(-3.10)[213.133.102.83]; DKIM_TRACE(0.00)[aosc.io:+]; RCPT_COUNT_TWELVE(0.00)[15]; RECEIVED_SPAMHAUS_PBL(0.00)[59.41.162.102:received]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:213.133.96.0/19, country:DE]; FREEMAIL_CC(0.00)[aosc.xyz,linaro.org,kernel.org,gmail.com,allwinnertech.com,lists.infradead.org,vger.kernel.org,googlegroups.com,ti.com]; SUSPICIOUS_RECIPS(1.50)[]; RCVD_COUNT_TWO(0.00)[2] X-Rspamd-Queue-Id: 0F6DA41A53 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2020-12-11星期五的 01:19 +0000，Andre Przywara写道： > Newer SoCs (A100, H616) need to clear a different bit in our > "unknown" > PMU PHY register. It looks like that the unknown PHY register is PHYCTL register for each individual PHY, and the bit that is cleared is called SUNXI_HCI_PHY_CTRL_SIDDQ in the BSP (similar to the USBC_PHY_CTL_SIDDQ we cleared for main PHYCTL). > > Generalise the existing code by allowing configs to specify a bitmask > of bits to clear. > > Signed-off-by: Andre Przywara > --- > drivers/phy/allwinner/phy-sun4i-usb.c | 28 +++++++++++------------ > ---- > 1 file changed, 11 insertions(+), 17 deletions(-) > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c > b/drivers/phy/allwinner/phy-sun4i-usb.c > index 651d5e2a25ce..4ba0699e0bb4 100644 > --- a/drivers/phy/allwinner/phy-sun4i-usb.c > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c > @@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg { > int hsic_index; > enum sun4i_usb_phy_type type; > u32 disc_thresh; > + u32 pmu_unk1_clrbits; > u8 phyctl_offset; > bool dedicated_clocks; > - bool enable_pmu_unk1; > bool phy0_dual_route; > int missing_phys; > }; > @@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) > return ret; > } > > + if (phy->pmu && data->cfg->pmu_unk1_clrbits) { > + val = readl(phy->pmu + REG_PMU_UNK1); > + val &= ~data->cfg->pmu_unk1_clrbits; > + writel(val, phy->pmu + REG_PMU_UNK1); > + } > + > if (data->cfg->type == sun8i_a83t_phy || > data->cfg->type == sun50i_h6_phy) { > if (phy->index == 0) { > @@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) > writel(val, data->base + data->cfg- > >phyctl_offset); > } > } else { > - if (phy->pmu && data->cfg->enable_pmu_unk1) { > - val = readl(phy->pmu + REG_PMU_UNK1); > - writel(val & ~2, phy->pmu + REG_PMU_UNK1); > - } > - > /* Enable USB 45 Ohm resistor calibration */ > if (phy->index == 0) > sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, > 0x01, 1); > @@ -867,7 +868,6 @@ static const struct sun4i_usb_phy_cfg > sun4i_a10_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A10, > .dedicated_clocks = false, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { > @@ -876,7 +876,6 @@ static const struct sun4i_usb_phy_cfg > sun5i_a13_cfg = { > .disc_thresh = 2, > .phyctl_offset = REG_PHYCTL_A10, > .dedicated_clocks = false, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { > @@ -885,7 +884,6 @@ static const struct sun4i_usb_phy_cfg > sun6i_a31_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A10, > .dedicated_clocks = true, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { > @@ -894,7 +892,6 @@ static const struct sun4i_usb_phy_cfg > sun7i_a20_cfg = { > .disc_thresh = 2, > .phyctl_offset = REG_PHYCTL_A10, > .dedicated_clocks = false, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { > @@ -903,7 +900,6 @@ static const struct sun4i_usb_phy_cfg > sun8i_a23_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A10, > .dedicated_clocks = true, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { > @@ -912,7 +908,6 @@ static const struct sun4i_usb_phy_cfg > sun8i_a33_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = false, > }; > > static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { > @@ -929,7 +924,7 @@ static const struct sun4i_usb_phy_cfg > sun8i_h3_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > + .pmu_unk1_clrbits = BIT(1), > .phy0_dual_route = true, > }; > > @@ -939,7 +934,7 @@ static const struct sun4i_usb_phy_cfg > sun8i_r40_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > + .pmu_unk1_clrbits = BIT(1), > .phy0_dual_route = true, > }; > > @@ -949,7 +944,7 @@ static const struct sun4i_usb_phy_cfg > sun8i_v3s_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > + .pmu_unk1_clrbits = BIT(1), > .phy0_dual_route = true, > }; > > @@ -959,7 +954,7 @@ static const struct sun4i_usb_phy_cfg > sun50i_a64_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > + .pmu_unk1_clrbits = BIT(1), > .phy0_dual_route = true, > }; > > @@ -969,7 +964,6 @@ static const struct sun4i_usb_phy_cfg > sun50i_h6_cfg = { > .disc_thresh = 3, > .phyctl_offset = REG_PHYCTL_A33, > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > .phy0_dual_route = true, > .missing_phys = BIT(1) | BIT(2), > }; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, 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(UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1607883906; bh=+LGuRIW3w+rBMNLbodKIkSob5p2vS5X84LMEHhm63h4=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=MG8O1fCxMafOPgABaOZ210gqOOl3BAEDZGIbKRqO1gGi3r3HSBRcUoI/N8j/Ijfwx CtnituWlrJH+UQsS8nSfhxDBbxQdn0D2l0/IQLeQb0CqoLzDMn4jQ1U2tYF5YuV+SN EE6DrP/WhaxGhcbrquKgW9CHNjNiHLVM/FwuNCC8= Message-ID: <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io> Subject: Re: [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling From: Icenowy Zheng To: Andre Przywara , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Date: Mon, 14 Dec 2020 02:24:58 +0800 In-Reply-To: <20201211011934.6171-15-andre.przywara@arm.com> References: <20201211011934.6171-1-andre.przywara@arm.com> <20201211011934.6171-15-andre.przywara@arm.com> User-Agent: Evolution 3.36.5 MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [1.40 / 20.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; 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linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Vinod Koul , Yangtao Li , Linus Walleij , linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , linux-sunxi@googlegroups.com, =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= , Icenowy Zheng , Shuosheng Huang , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 5ZyoIDIwMjAtMTItMTHmmJ/mnJ/kupTnmoQgMDE6MTkgKzAwMDDvvIxBbmRyZSBQcnp5d2FyYeWG memBk++8mgo+IE5ld2VyIFNvQ3MgKEExMDAsIEg2MTYpIG5lZWQgdG8gY2xlYXIgYSBkaWZmZXJl bnQgYml0IGluIG91cgo+ICJ1bmtub3duIgo+IFBNVSBQSFkgcmVnaXN0ZXIuCgpJdCBsb29rcyBs aWtlIHRoYXQgdGhlIHVua25vd24gUEhZIHJlZ2lzdGVyIGlzIFBIWUNUTCByZWdpc3RlciBmb3Ig ZWFjaAppbmRpdmlkdWFsIFBIWSwgYW5kIHRoZSBiaXQgdGhhdCBpcyBjbGVhcmVkIGlzCmNhbGxl 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