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Tue, 4 May 2021 23:46:25 -0700 Envelope-to: robh@kernel.org, alvaro.gamez@hazent.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, sean.anderson@seco.com Received: from [172.30.17.109] (port=47298) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1leBIf-0000mM-1m; Tue, 04 May 2021 23:46:25 -0700 To: Sean Anderson , , CC: , , , Alvaro Gamez , Rob Herring References: <20210504184925.3399934-1-sean.anderson@seco.com> From: Michal Simek Subject: Re: [PATCH v2 1/2] dt-bindings: pwm: Add Xilinx AXI Timer Message-ID: <0326a217-e6cd-d2b3-65a2-4285e9342418@xilinx.com> Date: Wed, 5 May 2021 08:46:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <20210504184925.3399934-1-sean.anderson@seco.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 873e3989-4f1a-40bd-dddc-08d90f9180f5 X-MS-TrafficTypeDiagnostic: SA0PR02MB7242: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 06:46:25.7097 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 873e3989-4f1a-40bd-dddc-08d90f9180f5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT016.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7242 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/4/21 8:49 PM, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of properties > must be kept as they are. > > Signed-off-by: Sean Anderson > --- > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..bd014134c322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson > + > +properties: > + compatible: > + items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + description: > + The width of the counters, in bits. > + > + xlnx,gen0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,gen1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > + xlnx,trig0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,trig1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > + Based on xilinx design tool selection there is also mode_64bit option which I expect will be translate to xlnx,mode-64bit [0, 1]. But any coverage of this as bool property should be fine. > +required: > + - compatible > + - clocks > + - reg > + - xlnx,count-width > + - xlnx,gen0-assert > + - xlnx,gen1-assert these 3 shouldn't be required. > + - xlnx,one-timer-only > + - xlnx,trig0-assert > + - xlnx,trig1-assert these 2 are also not required. > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { > + clock-frequency = <99999001>; I can't see this listed above. It is allowed to have additional properties but I don't think it is good to list it here. > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,gen0-assert = <0x1>; > + xlnx,gen1-assert = <0x1>; > + xlnx,one-timer-only = <0x0>; > + xlnx,trig0-assert = <0x1>; > + xlnx,trig1-assert = <0x1>; > + }; > Thanks, Michal From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0068C433ED for ; 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Tue, 04 May 2021 23:46:25 -0700 To: Sean Anderson , , CC: , , , Alvaro Gamez , Rob Herring References: <20210504184925.3399934-1-sean.anderson@seco.com> From: Michal Simek Subject: Re: [PATCH v2 1/2] dt-bindings: pwm: Add Xilinx AXI Timer Message-ID: <0326a217-e6cd-d2b3-65a2-4285e9342418@xilinx.com> Date: Wed, 5 May 2021 08:46:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <20210504184925.3399934-1-sean.anderson@seco.com> Content-Language: en-US X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 873e3989-4f1a-40bd-dddc-08d90f9180f5 X-MS-TrafficTypeDiagnostic: SA0PR02MB7242: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VfI0lWYUimHtKiVczDCefmScbzPYLY8mnRJhqOI9WT4wy7Tmf1f2KYAwbJauqck5bs1gsUFCWf2hLwJRiV/FEuEqdERyG+PwLLOKoWxXUMM2DuFN+gcmEp8Q9n03t2FrnEpS9YPbMDa8+WrgAAjUEks0QQqlC7dTlu+taaljdTmU9gcGPncy5wDj4RqxckIJIemtfCf2R2opRchF5avlry+Sm9kTZwBTPLgW659ISHq3DlVVmjbHsrx1kd9gDj+3DDYLsE1A41gLklfQtKTAopr3sujqq2veX5NF7RDt/qPYH4o7fNfuOY/L2EfX8xYRDITyFtPm2gEk0WJCUO+rrCxK+W33jmFrCkLb26bcz7o1daUBAbZDS1aEq6ujYQIdupmyktSbkqxJg1nxowCNBlZ5u2R3MXgTllcJUEYpEwKVJZ5uvyV6sBbgNMuQGupQp4Oe2wGCyzI/UXpQ+tK9dK/KzcWQjm8uIvkBGFwHTm6v8pE3cy1eiyvnJ2CkzO6oLa6crzckgCgBcNaB2IpZRsAMsEG6DanYHHH6e4KCNmnjFdJUrn+DW3KGEGzBiawGwgssIXa5AlWF2/NhT2MhkVm4LKuROKVGwe5KzTRsObTX2QD+bT4UT50xru3BxO0u5NEVWXwYxV0IbM7IGhJwfksJl+eX2WmqL3mGLhJ7DDcEZiiKSv8a2OHDt4uzTikdJt4zlHclJec0i4PTYuh1HYZTVcOdeabpLQw7k37vKbT7BvDb6LywwPi07HRvIYdtT+aTRqrCLs7lhnDl0jEnplr8WAbb3I+G9cpuNejtKHc= X-Forefront-Antispam-Report: CIP:149.199.62.198; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/4/21 8:49 PM, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of properties > must be kept as they are. > > Signed-off-by: Sean Anderson > --- > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..bd014134c322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson > + > +properties: > + compatible: > + items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + description: > + The width of the counters, in bits. > + > + xlnx,gen0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,gen1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > + xlnx,trig0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,trig1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > + Based on xilinx design tool selection there is also mode_64bit option which I expect will be translate to xlnx,mode-64bit [0, 1]. But any coverage of this as bool property should be fine. > +required: > + - compatible > + - clocks > + - reg > + - xlnx,count-width > + - xlnx,gen0-assert > + - xlnx,gen1-assert these 3 shouldn't be required. > + - xlnx,one-timer-only > + - xlnx,trig0-assert > + - xlnx,trig1-assert these 2 are also not required. > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { > + clock-frequency = <99999001>; I can't see this listed above. It is allowed to have additional properties but I don't think it is good to list it here. > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,gen0-assert = <0x1>; > + xlnx,gen1-assert = <0x1>; > + xlnx,one-timer-only = <0x0>; > + xlnx,trig0-assert = <0x1>; > + xlnx,trig1-assert = <0x1>; > + }; > Thanks, Michal _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel