All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Geis <pgwipeout@gmail.com>
To: Aapo Vienamo <avienamo@nvidia.com>,
	Thierry Reding <thierry.reding@gmail.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Mikko Perttunen <mperttunen@nvidia.com>,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value
Date: Thu, 9 Aug 2018 08:23:16 -0400	[thread overview]
Message-ID: <03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com> (raw)
In-Reply-To: <20180809150226.64657f56@dhcp-10-21-25-168>



On 08/09/2018 08:02 AM, Aapo Vienamo wrote:
> On Thu, 9 Aug 2018 13:49:22 +0200
> Thierry Reding <thierry.reding@gmail.com> wrote:
> 
>> On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote:
>>> Add the HS400 DQS trim value for Tegra186 SDMMC4.
>>>
>>> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
>>> ---
>>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 6e9ef26..9e07bc6 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -313,6 +313,7 @@
>>>   		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
>>>   		nvidia,default-tap = <0x5>;
>>>   		nvidia,default-trim = <0x9>;
>>> +		nvidia,dqs-trim = <63>;
>>>   		status = "disabled";
>>>   	};
>>>     
>>
>> Isn't this technically dependent on the board layout and as such would
>> belong in the board DTS file? Or does this value work on all existing
>> Tegra186 platforms?
> 
> This value is specified as part of the controller initialization
> sequence in the TRM. I've understood that this (and other tap and trim)
> value(s) are used for compensating the propagation delay differences
> that are caused by the internal SoC layout.
> 
>   -Aapo
> --

The Tegra2 and Tegra3 TRMs also specify recommended DQS values, and I am 
working on at least one device that differs in the platform data from 
the default value.
I see that you mentioned this is for the newer devices that support 
HS200/HS400 modes, but does it enable setting DQS on older devices?

  reply	other threads:[~2018-08-09 12:23 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-07 13:59 [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Aapo Vienamo
2018-08-07 13:59 ` Aapo Vienamo
2018-08-07 13:59 ` [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Aapo Vienamo
2018-08-07 13:59   ` Aapo Vienamo
2018-08-09 11:36   ` Thierry Reding
2018-08-09 11:45     ` Aapo Vienamo
2018-08-09 11:45       ` Aapo Vienamo
2018-08-09 13:46       ` Thierry Reding
2018-08-09 14:06         ` Aapo Vienamo
2018-08-09 14:06           ` Aapo Vienamo
2018-08-09 14:09           ` Thierry Reding
2018-08-07 13:59 ` [PATCH 2/8] mmc: tegra: Parse and program DQS trim value Aapo Vienamo
2018-08-07 13:59   ` Aapo Vienamo
2018-08-09 11:40   ` Thierry Reding
2018-08-09 11:42   ` Thierry Reding
2018-08-07 13:59 ` [PATCH 3/8] mmc: tegra: Implement HS400 enhanced strobe Aapo Vienamo
2018-08-07 13:59   ` Aapo Vienamo
2018-08-09 11:43   ` Thierry Reding
2018-08-09 12:22     ` Aapo Vienamo
2018-08-09 12:22       ` Aapo Vienamo
2018-08-09 13:47       ` Thierry Reding
2018-08-07 14:00 ` [PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration Aapo Vienamo
2018-08-07 14:00   ` Aapo Vienamo
2018-08-09 11:48   ` Thierry Reding
2018-08-09 12:29     ` Aapo Vienamo
2018-08-09 12:29       ` Aapo Vienamo
2018-08-07 14:00 ` [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Aapo Vienamo
2018-08-07 14:00   ` Aapo Vienamo
2018-08-09 11:49   ` Thierry Reding
2018-08-09 12:02     ` Aapo Vienamo
2018-08-09 12:02       ` Aapo Vienamo
2018-08-09 12:23       ` Peter Geis [this message]
2018-08-09 12:37         ` Aapo Vienamo
2018-08-09 12:37           ` Aapo Vienamo
2018-08-09 12:50           ` Peter Geis
2018-08-09 13:52       ` Thierry Reding
2018-08-07 14:00 ` [PATCH 6/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-07 14:00   ` Aapo Vienamo
2018-08-07 14:00 ` [PATCH 7/8] arm64: dts: tegra186: Enable HS400 Aapo Vienamo
2018-08-07 14:00   ` Aapo Vienamo
2018-08-07 14:00 ` [PATCH 8/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-07 14:00   ` Aapo Vienamo

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com \
    --to=pgwipeout@gmail.com \
    --cc=adrian.hunter@intel.com \
    --cc=avienamo@nvidia.com \
    --cc=devicetree@vger.kernel.org \
    --cc=jonathanh@nvidia.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mmc@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mperttunen@nvidia.com \
    --cc=robh+dt@kernel.org \
    --cc=thierry.reding@gmail.com \
    --cc=ulf.hansson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.