From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752814AbdA3NNb (ORCPT ); Mon, 30 Jan 2017 08:13:31 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:36572 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752996AbdA3NNL (ORCPT ); Mon, 30 Jan 2017 08:13:11 -0500 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Subject: Re: [PATCH v5 3/8] ARM: dts: rockchip: add timer entries to rk3188 SoC From: Alexander Kochetkov In-Reply-To: <20170130120444.GE2206@mai> Date: Mon, 30 Jan 2017 16:13:07 +0300 Cc: Heiko Stuebner , LKML , devicetree@vger.kernel.org, LAK , linux-rockchip@lists.infradead.org, Thomas Gleixner , Mark Rutland , Rob Herring , Russell King , Caesar Wang , Huang Tao Message-Id: <046978C2-808F-4EC3-9429-063BC1A7CE7B@gmail.com> References: <1485260203-14216-1-git-send-email-al.kochet@gmail.com> <1485260203-14216-4-git-send-email-al.kochet@gmail.com> <20170130110428.GC2206@mai> <20170130120444.GE2206@mai> To: Daniel Lezcano X-Mailer: Apple Mail (2.3124) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v0UDDq0i007327 > 30 янв. 2017 г., в 15:04, Daniel Lezcano написал(а): > > There is no case when the rockchip timer is used for the clockevent. The is already timer entry for rk3228 in the DT. And it act as clockevent. I guess it work as backup, but I cannot test it also. In order to not break DT compatibility I had to provide one timer to be initialized as clockevent. And implemented implicit rule the driver (first DT timer - clockevent, second DT timer - clocksource) already exists for other timers. > If I'm not wrong, you can check /proc/interrupts and see there is no interrupt > on the rockchip timer. Yes, you right here. I’ve temporary disable smp_twd to test rockchip timer interrupts. There is no interrupt on the rockchip timer during normal work. > - when the CPU enters a deep idle state. But such state does not exist on rk3188 ARM chip/revision specific? > - when the system goes to suspend. But the timers are stopped in any case and > CPU0 is always on. There is timer for rk3228 in the DT. I guess there are situations where it can be used. May be the situations are also acceptable for rk3188? May be something like suspend to RAM or suspend to HDD? I am not expert in that questions. I can do some tests if you give hint/link. So, as I understood you suggest to leave only one timer what can be used as clocksource only. I can implement that, but there should be DT rule what allow to setup timer as clocksource only. I cannot do more without timer framework support. Looks, like I have to wait your patch to implement that. Alexander. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Kochetkov Subject: Re: [PATCH v5 3/8] ARM: dts: rockchip: add timer entries to rk3188 SoC Date: Mon, 30 Jan 2017 16:13:07 +0300 Message-ID: <046978C2-808F-4EC3-9429-063BC1A7CE7B@gmail.com> References: <1485260203-14216-1-git-send-email-al.kochet@gmail.com> <1485260203-14216-4-git-send-email-al.kochet@gmail.com> <20170130110428.GC2206@mai> <20170130120444.GE2206@mai> Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20170130120444.GE2206@mai> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Daniel Lezcano Cc: Heiko Stuebner , LKML , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, LAK , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Gleixner , Mark Rutland , Rob Herring , Russell King , Caesar Wang , Huang Tao List-Id: devicetree@vger.kernel.org > 30 =D1=8F=D0=BD=D0=B2. 2017 =D0=B3., =D0=B2 15:04, Daniel Lezcano = =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0= =B0): >=20 > There is no case when the rockchip timer is used for the clockevent. The is already timer entry for rk3228 in the DT. And it act as = clockevent. I guess it work as backup, but I cannot test it also. In order to not break DT compatibility I had = to provide one timer to be initialized as clockevent. And implemented implicit rule the driver = (first DT timer - clockevent, second DT timer - clocksource) already exists for other timers. > If I'm not wrong, you can check /proc/interrupts and see there is no = interrupt > on the rockchip timer. Yes, you right here. I=E2=80=99ve temporary disable smp_twd to test = rockchip timer interrupts. There is no interrupt on the rockchip timer during normal work. > - when the CPU enters a deep idle state. But such state does not exist = on rk3188 ARM chip/revision specific? > - when the system goes to suspend. But the timers are stopped in any = case and > CPU0 is always on. There is timer for rk3228 in the DT. I guess there are situations where = it can be used. May be the situations are also acceptable for rk3188? May be something = like suspend to RAM or suspend to HDD? I am not expert in that questions. I can do some tests = if you give hint/link. So, as I understood you suggest to leave only one timer what can be used = as clocksource only. I can implement that, but there should be DT rule what allow to = setup timer as clocksource only. I cannot do more without timer framework support. Looks, like I have to wait your patch to implement that. Alexander. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: al.kochet@gmail.com (Alexander Kochetkov) Date: Mon, 30 Jan 2017 16:13:07 +0300 Subject: [PATCH v5 3/8] ARM: dts: rockchip: add timer entries to rk3188 SoC In-Reply-To: <20170130120444.GE2206@mai> References: <1485260203-14216-1-git-send-email-al.kochet@gmail.com> <1485260203-14216-4-git-send-email-al.kochet@gmail.com> <20170130110428.GC2206@mai> <20170130120444.GE2206@mai> Message-ID: <046978C2-808F-4EC3-9429-063BC1A7CE7B@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > 30 ???. 2017 ?., ? 15:04, Daniel Lezcano ???????(?): > > There is no case when the rockchip timer is used for the clockevent. The is already timer entry for rk3228 in the DT. And it act as clockevent. I guess it work as backup, but I cannot test it also. In order to not break DT compatibility I had to provide one timer to be initialized as clockevent. And implemented implicit rule the driver (first DT timer - clockevent, second DT timer - clocksource) already exists for other timers. > If I'm not wrong, you can check /proc/interrupts and see there is no interrupt > on the rockchip timer. Yes, you right here. I?ve temporary disable smp_twd to test rockchip timer interrupts. There is no interrupt on the rockchip timer during normal work. > - when the CPU enters a deep idle state. But such state does not exist on rk3188 ARM chip/revision specific? > - when the system goes to suspend. But the timers are stopped in any case and > CPU0 is always on. There is timer for rk3228 in the DT. I guess there are situations where it can be used. May be the situations are also acceptable for rk3188? May be something like suspend to RAM or suspend to HDD? I am not expert in that questions. I can do some tests if you give hint/link. So, as I understood you suggest to leave only one timer what can be used as clocksource only. I can implement that, but there should be DT rule what allow to setup timer as clocksource only. I cannot do more without timer framework support. Looks, like I have to wait your patch to implement that. Alexander.