From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932175AbbKYF5k (ORCPT ); Wed, 25 Nov 2015 00:57:40 -0500 Received: from mail9.hitachi.co.jp ([133.145.228.44]:52846 "EHLO mail9.hitachi.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751182AbbKYF5i (ORCPT ); Wed, 25 Nov 2015 00:57:38 -0500 From: =?utf-8?B?5rKz5ZCI6Iux5a6PIC8gS0FXQUnvvIxISURFSElSTw==?= To: "'Steven Rostedt'" , Borislav Petkov CC: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , "Eric W. Biederman" , "H. Peter Anvin" , Andrew Morton , Thomas Gleixner , Vivek Goyal , Baoquan He , "linux-doc@vger.kernel.org" , "x86@kernel.org" , "kexec@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Michal Hocko , Ingo Molnar , =?utf-8?B?5bmz5p2+6ZuF5bezIC8gSElSQU1BVFXvvIxNQVNBTUk=?= Subject: RE: [V5 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context Thread-Topic: [V5 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context Thread-Index: AQHRI3eQMDnSwb7qM0y43uYtcLxsUp6qbZyAgACTjgCAAUMWkA== Date: Wed, 25 Nov 2015 05:57:34 +0000 Message-ID: <04EAB7311EE43145B2D3536183D1A84454A2A444@GSjpTKYDCembx31.service.hitachi.net> References: <20151120093641.4285.97253.stgit@softrs> <20151120093646.4285.62259.stgit@softrs> <20151124104853.GC3785@pd.tnic> <20151124193700.GB6100@home.goodmis.org> In-Reply-To: <20151124193700.GB6100@home.goodmis.org> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.198.220.44] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id tAP5vj9M026203 > On Tue, Nov 24, 2015 at 11:48:53AM +0100, Borislav Petkov wrote: > > > > > + */ > > > + while (!raw_spin_trylock(&nmi_reason_lock)) > > > + poll_crash_ipi_and_callback(regs); > > > > Waaait a minute: so if we're getting NMIs broadcasted on every core but > > we're *not* crash dumping, we will run into here too. This can't be > > right. :-\ > > This only does something if crash_ipi_done is set, which means you are killing > the box. But perhaps a comment that states that here would be useful, or maybe > just put in the check here. OK, I'll add more comments around this. > There's no need to make it depend on SMP, as > raw_spin_trylock() will turn to just ({1}) for UP, and that code wont even be > hit. I'll integrate these SMP and UP versions with a comment about that. Regards, -- Hidehiro Kawai Hitachi, Ltd. Research & Development Group {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail9.hitachi.co.jp ([133.145.228.44]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a1T5Z-0005CO-SK for kexec@lists.infradead.org; Wed, 25 Nov 2015 05:57:58 +0000 From: =?utf-8?B?5rKz5ZCI6Iux5a6PIC8gS0FXQUnvvIxISURFSElSTw==?= Subject: RE: [V5 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context Date: Wed, 25 Nov 2015 05:57:34 +0000 Message-ID: <04EAB7311EE43145B2D3536183D1A84454A2A444@GSjpTKYDCembx31.service.hitachi.net> References: <20151120093641.4285.97253.stgit@softrs> <20151120093646.4285.62259.stgit@softrs> <20151124104853.GC3785@pd.tnic> <20151124193700.GB6100@home.goodmis.org> In-Reply-To: <20151124193700.GB6100@home.goodmis.org> Content-Language: ja-JP MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: 'Steven Rostedt' , Borislav Petkov Cc: "x86@kernel.org" , Baoquan He , Jonathan Corbet , Peter Zijlstra , "linux-doc@vger.kernel.org" , "kexec@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Michal Hocko , Ingo Molnar , Thomas Gleixner , "Eric W. Biederman" , "H. Peter Anvin" , =?utf-8?B?5bmz5p2+6ZuF5bezIC8gSElSQU1BVFXvvIxNQVNBTUk=?= , Andrew Morton , Ingo Molnar , Vivek Goyal > On Tue, Nov 24, 2015 at 11:48:53AM +0100, Borislav Petkov wrote: > > > > > + */ > > > + while (!raw_spin_trylock(&nmi_reason_lock)) > > > + poll_crash_ipi_and_callback(regs); > > > > Waaait a minute: so if we're getting NMIs broadcasted on every core but > > we're *not* crash dumping, we will run into here too. This can't be > > right. :-\ > > This only does something if crash_ipi_done is set, which means you are killing > the box. But perhaps a comment that states that here would be useful, or maybe > just put in the check here. OK, I'll add more comments around this. > There's no need to make it depend on SMP, as > raw_spin_trylock() will turn to just ({1}) for UP, and that code wont even be > hit. I'll integrate these SMP and UP versions with a comment about that. Regards, -- Hidehiro Kawai Hitachi, Ltd. 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