All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marc Zyngier <marc.zyngier@arm.com>
To: Manish Jaggi <manish.jaggi@cavium.com>,
	xen-devel@lists.xenproject.org, julien.grall@arm.com,
	sstabellini@kernel.org, andre.przywara@arm.com
Subject: Re: [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
Date: Tue, 27 Mar 2018 11:18:46 +0100	[thread overview]
Message-ID: <05029e6f-6812-d02e-aa41-e5ff4f0c0cad@arm.com> (raw)
In-Reply-To: <e7402c406f8c894ee469cd8f7f08c16c4c2e90ad.1522135597.git.manish.jaggi@cavium.com>

On 27/03/18 10:07, Manish Jaggi wrote:
> This patch is ported to xen from linux commit
> b6f49035b4bf6e2709f2a5fed3107f5438c1fd02
> KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
> 
> Add a handler for writing the guest's view of the ICC_EOIR1_EL1
> register. This involves dropping the priority of the interrupt,
> and deactivating it if required (EOImode == 0).
> 
> Signed-off-by : Manish Jaggi <manish.jaggi@cavium.com>
> ---
>  xen/arch/arm/arm64/vgic-v3-sr.c     | 136 ++++++++++++++++++++++++++++++++++++
>  xen/include/asm-arm/arm64/sysregs.h |   1 +
>  xen/include/asm-arm/gic_v3_defs.h   |   4 ++
>  3 files changed, 141 insertions(+)
> 
> diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
> index 026d64506f..e32ec01f56 100644
> --- a/xen/arch/arm/arm64/vgic-v3-sr.c
> +++ b/xen/arch/arm/arm64/vgic-v3-sr.c
> @@ -33,6 +33,7 @@
>  
>  #define ICC_IAR1_EL1_SPURIOUS    0x3ff
>  #define VGIC_MAX_SPI             1019
> +#define VGIC_MIN_LPI             8192
>  
>  static int vgic_v3_bpr_min(void)
>  {
> @@ -482,6 +483,137 @@ static void vreg_emulate_iar(struct cpu_user_regs *regs, const union hsr hsr)
>      vgic_v3_read_iar(regs, hsr);
>  }
>  
> +static int vgic_v3_find_active_lr(int intid, uint64_t *lr_val)
> +{
> +    int i;
> +    unsigned int used_lrs =  gic_get_num_lrs();

This is quite a departure from the existing code. KVM always allocate
LRs sequentially, and used_lrs represents the current upper bound. Here,
you seem to be looking at *all* the LRs. Is that safe? Are you
guaranteed not to have any stale state?

In any case, the change should be documented.

> +
> +    for ( i = 0; i < used_lrs; i++ )
> +    {
> +        uint64_t val = gicv3_ich_read_lr(i);
> +
> +        if ( (val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
> +            (val & ICH_LR_ACTIVE_BIT) )
> +        {
> +            *lr_val = val;
> +            return i;
> +        }
> +    }
> +
> +    *lr_val = ICC_IAR1_EL1_SPURIOUS;
> +    return -1;
> +}

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

  reply	other threads:[~2018-03-27 10:18 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-27  9:07 [PATCH v2 00/17] arm64: Mediate access to GICv3 sysregs at EL2 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps Manish Jaggi
2018-03-27 10:01   ` Marc Zyngier
2018-03-27 10:10     ` Manish Jaggi
2018-03-27 10:22       ` Marc Zyngier
2018-03-27 20:16         ` Stefano Stabellini
2018-03-28  0:48           ` Julien Grall
2018-03-28  3:48             ` Manish Jaggi
2018-04-03 15:33               ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler Manish Jaggi
2018-03-27 10:30   ` Marc Zyngier
2018-03-27 10:35     ` Manish Jaggi
2018-03-27 10:45       ` Marc Zyngier
2018-03-27 10:56         ` Manish Jaggi
2018-03-27 11:05           ` Marc Zyngier
2018-03-27 11:07             ` Manish Jaggi
2018-03-27 11:11               ` Marc Zyngier
2018-03-27 11:15                 ` Manish Jaggi
2018-03-27 11:25                   ` Marc Zyngier
2018-03-27 11:27                     ` Manish Jaggi
2018-03-27 11:38                       ` Marc Zyngier
2018-03-28  3:51                         ` Manish Jaggi
2018-04-03 15:59                           ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 03/17] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 04/17] arm64: Add accessors for the ICH_APxRn_EL2 registers Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 05/17] Expose ich_read/write_lr in vgic-v3-sr.c Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 06/17] arm64: Add ICV_IAR1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Manish Jaggi
2018-03-27 10:18   ` Marc Zyngier [this message]
2018-04-02 11:03     ` Manish Jaggi
2018-04-02 11:17       ` Manish Jaggi
2018-04-05  9:40         ` Julien Grall
2018-04-05 19:53           ` Stefano Stabellini
2018-04-06  8:37           ` Manish Jaggi
2018-04-11 14:16             ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 08/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 09/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Manish Jaggi
2018-03-27 10:56   ` Marc Zyngier
2018-03-27 11:02     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 10/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 11/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers Manish Jaggi
2018-03-27 10:58   ` Marc Zyngier
2018-03-27 11:01     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 13/17] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 14/17] arm64: Add config for Cavium Thunder erratum 30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 15/17] arm: Hook workaround handler from traps.c based on Cavium workaround_30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 16/17] arm64: if trapping a write-to-read-only GICv3 access inject Undef exception in guest Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 17/17] arm64: if trapping a read-from-write-only GICv3 access inject undef " Manish Jaggi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=05029e6f-6812-d02e-aa41-e5ff4f0c0cad@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=andre.przywara@arm.com \
    --cc=julien.grall@arm.com \
    --cc=manish.jaggi@cavium.com \
    --cc=sstabellini@kernel.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.