From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98C73C433EF for ; Tue, 19 Jul 2022 04:04:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236578AbiGSEED (ORCPT ); Tue, 19 Jul 2022 00:04:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236509AbiGSEEB (ORCPT ); Tue, 19 Jul 2022 00:04:01 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D67AF2BB3F for ; Mon, 18 Jul 2022 21:04:00 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BFFE1042; Mon, 18 Jul 2022 21:04:01 -0700 (PDT) Received: from [10.162.41.8] (unknown [10.162.41.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D0E6A3F766; Mon, 18 Jul 2022 21:03:54 -0700 (PDT) Message-ID: <05639c8d-73f7-7e12-9941-cae3037e44b4@arm.com> Date: Tue, 19 Jul 2022 09:33:52 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [RESEND PATCH v3] arm64: enable THP_SWAP for arm64 Content-Language: en-US To: Barry Song <21cnbao@gmail.com> Cc: "Huang, Ying" , Andrew Morton , Catalin Marinas , LAK , Linux-MM , Steven Price , Will Deacon , Andrea Arcangeli , =?UTF-8?B?6YOt5YGl?= , hanchuanhua , Johannes Weiner , Hugh Dickins , LKML , Minchan Kim , Yang Shi , Barry Song , =?UTF-8?B?5byg6K+X5piOKFNpbW9uIFpoYW5nKQ==?= References: <20220718090050.2261-1-21cnbao@gmail.com> <87mtd62apo.fsf@yhuang6-desk2.ccr.corp.intel.com> <87zgh5232o.fsf@yhuang6-desk2.ccr.corp.intel.com> <416a06f6-ca7d-d4a9-2cda-af0ad6e28261@arm.com> From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/19/22 09:29, Barry Song wrote: > On Tue, Jul 19, 2022 at 3:35 PM Anshuman Khandual > wrote: >> >> >> >> On 7/19/22 08:58, Huang, Ying wrote: >>> Anshuman Khandual writes: >>> >>>> On 7/19/22 06:53, Barry Song wrote: >>>>> On Tue, Jul 19, 2022 at 12:44 PM Huang, Ying wrote: >>>>>> >>>>>> Barry Song <21cnbao@gmail.com> writes: >>>>>> >>>>>>> From: Barry Song >>>>>>> >>>>>>> THP_SWAP has been proven to improve the swap throughput significantly >>>>>>> on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay >>>>>>> splitting THP after swapped out"). >>>>>>> As long as arm64 uses 4K page size, it is quite similar with x86_64 >>>>>>> by having 2MB PMD THP. THP_SWAP is architecture-independent, thus, >>>>>>> enabling it on arm64 will benefit arm64 as well. >>>>>>> A corner case is that MTE has an assumption that only base pages >>>>>>> can be swapped. We won't enable THP_SWAP for ARM64 hardware with >>>>>>> MTE support until MTE is reworked to coexist with THP_SWAP. >>>>>>> >>>>>>> A micro-benchmark is written to measure thp swapout throughput as >>>>>>> below, >>>>>>> >>>>>>> unsigned long long tv_to_ms(struct timeval tv) >>>>>>> { >>>>>>> return tv.tv_sec * 1000 + tv.tv_usec / 1000; >>>>>>> } >>>>>>> >>>>>>> main() >>>>>>> { >>>>>>> struct timeval tv_b, tv_e;; >>>>>>> #define SIZE 400*1024*1024 >>>>>>> volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, >>>>>>> MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); >>>>>>> if (!p) { >>>>>>> perror("fail to get memory"); >>>>>>> exit(-1); >>>>>>> } >>>>>>> >>>>>>> madvise(p, SIZE, MADV_HUGEPAGE); >>>>>>> memset(p, 0x11, SIZE); /* write to get mem */ >>>>>>> >>>>>>> gettimeofday(&tv_b, NULL); >>>>>>> madvise(p, SIZE, MADV_PAGEOUT); >>>>>>> gettimeofday(&tv_e, NULL); >>>>>>> >>>>>>> printf("swp out bandwidth: %ld bytes/ms\n", >>>>>>> SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b))); >>>>>>> } >>>>>>> >>>>>>> Testing is done on rk3568 64bit quad core processor Quad Core >>>>>>> Cortex-A55 platform - ROCK 3A. >>>>>>> thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests) >>>>>>> thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests) >>>>>>> >>>>>>> Cc: "Huang, Ying" >>>>>>> Cc: Minchan Kim >>>>>>> Cc: Johannes Weiner >>>>>>> Cc: Hugh Dickins >>>>>>> Cc: Andrea Arcangeli >>>>>>> Cc: Anshuman Khandual >>>>>>> Cc: Steven Price >>>>>>> Cc: Yang Shi >>>>>>> Signed-off-by: Barry Song >>>>>>> --- >>>>>>> -v3: >>>>>>> * refine the commit log; >>>>>>> * add a benchmark result; >>>>>>> * refine the macro of arch_thp_swp_supported >>>>>>> Thanks to the comments of Anshuman, Andrew, Steven >>>>>>> >>>>>>> arch/arm64/Kconfig | 1 + >>>>>>> arch/arm64/include/asm/pgtable.h | 6 ++++++ >>>>>>> include/linux/huge_mm.h | 12 ++++++++++++ >>>>>>> mm/swap_slots.c | 2 +- >>>>>>> 4 files changed, 20 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>>>>>> index 1652a9800ebe..e1c540e80eec 100644 >>>>>>> --- a/arch/arm64/Kconfig >>>>>>> +++ b/arch/arm64/Kconfig >>>>>>> @@ -101,6 +101,7 @@ config ARM64 >>>>>>> select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP >>>>>>> select ARCH_WANT_LD_ORPHAN_WARN >>>>>>> select ARCH_WANTS_NO_INSTR >>>>>>> + select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES >>>>>>> select ARCH_HAS_UBSAN_SANITIZE_ALL >>>>>>> select ARM_AMBA >>>>>>> select ARM_ARCH_TIMER >>>>>>> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >>>>>>> index 0b6632f18364..78d6f6014bfb 100644 >>>>>>> --- a/arch/arm64/include/asm/pgtable.h >>>>>>> +++ b/arch/arm64/include/asm/pgtable.h >>>>>>> @@ -45,6 +45,12 @@ >>>>>>> __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) >>>>>>> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ >>>>>>> >>>>>>> +static inline bool arch_thp_swp_supported(void) >>>>>>> +{ >>>>>>> + return !system_supports_mte(); >>>>>>> +} >>>>>>> +#define arch_thp_swp_supported arch_thp_swp_supported >>>>>>> + >>>>>>> /* >>>>>>> * Outside of a few very special situations (e.g. hibernation), we always >>>>>>> * use broadcast TLB invalidation instructions, therefore a spurious page >>>>>>> diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h >>>>>>> index de29821231c9..4ddaf6ad73ef 100644 >>>>>>> --- a/include/linux/huge_mm.h >>>>>>> +++ b/include/linux/huge_mm.h >>>>>>> @@ -461,4 +461,16 @@ static inline int split_folio_to_list(struct folio *folio, >>>>>>> return split_huge_page_to_list(&folio->page, list); >>>>>>> } >>>>>>> >>>>>>> +/* >>>>>>> + * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to >>>>>>> + * limitations in the implementation like arm64 MTE can override this to >>>>>>> + * false >>>>>>> + */ >>>>>>> +#ifndef arch_thp_swp_supported >>>>>>> +static inline bool arch_thp_swp_supported(void) >>>>>>> +{ >>>>>>> + return true; >>>>>>> +} >>>>>> >>>>>> How about the following? >>>>>> >>>>>> static inline bool arch_wants_thp_swap(void) >>>>>> { >>>>>> return IS_ENABLED(ARCH_WANTS_THP_SWAP); >>>>>> } >>>>> >>>>> This looks good. then i'll need to change arm64 to >>>>> >>>>> +static inline bool arch_thp_swp_supported(void) >>>>> +{ >>>>> + return IS_ENABLED(ARCH_WANTS_THP_SWAP) && !system_supports_mte(); >>>>> +} >>>> >>>> Why ? CONFIG_THP_SWAP depends on ARCH_WANTS_THP_SWAP. In folio_alloc_swap(), >>>> IS_ENABLED(CONFIG_THP_SWAP) enabled, will also imply ARCH_WANTS_THP_SWAP too >>>> is enabled. Hence checking for ARCH_WANTS_THP_SWAP again does not make sense >>>> either in the generic fallback stub, or in arm64 platform override. Because >>>> without ARCH_WANTS_THP_SWAP enabled, arch_thp_swp_supported() should never >>>> be called in the first place. >>> >>> For the only caller now, the checking looks redundant. But the original >>> proposed implementation as follows, >>> >>> static inline bool arch_thp_swp_supported(void) >>> { >>> return true; >>> } >>> >>> will return true even on architectures that don't support/want THP swap. >> >> But the function will never be called on for those platforms. >> >>> That will confuse people too. >> >> I dont see how. >> >>> >>> And the "redundant" checking has no run time overhead, because compiler >>> will do the trick. >> I understand that, but dont think this indirection is necessary. > > Hi Anshuman, Hi Ying, > Thanks for the comments of both of you. Does the below look ok? > > generic, > > static inline bool arch_wants_thp_swap(void) > { > return IS_ENABLED(CONFIG_THP_SWAP); > } > > arm64, > > static inline bool arch_thp_swp_supported(void) > { > return IS_ENABLED(CONFIG_THP_SWAP) && !system_supports_mte(); > } > > caller, > > folio_alloc_swap(struct folio *folio) > { > > if (folio_test_large(folio)) { > - if (IS_ENABLED(CONFIG_THP_SWAP)) > + if (arch_thp_swp_supported()) > get_swap_pages(1, &entry, folio_nr_pages(folio)); > goto out; > } Current proposal in this patch LGTM, I dont see any reason for these changes. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EFF2C43334 for ; Tue, 19 Jul 2022 04:05:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AsuI8fXotOJUWh/8/Ddr/JKN6RwiniCxS13q7pIhDlg=; b=EXapicdveneLml ZCUf1PYqizIez2Q5gHboWfKpQ+bGL6K0HIueSEc3WLsg5PUMXOij2dD7KPjBYEASFVqgBQVeearhy WaSp8ydn9wUk0Xi/Pip12NREYPDVPprJz27Y4EppJZNb0Vio0L5HCk5clL4xsJ9Xkz/AEubi48hb3 3D6/cc8piYeuf/04OG3KcnV/44G1xk7giOnpDC6GK8JX7wRD8Xr4YiWrAv/LuNtfmXVGfe+iQzIXi cJMR3+tQ8OshgOUSxNCcEVw+AWjtzydk2JZC8bECtMkemFt1TO6/Ow2+l0UCxLkmjjPi58woVHMBz jIbBehLKygFILr1LnjmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oDeSt-004brU-0V; Tue, 19 Jul 2022 04:04:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oDeSp-004bm6-Di for linux-arm-kernel@lists.infradead.org; Tue, 19 Jul 2022 04:04:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BFFE1042; Mon, 18 Jul 2022 21:04:01 -0700 (PDT) Received: from [10.162.41.8] (unknown [10.162.41.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D0E6A3F766; Mon, 18 Jul 2022 21:03:54 -0700 (PDT) Message-ID: <05639c8d-73f7-7e12-9941-cae3037e44b4@arm.com> Date: Tue, 19 Jul 2022 09:33:52 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [RESEND PATCH v3] arm64: enable THP_SWAP for arm64 Content-Language: en-US To: Barry Song <21cnbao@gmail.com> Cc: "Huang, Ying" , Andrew Morton , Catalin Marinas , LAK , Linux-MM , Steven Price , Will Deacon , Andrea Arcangeli , =?UTF-8?B?6YOt5YGl?= , hanchuanhua , Johannes Weiner , Hugh Dickins , LKML , Minchan Kim , Yang Shi , Barry Song , =?UTF-8?B?5byg6K+X5piOKFNpbW9uIFpoYW5nKQ==?= References: <20220718090050.2261-1-21cnbao@gmail.com> <87mtd62apo.fsf@yhuang6-desk2.ccr.corp.intel.com> <87zgh5232o.fsf@yhuang6-desk2.ccr.corp.intel.com> <416a06f6-ca7d-d4a9-2cda-af0ad6e28261@arm.com> From: Anshuman Khandual In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220718_210403_585316_1FD7CC95 X-CRM114-Status: GOOD ( 23.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/19/22 09:29, Barry Song wrote: > On Tue, Jul 19, 2022 at 3:35 PM Anshuman Khandual > wrote: >> >> >> >> On 7/19/22 08:58, Huang, Ying wrote: >>> Anshuman Khandual writes: >>> >>>> On 7/19/22 06:53, Barry Song wrote: >>>>> On Tue, Jul 19, 2022 at 12:44 PM Huang, Ying wrote: >>>>>> >>>>>> Barry Song <21cnbao@gmail.com> writes: >>>>>> >>>>>>> From: Barry Song >>>>>>> >>>>>>> THP_SWAP has been proven to improve the swap throughput significantly >>>>>>> on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay >>>>>>> splitting THP after swapped out"). >>>>>>> As long as arm64 uses 4K page size, it is quite similar with x86_64 >>>>>>> by having 2MB PMD THP. THP_SWAP is architecture-independent, thus, >>>>>>> enabling it on arm64 will benefit arm64 as well. >>>>>>> A corner case is that MTE has an assumption that only base pages >>>>>>> can be swapped. We won't enable THP_SWAP for ARM64 hardware with >>>>>>> MTE support until MTE is reworked to coexist with THP_SWAP. >>>>>>> >>>>>>> A micro-benchmark is written to measure thp swapout throughput as >>>>>>> below, >>>>>>> >>>>>>> unsigned long long tv_to_ms(struct timeval tv) >>>>>>> { >>>>>>> return tv.tv_sec * 1000 + tv.tv_usec / 1000; >>>>>>> } >>>>>>> >>>>>>> main() >>>>>>> { >>>>>>> struct timeval tv_b, tv_e;; >>>>>>> #define SIZE 400*1024*1024 >>>>>>> volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, >>>>>>> MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); >>>>>>> if (!p) { >>>>>>> perror("fail to get memory"); >>>>>>> exit(-1); >>>>>>> } >>>>>>> >>>>>>> madvise(p, SIZE, MADV_HUGEPAGE); >>>>>>> memset(p, 0x11, SIZE); /* write to get mem */ >>>>>>> >>>>>>> gettimeofday(&tv_b, NULL); >>>>>>> madvise(p, SIZE, MADV_PAGEOUT); >>>>>>> gettimeofday(&tv_e, NULL); >>>>>>> >>>>>>> printf("swp out bandwidth: %ld bytes/ms\n", >>>>>>> SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b))); >>>>>>> } >>>>>>> >>>>>>> Testing is done on rk3568 64bit quad core processor Quad Core >>>>>>> Cortex-A55 platform - ROCK 3A. >>>>>>> thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests) >>>>>>> thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests) >>>>>>> >>>>>>> Cc: "Huang, Ying" >>>>>>> Cc: Minchan Kim >>>>>>> Cc: Johannes Weiner >>>>>>> Cc: Hugh Dickins >>>>>>> Cc: Andrea Arcangeli >>>>>>> Cc: Anshuman Khandual >>>>>>> Cc: Steven Price >>>>>>> Cc: Yang Shi >>>>>>> Signed-off-by: Barry Song >>>>>>> --- >>>>>>> -v3: >>>>>>> * refine the commit log; >>>>>>> * add a benchmark result; >>>>>>> * refine the macro of arch_thp_swp_supported >>>>>>> Thanks to the comments of Anshuman, Andrew, Steven >>>>>>> >>>>>>> arch/arm64/Kconfig | 1 + >>>>>>> arch/arm64/include/asm/pgtable.h | 6 ++++++ >>>>>>> include/linux/huge_mm.h | 12 ++++++++++++ >>>>>>> mm/swap_slots.c | 2 +- >>>>>>> 4 files changed, 20 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>>>>>> index 1652a9800ebe..e1c540e80eec 100644 >>>>>>> --- a/arch/arm64/Kconfig >>>>>>> +++ b/arch/arm64/Kconfig >>>>>>> @@ -101,6 +101,7 @@ config ARM64 >>>>>>> select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP >>>>>>> select ARCH_WANT_LD_ORPHAN_WARN >>>>>>> select ARCH_WANTS_NO_INSTR >>>>>>> + select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES >>>>>>> select ARCH_HAS_UBSAN_SANITIZE_ALL >>>>>>> select ARM_AMBA >>>>>>> select ARM_ARCH_TIMER >>>>>>> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >>>>>>> index 0b6632f18364..78d6f6014bfb 100644 >>>>>>> --- a/arch/arm64/include/asm/pgtable.h >>>>>>> +++ b/arch/arm64/include/asm/pgtable.h >>>>>>> @@ -45,6 +45,12 @@ >>>>>>> __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) >>>>>>> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ >>>>>>> >>>>>>> +static inline bool arch_thp_swp_supported(void) >>>>>>> +{ >>>>>>> + return !system_supports_mte(); >>>>>>> +} >>>>>>> +#define arch_thp_swp_supported arch_thp_swp_supported >>>>>>> + >>>>>>> /* >>>>>>> * Outside of a few very special situations (e.g. hibernation), we always >>>>>>> * use broadcast TLB invalidation instructions, therefore a spurious page >>>>>>> diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h >>>>>>> index de29821231c9..4ddaf6ad73ef 100644 >>>>>>> --- a/include/linux/huge_mm.h >>>>>>> +++ b/include/linux/huge_mm.h >>>>>>> @@ -461,4 +461,16 @@ static inline int split_folio_to_list(struct folio *folio, >>>>>>> return split_huge_page_to_list(&folio->page, list); >>>>>>> } >>>>>>> >>>>>>> +/* >>>>>>> + * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to >>>>>>> + * limitations in the implementation like arm64 MTE can override this to >>>>>>> + * false >>>>>>> + */ >>>>>>> +#ifndef arch_thp_swp_supported >>>>>>> +static inline bool arch_thp_swp_supported(void) >>>>>>> +{ >>>>>>> + return true; >>>>>>> +} >>>>>> >>>>>> How about the following? >>>>>> >>>>>> static inline bool arch_wants_thp_swap(void) >>>>>> { >>>>>> return IS_ENABLED(ARCH_WANTS_THP_SWAP); >>>>>> } >>>>> >>>>> This looks good. then i'll need to change arm64 to >>>>> >>>>> +static inline bool arch_thp_swp_supported(void) >>>>> +{ >>>>> + return IS_ENABLED(ARCH_WANTS_THP_SWAP) && !system_supports_mte(); >>>>> +} >>>> >>>> Why ? CONFIG_THP_SWAP depends on ARCH_WANTS_THP_SWAP. In folio_alloc_swap(), >>>> IS_ENABLED(CONFIG_THP_SWAP) enabled, will also imply ARCH_WANTS_THP_SWAP too >>>> is enabled. Hence checking for ARCH_WANTS_THP_SWAP again does not make sense >>>> either in the generic fallback stub, or in arm64 platform override. Because >>>> without ARCH_WANTS_THP_SWAP enabled, arch_thp_swp_supported() should never >>>> be called in the first place. >>> >>> For the only caller now, the checking looks redundant. But the original >>> proposed implementation as follows, >>> >>> static inline bool arch_thp_swp_supported(void) >>> { >>> return true; >>> } >>> >>> will return true even on architectures that don't support/want THP swap. >> >> But the function will never be called on for those platforms. >> >>> That will confuse people too. >> >> I dont see how. >> >>> >>> And the "redundant" checking has no run time overhead, because compiler >>> will do the trick. >> I understand that, but dont think this indirection is necessary. > > Hi Anshuman, Hi Ying, > Thanks for the comments of both of you. Does the below look ok? > > generic, > > static inline bool arch_wants_thp_swap(void) > { > return IS_ENABLED(CONFIG_THP_SWAP); > } > > arm64, > > static inline bool arch_thp_swp_supported(void) > { > return IS_ENABLED(CONFIG_THP_SWAP) && !system_supports_mte(); > } > > caller, > > folio_alloc_swap(struct folio *folio) > { > > if (folio_test_large(folio)) { > - if (IS_ENABLED(CONFIG_THP_SWAP)) > + if (arch_thp_swp_supported()) > get_swap_pages(1, &entry, folio_nr_pages(folio)); > goto out; > } Current proposal in this patch LGTM, I dont see any reason for these changes. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel