[PATCH 00/13] arm: Implement ARMv8.1-PMU and ARMv8.4-PMU

* [PATCH 00/13] arm: Implement ARMv8.1-PMU and ARMv8.4-PMU
@ 2020-02-11 17:37 Peter Maydell
  2020-02-11 17:37 ` [PATCH 01/13] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
                   ` (12 more replies)
  0 siblings, 13 replies; 37+ messages in thread
From: Peter Maydell @ 2020-02-11 17:37 UTC (permalink / raw)
  To: qemu-arm, qemu-devel; +Cc: Eric Auger, Aaron Lindsay, Richard Henderson

This patchset implements the ARMv8.1-PMU and ARMv8.4-PMU architecture
extensions. These are fairly small changes on top of the basic
PMUv3 we already implement, and in fact we already had most of
the v8.1-PMU functionality implemented but unadvertised.

In the course of doing this, I found that our naming and use of
isar_feature ID register test functions was slightly inconsistent,
so the first few patches straighten this out and align on:

 * functions which test AArch32 ID registers always have an
   _aa32_ infix in their name, and can only be used if we
   know the CPU has AArch32 (eg in codegen in translate.c)
   or if "false" is the right answer for a no-AArch32 CPU
   (eg registering AArch32-only system registers, or
   determining whether to allow guest writes to sysreg bits
   that are writeable only on the AArch32 version of the reg)
 * functions which test AArch64 ID registers always have an
   _aa64_ infix in their name, and can only be used if
   we know the CPU has AArch64 or if "false" is the right
   answer for a no-AArch64 CPU
 * functions with an _any_ infix always return the logical
   OR of the _aa32_ and _aa64_ tests, and should be used
   when we want to know "does this feature exist" in code
   that might be called for AArch32 or AArch64

I have audited all the callsites of isar_feature tests and they
almost all followed this naming convention and usage already.  We
were missing the _aa32_ infix in the arm_div, thumb_div and jazelle
tests, and we needed an _any_ version of the function for fp16
(specifically whether FP(S)CR.FZ16 is writeable) and for predinv
(whether to register the sysregs).

Having got those preliminaries out of the way, we can define _aa32_,
_aa64_ and _any_ versions of "do I have a PMUv3 with the v8.1
extensions?", and use them when implementing the extended
functionality.

The ARMv8.1-PMU extension requires:
 * the evtCount field in PMETYPER<n>_EL0 is 16 bits, not 10
 * MDCR_EL2.HPMD allows event counting to be disabled at EL2
 * two new required events, STALL_FRONTEND and STALL_BACKEND
 * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0
We already implement all of that except the new events;
for QEMU our CPU never "stalls" in that sense, so we can
just implement them as always-reads-zero.

The ARMv8.4-PMU extension adds:
 * one new required event, STALL (again, reads-as-zero)
 * one new system register PMMIR_EL1, which provides information
   about the PMU implementation. Since the only currently defined
   field in it relates to an event we don't provide, we can
   validly implement the register as RAZ.

The final two patches fix some bugs I discovered while
running this through Eric's recent kvm-unit-tests PMU tests:
 * we had the wrong definition of the PMCR.DP bit position
 * we incorrectly implemented PMCR.LC as RAZ/WI

I've tested this with Eric's unit tests, and by running 'perf test'
in a VM (which had some failures but none which seemed to be related
to these changes).  I don't generally use the perf emulation, so
testing would be welcome from people who do.

Based-on: 20200210120146.17631-1-peter.maydell@linaro.org
("target/arm: Implement ARMv8.1-VMID16 extension")
purely to avoid possible textual conflicts.

thanks
-- PMM

Peter Maydell (13):
  target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID
    registers
  target/arm: Add isar_feature_any_fp16 and document naming/usage
    conventions
  target/arm: Define and use any_predinv isar_feature test
  target/arm: Factor out PMU register definitions
  target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
  target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
  target/arm: Define an aa32_pmu_8_1 isar feature test function
  target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
  target/arm: Implement ARMv8.1-PMU extension
  target/arm: Implement ARMv8.4-PMU extension
  target/arm: Provide ARMv8.4-PMU in '-cpu max'
  target/arm: Correct definition of PMCRDP
  target/arm: Correct handling of PMCR_EL0.LC bit

 target/arm/cpu.h        |  87 +++++++++++++-
 hw/intc/armv7m_nvic.c   |   2 +-
 linux-user/elfload.c    |   4 +-
 target/arm/cpu.c        |  37 +++---
 target/arm/cpu64.c      |  20 +++-
 target/arm/helper.c     | 248 ++++++++++++++++++++++++----------------
 target/arm/translate.c  |   6 +-
 target/arm/vfp_helper.c |   2 +-
 8 files changed, 273 insertions(+), 133 deletions(-)

-- 
2.20.1

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