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Sat, 23 Oct 2021 22:04:53 -0700 (PDT) Subject: Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20211023214803.522078-1-f4bug@amsat.org> <20211023214803.522078-18-f4bug@amsat.org> From: Richard Henderson Message-ID: <05abb10d-25c6-3b39-dd43-cc269dc1dcb0@linaro.org> Date: Sat, 23 Oct 2021 22:04:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211023214803.522078-18-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.781, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luis Pires Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote: > Convert the FILL opcode (Vector Fill from GPR) to decodetree. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/tcg/msa.decode | 2 ++ > target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++---------- > 2 files changed, 30 insertions(+), 12 deletions(-) > > diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode > index 2997bfa24e3..e97490cf880 100644 > --- a/target/mips/tcg/msa.decode > +++ b/target/mips/tcg/msa.decode > @@ -21,6 +21,7 @@ > @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst > @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 > @bz ...... ... df:2 wt:5 sa:16 &msa_bz > +@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 > @2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0 > @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst > @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst > @@ -76,6 +77,7 @@ BNZ 010001 111 .. ..... ................ @bz > SRARI 011110 010 ....... ..... ..... 001010 @bit > SRLRI 011110 011 ....... ..... ..... 001010 @bit > > + FILL 011110 11000000 .. ..... ..... 011110 @2r > FCLASS 011110 110010000 . ..... ..... 011110 @2rf > FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf > FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf > diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c > index c6a77381c0e..fc0b80f83ac 100644 > --- a/target/mips/tcg/msa_translate.c > +++ b/target/mips/tcg/msa_translate.c > @@ -53,7 +53,6 @@ enum { > OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC, > > /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */ > - OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R, > OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R, > OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R, > OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R, > @@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx) > TCGv_i32 tws = tcg_const_i32(ws); > > switch (MASK_MSA_2R(ctx->opcode)) { > - case OPC_FILL_df: > -#if !defined(TARGET_MIPS64) > - /* Double format valid only for MIPS64 */ > - if (df == DF_DOUBLE) { > - gen_reserved_instruction(ctx); > - break; > - } > -#endif > - gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df), > - twd, tws); /* trs */ > - break; > case OPC_NLOC_df: > switch (df) { > case DF_BYTE: > @@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx) > tcg_temp_free_i32(tws); > } > > +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) > +{ > + TCGv_i32 twd; > + TCGv_i32 tws; > + TCGv_i32 tdf; > + > + if (!check_msa_access(ctx)) { > + return false; > + } > + > + if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { > + /* Double format valid only for MIPS64 */ > + gen_reserved_instruction(ctx); > + return true; > + } I expect this reserved check should be above the MSA is disabled check, within check_msa_access. > + twd = tcg_const_i32(a->wd); > + tws = tcg_const_i32(a->ws); tcg_constant_i32. r~