From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1F00C48BDF for ; Thu, 10 Jun 2021 22:33:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9EEA7613E7 for ; Thu, 10 Jun 2021 22:33:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9EEA7613E7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 311F16EE09; Thu, 10 Jun 2021 22:33:34 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DC786E1F4; Thu, 10 Jun 2021 22:33:32 +0000 (UTC) IronPort-SDR: D2PZFnKGXrJT07H7wOcpeAsL6fphpbmMf/QbFVedTzX+FxyKCl1ZCtwIIhAL84dYJseHVZUqx3 U3z9/uy4l4nA== X-IronPort-AV: E=McAfee;i="6200,9189,10011"; a="205380372" X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="205380372" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2021 15:33:25 -0700 IronPort-SDR: /4IryvMKs4e4TizN00b5hnVUpUScCIhgoyMwpXT51Riz/dKPylBQmsqBHL1g+mbSCCxIrxc7K0 gSRacYEizJSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="483034271" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by orsmga001.jf.intel.com with ESMTP; 10 Jun 2021 15:33:22 -0700 Received: from [10.249.139.200] (mwajdecz-MOBL.ger.corp.intel.com [10.249.139.200]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 15AMXL7o031710; Thu, 10 Jun 2021 23:33:21 +0100 Subject: Re: [PATCH 1/3] drm/i915/guc: Add fetch of hwconfig table To: John.C.Harrison@Intel.com, Intel-GFX@Lists.FreeDesktop.Org References: <20210610204626.2995262-1-John.C.Harrison@Intel.com> <20210610204626.2995262-2-John.C.Harrison@Intel.com> From: Michal Wajdeczko Message-ID: <05ffd7fa-8ebb-7d63-89dd-84116ccbe824@intel.com> Date: Fri, 11 Jun 2021 00:33:21 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210610204626.2995262-2-John.C.Harrison@Intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: DRI-Devel@Lists.FreeDesktop.Org, Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 10.06.2021 22:46, John.C.Harrison@Intel.com wrote: > From: John Harrison > > Implement support for fetching the hardware description table from the > GuC. The call is made twice - once without a destination buffer to > query the size and then a second time to fill in the buffer. > > This patch also adds a header file which lists all the attribute values > currently defined for the table. This is included for reference as > these are not currently used by the i915 driver itself. > > Note that the table is only available on ADL-P and later platforms. > > Cc: Michal Wajdeczko > Signed-off-by: Rodrigo Vivi > Signed-off-by: John Harrison > --- > drivers/gpu/drm/i915/Makefile | 1 + > .../gpu/drm/i915/gt/intel_hwconfig_types.h | 102 +++++++++++ > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 + > .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 + > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 +- > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + > .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 167 ++++++++++++++++++ > .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 ++ > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 + > 9 files changed, 304 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/i915/gt/intel_hwconfig_types.h > create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c > create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 2adb6b420c7c..8e957ca7c9f1 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -187,6 +187,7 @@ i915-y += gt/uc/intel_uc.o \ > gt/uc/intel_guc_log.o \ > gt/uc/intel_guc_log_debugfs.o \ > gt/uc/intel_guc_submission.o \ > + gt/uc/intel_guc_hwconfig.o \ > gt/uc/intel_huc.o \ > gt/uc/intel_huc_debugfs.o \ > gt/uc/intel_huc_fw.o > diff --git a/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h b/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h > new file mode 100644 > index 000000000000..b09c0f65b93a > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h > @@ -0,0 +1,102 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2020 Intel Corporation it's already June'21 > + */ > + > +#ifndef _INTEL_HWCONFIG_TYPES_H_ > +#define _INTEL_HWCONFIG_TYPES_H_ > + > +/** > + * enum intel_hwconfig - Global definition of hwconfig table attributes > + * > + * Intel devices provide a KLV (Key/Length/Value) table containing > + * the static hardware configuration for that platform. > + * This header defines the current attribute keys for this KLV. s/header/enum as this is enum documentation likely separate DOC: section with explanation of the whole HW KLV concept could be helpful if plugged into i915 rst > + */ > +enum intel_hwconfig { > + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1, > + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */ putting estimated enum values in comments could be misleading, as if someone accidentally add some enum in the middle then all values in comments will be stale if you really want stable definitions, without risking accidental breakage, then better to define enums with explicit value, like you did for the first one: INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1, INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED = 2, INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS = 3, ... > + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */ > + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */ > + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */ > + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */ > + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */ what's the meaning of the 'deprecated' here ? if not used in ADLP and beyond, then I guess no reason to define them. just skip these numbers: INTEL_HWCONFIG_NUM_PIXEL_PIPES = 4, /* 5-7 not used/reserved/deprecated */ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES = 8, > + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */ > + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */ > + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */ > + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */ > + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */ > + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */ > + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */ > + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */ > + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */ > + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */ > + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */ > + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */ > + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */ > + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */ > + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */ > + INTEL_HWCONFIG_MAX_RCS, /* 23 */ > + INTEL_HWCONFIG_MAX_CCS, /* 24 */ > + INTEL_HWCONFIG_MAX_VCS, /* 25 */ > + INTEL_HWCONFIG_MAX_VECS, /* 26 */ > + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */ > + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */ > + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */ > + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */ > + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */ > + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */ > + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */ > + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */ > + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */ > + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */ > + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */ > + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */ > + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */ > + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */ > + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */ > + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */ > + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */ > + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */ > + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */ > + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */ > + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */ > + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */ > + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */ > + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */ > + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */ > + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */ > + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */ > + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */ > + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */ > + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */ > + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */ > + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */ > + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */ > + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */ > + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */ > + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */ > + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */ > + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */ > + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */ > + __INTEL_HWCONFIG_LIMIT what's the purpose of this 'limit' ? > +}; > + below are values definitions just for two keys, what about others like MAX_PIXEL_FILL_RATE ? either add them all or introduce by one while adding support > +enum { > + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0, > + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5, > +}; > + > +#define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0) > +#define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1) > +#define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2) why mixing style for KLV values ? you can still use enum: enum { INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0), INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1), INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2), }; and as you're using BIT macro then likely you should earlier add: #include > + > +#endif /* _INTEL_HWCONFIG_TYPES_H_ */ > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > index 90efef8a73e4..075f56a040b7 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > @@ -19,6 +19,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > + INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100, > INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, > INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, > INTEL_GUC_ACTION_LIMIT > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h > index 488b6061ee89..f9e2a6aaef4a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h > @@ -8,6 +8,10 @@ > > enum intel_guc_response_status { > INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, > + INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20, > + INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201, > + INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202, > + INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204, > INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, > }; > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index f147cb389a20..01839d5eb130 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -407,13 +407,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, > /* > * No GuC command should ever take longer than 10ms. > * Fast commands should still complete in 10us. > + * Except for the hwconfig table query, which takes ~50ms. I assume this is a limitation of the specific fw release and will be fixed in next releases, so maybe worth to add some FIXME to don't forget to drop this hack once fw is fixed ? > */ > ret = __intel_wait_for_register_fw(uncore, > guc_send_reg(guc, 0), > INTEL_GUC_MSG_TYPE_MASK, > INTEL_GUC_MSG_TYPE_RESPONSE << > INTEL_GUC_MSG_TYPE_SHIFT, > - 10, 10, &status); > + 10, 100, &status); > /* If GuC explicitly returned an error, convert it to -EIO */ > if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status)) > ret = -EIO; > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > index 4abc59f6f3cd..8307de463af0 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > @@ -12,6 +12,7 @@ > #include "intel_guc_ct.h" > #include "intel_guc_log.h" > #include "intel_guc_reg.h" > +#include "intel_guc_hwconfig.h" > #include "intel_uc_fw.h" > #include "i915_utils.h" > #include "i915_vma.h" > @@ -27,6 +28,7 @@ struct intel_guc { > struct intel_uc_fw fw; > struct intel_guc_log log; > struct intel_guc_ct ct; > + struct intel_guc_hwconfig hwconfig; > > /* intel_guc_recv interrupt related state */ > spinlock_t irq_lock; > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c > new file mode 100644 > index 000000000000..938b1edb7209 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c > @@ -0,0 +1,167 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2020 Intel Corporation 2021 > + */ > + > +#include "gt/intel_gt.h" > +#include "gt/intel_hwconfig_types.h" > +#include "i915_drv.h" > +#include "i915_memcpy.h" > +#include "intel_guc_hwconfig.h" > + > +static > +inline struct intel_guc *hwconfig_to_guc(struct intel_guc_hwconfig *hwconfig) no need to (badly) split lines, column limit is 100 > +{ > + return container_of(hwconfig, struct intel_guc, hwconfig); > +} > + > +/** this doesn't looks like kernel doc > + * GuC has a blob containing hardware configuration information (hwconfig). later you are using "HWConfig" name > + * This is formatted as a simple and flexible KLV (Key/Length/Value) table. in file intel_hwconfig_types.h there was statement "Intel devices provide a KLV ..." so maybe we don't have to repeat that here and also just move example below to .h where whole concept could be explained in one place. > + * > + * For example, a minimal version could be: > + * enum device_attr { > + * ATTR_SOME_VALUE = 0, > + * ATTR_SOME_MASK = 1, > + * }; > + * > + * static const u32 hwconfig[] = { > + * ATTR_SOME_VALUE, > + * 1, // Value Length in DWords > + * 8, // Value > + * > + * ATTR_SOME_MASK, > + * 3, > + * 0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000, > + * }; > + * > + * The attribute ids are defined in a hardware spec. The current list as > + * known to the i915 driver can be found in i915/gt/intel_guc_hwconfig_types.h > + */ > + > +static int __guc_action_get_hwconfig(struct intel_guc_hwconfig *hwconfig, all other "guc_action" functions take directly "guc" as param > + u32 ggtt_offset, u32 ggtt_size) > +{ > + struct intel_guc *guc = hwconfig_to_guc(hwconfig); > + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; > + u32 action[] = { > + INTEL_GUC_ACTION_GET_HWCONFIG, > + ggtt_offset, > + ggtt_size, > + (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915), > + }; > + int ret; > + > + ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); why this is over MMIO? as you need to pass GGTT then CTB is also already available... > + if (ret == -ENXIO) > + return -ENOENT; > + > + if (!ggtt_size && !ret) > + ret = -EINVAL; > + > + return ret; > +} > + > +static int guc_hwconfig_discover_size(struct intel_guc_hwconfig *hwconfig) > +{ > + int ret; > + > + /* Sending a query with too small a table will return the size of the table */ likely: "Sending a query with zero buffer size will return .." > + ret = __guc_action_get_hwconfig(hwconfig, 0, 0); > + if (ret < 0) > + return ret; > + > + hwconfig->size = ret; > + return 0; > +} > + > +static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig) > +{ > + struct intel_guc *guc = hwconfig_to_guc(hwconfig); > + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; > + u32 ggtt_offset; > + int ret; > + struct i915_vma *vma; > + void *vaddr; nit: some would prefer this order: struct i915_vma *vma; u32 ggtt_offset; void *vaddr; int ret; > + > + GEM_BUG_ON(!hwconfig->size); > + > + ret = intel_guc_allocate_and_map_vma(guc, hwconfig->size, &vma, &vaddr); > + if (ret) { > + drm_err(&i915->drm, "HWConfig: Failed to allocate buffer: %d!\n", ret); we can fail in many different ways, also in other places, why only this case has dedicated error message ? nit: to be more friendly we can print error code with %pe > + return ret; > + } > + > + ggtt_offset = intel_guc_ggtt_offset(guc, vma); > + > + ret = __guc_action_get_hwconfig(hwconfig, ggtt_offset, hwconfig->size); > + if (ret >= 0) > + memcpy(hwconfig->ptr, vaddr, hwconfig->size); do you plan to add some validation of the received klvs ? like if last one is not truncated ? and to (debug) print it anywhere ? and maybe to add to error capture? > + > + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); > + > + return ret; > +} > + > +static bool has_table(struct drm_i915_private *i915) > +{ > + if (IS_ALDERLAKE_P(i915)) { > + if (IS_ADLP_GT_STEP(i915, STEP_A0, STEP_A0)) > + return 0; > + > + return 1; nit: this could be single line: return !IS_ADLP_GT_STEP(i915, STEP_A0, STEP_A0); and maybe add few words as in commit message you said all ADP-P have it > + } > + > + return 0; since you defined function as returning bool, then use true/false > +} > + > +/** > + * intel_guc_hwconfig_init - Initialize the HWConfig > + * > + * Retrieve the HWConfig table from the GuC and save it away in a local memory > + * allocation. It can then be queried on demand by other users later on. > + */ > +int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig) > +{ > + struct intel_guc *guc = hwconfig_to_guc(hwconfig); > + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; > + int ret; > + > + if (!has_table(i915)) > + return 0; > + > + ret = guc_hwconfig_discover_size(hwconfig); > + if (ret) > + return ret; > + > + hwconfig->ptr = kmalloc(hwconfig->size, GFP_KERNEL); > + if (!hwconfig->ptr) { > + hwconfig->size = 0; > + return -ENOMEM; > + } > + > + ret = guc_hwconfig_fill_buffer(hwconfig); > + if (ret < 0) { > + kfree(hwconfig->ptr); > + hwconfig->size = 0; > + hwconfig->ptr = NULL; > + return ret; maybe use onion cleanup ? > + } > + > + return 0; > +} > + > +/** > + * intel_guc_hwconfig_fini - Finalize the HWConfig > + * > + * Free up the memory allocation holding the table. > + */ > +void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig) > +{ > + if (!hwconfig->size) > + return; not needed, kfree will work with null > + > + kfree(hwconfig->ptr); > + hwconfig->size = 0; > + hwconfig->ptr = NULL; > +} > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h > new file mode 100644 > index 000000000000..91e96d88d713 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2020 Intel Corporation 2021 > + */ > + > +#ifndef _INTEL_GUC_HWCONFIG_H_ > +#define _INTEL_GUC_HWCONFIG_H_ > + > +#include > + > +struct intel_guc_hwconfig { > + u32 size; size in bytes or dwords ? > + void *ptr; nit: as this is ptr to klv dwords, maybe: u32 *kls; > +}; > + > +int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig); > +void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig); > + > +#endif /* _INTEL_GUC_HWCONFIG_H_ */ > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index 6d8b9233214e..b289693f9767 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -502,6 +502,10 @@ static int __uc_init_hw(struct intel_uc *uc) > > intel_huc_auth(huc); > > + ret = intel_guc_hwconfig_init(&guc->hwconfig); > + if (ret) > + goto err_log_capture; > + > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_enable(guc); > > @@ -552,6 +556,8 @@ static void __uc_fini_hw(struct intel_uc *uc) > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_disable(guc); > > + intel_guc_hwconfig_fini(&guc->hwconfig); > + > __uc_sanitize(uc); > } > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC3D2C48BD1 for ; Thu, 10 Jun 2021 22:33:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D745613E7 for ; Thu, 10 Jun 2021 22:33:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D745613E7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CF6F6E1F4; Thu, 10 Jun 2021 22:33:34 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DC786E1F4; Thu, 10 Jun 2021 22:33:32 +0000 (UTC) IronPort-SDR: D2PZFnKGXrJT07H7wOcpeAsL6fphpbmMf/QbFVedTzX+FxyKCl1ZCtwIIhAL84dYJseHVZUqx3 U3z9/uy4l4nA== X-IronPort-AV: E=McAfee;i="6200,9189,10011"; a="205380372" X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="205380372" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2021 15:33:25 -0700 IronPort-SDR: /4IryvMKs4e4TizN00b5hnVUpUScCIhgoyMwpXT51Riz/dKPylBQmsqBHL1g+mbSCCxIrxc7K0 gSRacYEizJSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="483034271" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by orsmga001.jf.intel.com with ESMTP; 10 Jun 2021 15:33:22 -0700 Received: from [10.249.139.200] (mwajdecz-MOBL.ger.corp.intel.com [10.249.139.200]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 15AMXL7o031710; Thu, 10 Jun 2021 23:33:21 +0100 To: John.C.Harrison@Intel.com, Intel-GFX@Lists.FreeDesktop.Org References: <20210610204626.2995262-1-John.C.Harrison@Intel.com> <20210610204626.2995262-2-John.C.Harrison@Intel.com> From: Michal Wajdeczko Message-ID: <05ffd7fa-8ebb-7d63-89dd-84116ccbe824@intel.com> Date: Fri, 11 Jun 2021 00:33:21 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210610204626.2995262-2-John.C.Harrison@Intel.com> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Add fetch of hwconfig table X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: DRI-Devel@Lists.FreeDesktop.Org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" CgpPbiAxMC4wNi4yMDIxIDIyOjQ2LCBKb2huLkMuSGFycmlzb25ASW50ZWwuY29tIHdyb3RlOgo+ IEZyb206IEpvaG4gSGFycmlzb24gPEpvaG4uQy5IYXJyaXNvbkBJbnRlbC5jb20+Cj4gCj4gSW1w bGVtZW50IHN1cHBvcnQgZm9yIGZldGNoaW5nIHRoZSBoYXJkd2FyZSBkZXNjcmlwdGlvbiB0YWJs ZSBmcm9tIHRoZQo+IEd1Qy4gVGhlIGNhbGwgaXMgbWFkZSB0d2ljZSAtIG9uY2Ugd2l0aG91dCBh IGRlc3RpbmF0aW9uIGJ1ZmZlciB0bwo+IHF1ZXJ5IHRoZSBzaXplIGFuZCB0aGVuIGEgc2Vjb25k IHRpbWUgdG8gZmlsbCBpbiB0aGUgYnVmZmVyLgo+IAo+IFRoaXMgcGF0Y2ggYWxzbyBhZGRzIGEg aGVhZGVyIGZpbGUgd2hpY2ggbGlzdHMgYWxsIHRoZSBhdHRyaWJ1dGUgdmFsdWVzCj4gY3VycmVu dGx5IGRlZmluZWQgZm9yIHRoZSB0YWJsZS4gVGhpcyBpcyBpbmNsdWRlZCBmb3IgcmVmZXJlbmNl IGFzCj4gdGhlc2UgYXJlIG5vdCBjdXJyZW50bHkgdXNlZCBieSB0aGUgaTkxNSBkcml2ZXIgaXRz ZWxmLgo+IAo+IE5vdGUgdGhhdCB0aGUgdGFibGUgaXMgb25seSBhdmFpbGFibGUgb24gQURMLVAg YW5kIGxhdGVyIHBsYXRmb3Jtcy4KPiAKPiBDYzogTWljaGFsIFdhamRlY3prbyA8bWljaGFsLndh amRlY3prb0BpbnRlbC5jb20+Cj4gU2lnbmVkLW9mZi1ieTogUm9kcmlnbyBWaXZpIDxyb2RyaWdv LnZpdmlAaW50ZWwuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEpvaG4gSGFycmlzb24gPEpvaG4uQy5I YXJyaXNvbkBJbnRlbC5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L01ha2VmaWxl ICAgICAgICAgICAgICAgICB8ICAgMSArCj4gIC4uLi9ncHUvZHJtL2k5MTUvZ3QvaW50ZWxfaHdj b25maWdfdHlwZXMuaCAgICB8IDEwMiArKysrKysrKysrKwo+ICAuLi4vZ3B1L2RybS9pOTE1L2d0 L3VjL2FiaS9ndWNfYWN0aW9uc19hYmkuaCAgfCAgIDEgKwo+ICAuLi4vZ3B1L2RybS9pOTE1L2d0 L3VjL2FiaS9ndWNfZXJyb3JzX2FiaS5oICAgfCAgIDQgKwo+ICBkcml2ZXJzL2dwdS9kcm0vaTkx NS9ndC91Yy9pbnRlbF9ndWMuYyAgICAgICAgfCAgIDMgKy0KPiAgZHJpdmVycy9ncHUvZHJtL2k5 MTUvZ3QvdWMvaW50ZWxfZ3VjLmggICAgICAgIHwgICAyICsKPiAgLi4uL2dwdS9kcm0vaTkxNS9n dC91Yy9pbnRlbF9ndWNfaHdjb25maWcuYyAgIHwgMTY3ICsrKysrKysrKysrKysrKysrKwo+ICAu Li4vZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5oICAgfCAgMTkgKysKPiAg ZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfdWMuYyAgICAgICAgIHwgICA2ICsKPiAg OSBmaWxlcyBjaGFuZ2VkLCAzMDQgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQo+ICBjcmVh dGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvaW50ZWxfaHdjb25maWdfdHlw ZXMuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50 ZWxfZ3VjX2h3Y29uZmlnLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9p OTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5oCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9pOTE1L01ha2VmaWxlIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvTWFrZWZpbGUKPiBp bmRleCAyYWRiNmI0MjBjN2MuLjhlOTU3Y2E3YzlmMSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9NYWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L01ha2VmaWxl Cj4gQEAgLTE4Nyw2ICsxODcsNyBAQCBpOTE1LXkgKz0gZ3QvdWMvaW50ZWxfdWMubyBcCj4gIAkg IGd0L3VjL2ludGVsX2d1Y19sb2cubyBcCj4gIAkgIGd0L3VjL2ludGVsX2d1Y19sb2dfZGVidWdm cy5vIFwKPiAgCSAgZ3QvdWMvaW50ZWxfZ3VjX3N1Ym1pc3Npb24ubyBcCj4gKwkgIGd0L3VjL2lu dGVsX2d1Y19od2NvbmZpZy5vIFwKPiAgCSAgZ3QvdWMvaW50ZWxfaHVjLm8gXAo+ICAJICBndC91 Yy9pbnRlbF9odWNfZGVidWdmcy5vIFwKPiAgCSAgZ3QvdWMvaW50ZWxfaHVjX2Z3Lm8KPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvaW50ZWxfaHdjb25maWdfdHlwZXMuaCBi L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L2ludGVsX2h3Y29uZmlnX3R5cGVzLmgKPiBuZXcgZmls ZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMC4uYjA5YzBmNjViOTNhCj4gLS0tIC9k ZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L2ludGVsX2h3Y29uZmlnX3R5 cGVzLmgKPiBAQCAtMCwwICsxLDEwMiBAQAo+ICsvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjog TUlUICovCj4gKy8qCj4gKyAqIENvcHlyaWdodCDCqSAyMDIwIEludGVsIENvcnBvcmF0aW9uCgpp dCdzIGFscmVhZHkgSnVuZScyMQoKPiArICovCj4gKwo+ICsjaWZuZGVmIF9JTlRFTF9IV0NPTkZJ R19UWVBFU19IXwo+ICsjZGVmaW5lIF9JTlRFTF9IV0NPTkZJR19UWVBFU19IXwo+ICsKPiArLyoq Cj4gKyAqIGVudW0gaW50ZWxfaHdjb25maWcgLSBHbG9iYWwgZGVmaW5pdGlvbiBvZiBod2NvbmZp ZyB0YWJsZSBhdHRyaWJ1dGVzCj4gKyAqCj4gKyAqIEludGVsIGRldmljZXMgcHJvdmlkZSBhIEtM ViAoS2V5L0xlbmd0aC9WYWx1ZSkgdGFibGUgY29udGFpbmluZwo+ICsgKiB0aGUgc3RhdGljIGhh cmR3YXJlIGNvbmZpZ3VyYXRpb24gZm9yIHRoYXQgcGxhdGZvcm0uCj4gKyAqIFRoaXMgaGVhZGVy IGRlZmluZXMgdGhlIGN1cnJlbnQgYXR0cmlidXRlIGtleXMgZm9yIHRoaXMgS0xWLgoKcy9oZWFk ZXIvZW51bQoKYXMgdGhpcyBpcyBlbnVtIGRvY3VtZW50YXRpb24KCmxpa2VseSBzZXBhcmF0ZSBE T0M6IHNlY3Rpb24gd2l0aCBleHBsYW5hdGlvbiBvZiB0aGUgd2hvbGUgSFcgS0xWCmNvbmNlcHQg Y291bGQgYmUgaGVscGZ1bCBpZiBwbHVnZ2VkIGludG8gaTkxNSByc3QKCj4gKyAqLwo+ICtlbnVt IGludGVsX2h3Y29uZmlnIHsKPiArCUlOVEVMX0hXQ09ORklHX01BWF9TTElDRVNfU1VQUE9SVEVE ID0gMSwKPiArCUlOVEVMX0hXQ09ORklHX01BWF9EVUFMX1NVQlNMSUNFU19TVVBQT1JURUQsCQkv KiAyICovCgpwdXR0aW5nIGVzdGltYXRlZCBlbnVtIHZhbHVlcyBpbiBjb21tZW50cyBjb3VsZCBi ZSBtaXNsZWFkaW5nLCBhcyBpZgpzb21lb25lIGFjY2lkZW50YWxseSBhZGQgc29tZSBlbnVtIGlu IHRoZSBtaWRkbGUgdGhlbiBhbGwgdmFsdWVzIGluCmNvbW1lbnRzIHdpbGwgYmUgc3RhbGUKCmlm IHlvdSByZWFsbHkgd2FudCBzdGFibGUgZGVmaW5pdGlvbnMsIHdpdGhvdXQgcmlza2luZyBhY2Np ZGVudGFsCmJyZWFrYWdlLCB0aGVuIGJldHRlciB0byBkZWZpbmUgZW51bXMgd2l0aCBleHBsaWNp dCB2YWx1ZSwgbGlrZSB5b3UgZGlkCmZvciB0aGUgZmlyc3Qgb25lOgoKCUlOVEVMX0hXQ09ORklH X01BWF9TTElDRVNfU1VQUE9SVEVEID0gMSwKCUlOVEVMX0hXQ09ORklHX01BWF9EVUFMX1NVQlNM SUNFU19TVVBQT1JURUQgPSAyLAoJSU5URUxfSFdDT05GSUdfTUFYX05VTV9FVV9QRVJfRFNTID0g MywKCS4uLgoKPiArCUlOVEVMX0hXQ09ORklHX01BWF9OVU1fRVVfUEVSX0RTUywJCQkvKiAzICov Cj4gKwlJTlRFTF9IV0NPTkZJR19OVU1fUElYRUxfUElQRVMsCQkJCS8qIDQgKi8KPiArCUlOVEVM X0hXQ09ORklHX0RFUFJFQ0FURURfTUFYX05VTV9HRU9NRVRSWV9QSVBFUywJLyogNSAqLwo+ICsJ SU5URUxfSFdDT05GSUdfREVQUkVDQVRFRF9MM19DQUNIRV9TSVpFX0lOX0tCLAkJLyogNiAqLwo+ ICsJSU5URUxfSFdDT05GSUdfREVQUkVDQVRFRF9MM19CQU5LX0NPVU5ULAkJLyogNyAqLwoKd2hh dCdzIHRoZSBtZWFuaW5nIG9mIHRoZSAnZGVwcmVjYXRlZCcgaGVyZSA/CgppZiBub3QgdXNlZCBp biBBRExQIGFuZCBiZXlvbmQsIHRoZW4gSSBndWVzcyBubyByZWFzb24gdG8gZGVmaW5lIHRoZW0u Cmp1c3Qgc2tpcCB0aGVzZSBudW1iZXJzOgoKCUlOVEVMX0hXQ09ORklHX05VTV9QSVhFTF9QSVBF UyA9IDQsCgkvKiA1LTcgbm90IHVzZWQvcmVzZXJ2ZWQvZGVwcmVjYXRlZCAqLwoJSU5URUxfSFdD T05GSUdfTDNfQ0FDSEVfV0FZU19TSVpFX0lOX0JZVEVTID0gOCwKCj4gKwlJTlRFTF9IV0NPTkZJ R19MM19DQUNIRV9XQVlTX1NJWkVfSU5fQllURVMsCQkvKiA4ICovCj4gKwlJTlRFTF9IV0NPTkZJ R19MM19DQUNIRV9XQVlTX1BFUl9TRUNUT1IsCQkvKiA5ICovCj4gKwlJTlRFTF9IV0NPTkZJR19N QVhfTUVNT1JZX0NIQU5ORUxTLAkJCS8qIDEwICovCj4gKwlJTlRFTF9IV0NPTkZJR19NRU1PUllf VFlQRSwJCQkJLyogMTEgKi8KPiArCUlOVEVMX0hXQ09ORklHX0NBQ0hFX1RZUEVTLCAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgLyogMTIgKi8KPiArCUlOVEVMX0hXQ09ORklHX0xPQ0FMX01F TU9SWV9QQUdFX1NJWkVTX1NVUFBPUlRFRCwJLyogMTMgKi8KPiArCUlOVEVMX0hXQ09ORklHX0RF UFJFQ0FURURfU0xNX1NJWkVfSU5fS0IsCQkvKiAxNCAqLwo+ICsJSU5URUxfSFdDT05GSUdfTlVN X1RIUkVBRFNfUEVSX0VVLAkJCS8qIDE1ICovCj4gKwlJTlRFTF9IV0NPTkZJR19UT1RBTF9WU19U SFJFQURTLAkJCS8qIDE2ICovCj4gKwlJTlRFTF9IV0NPTkZJR19UT1RBTF9HU19USFJFQURTLAkJ CS8qIDE3ICovCj4gKwlJTlRFTF9IV0NPTkZJR19UT1RBTF9IU19USFJFQURTLAkJCS8qIDE4ICov Cj4gKwlJTlRFTF9IV0NPTkZJR19UT1RBTF9EU19USFJFQURTLAkJCS8qIDE5ICovCj4gKwlJTlRF TF9IV0NPTkZJR19UT1RBTF9WU19USFJFQURTX1BPQ1MsCQkJLyogMjAgKi8KPiArCUlOVEVMX0hX Q09ORklHX1RPVEFMX1BTX1RIUkVBRFMsCQkJLyogMjEgKi8KPiArCUlOVEVMX0hXQ09ORklHX0RF UFJFQ0FURURfTUFYX0ZJTExfUkFURSwJCS8qIDIyICovCj4gKwlJTlRFTF9IV0NPTkZJR19NQVhf UkNTLAkJCQkJLyogMjMgKi8KPiArCUlOVEVMX0hXQ09ORklHX01BWF9DQ1MsCQkJCQkvKiAyNCAq Lwo+ICsJSU5URUxfSFdDT05GSUdfTUFYX1ZDUywJCQkJCS8qIDI1ICovCj4gKwlJTlRFTF9IV0NP TkZJR19NQVhfVkVDUywJCQkJLyogMjYgKi8KPiArCUlOVEVMX0hXQ09ORklHX01BWF9DT1BZX0NT LAkJCQkvKiAyNyAqLwo+ICsJSU5URUxfSFdDT05GSUdfREVQUkVDQVRFRF9VUkJfU0laRV9JTl9L QiwJCS8qIDI4ICovCj4gKwlJTlRFTF9IV0NPTkZJR19NSU5fVlNfVVJCX0VOVFJJRVMsCQkJLyog MjkgKi8KPiArCUlOVEVMX0hXQ09ORklHX01BWF9WU19VUkJfRU5UUklFUywJCQkvKiAzMCAqLwo+ ICsJSU5URUxfSFdDT05GSUdfTUlOX1BDU19VUkJfRU5UUklFUywJCQkvKiAzMSAqLwo+ICsJSU5U RUxfSFdDT05GSUdfTUFYX1BDU19VUkJfRU5UUklFUywJCQkvKiAzMiAqLwo+ICsJSU5URUxfSFdD T05GSUdfTUlOX0hTX1VSQl9FTlRSSUVTLAkJCS8qIDMzICovCj4gKwlJTlRFTF9IV0NPTkZJR19N QVhfSFNfVVJCX0VOVFJJRVMsCQkJLyogMzQgKi8KPiArCUlOVEVMX0hXQ09ORklHX01JTl9HU19V UkJfRU5UUklFUywJCQkvKiAzNSAqLwo+ICsJSU5URUxfSFdDT05GSUdfTUFYX0dTX1VSQl9FTlRS SUVTLAkJCS8qIDM2ICovCj4gKwlJTlRFTF9IV0NPTkZJR19NSU5fRFNfVVJCX0VOVFJJRVMsCQkJ LyogMzcgKi8KPiArCUlOVEVMX0hXQ09ORklHX01BWF9EU19VUkJfRU5UUklFUywJCQkvKiAzOCAq Lwo+ICsJSU5URUxfSFdDT05GSUdfUFVTSF9DT05TVEFOVF9VUkJfUkVTRVJWRURfU0laRSwJCS8q IDM5ICovCj4gKwlJTlRFTF9IV0NPTkZJR19QT0NTX1BVU0hfQ09OU1RBTlRfVVJCX1JFU0VSVkVE X1NJWkUsCS8qIDQwICovCj4gKwlJTlRFTF9IV0NPTkZJR19VUkJfUkVHSU9OX0FMSUdOTUVOVF9T SVpFX0lOX0JZVEVTLAkvKiA0MSAqLwo+ICsJSU5URUxfSFdDT05GSUdfVVJCX0FMTE9DQVRJT05f U0laRV9VTklUU19JTl9CWVRFUywJLyogNDIgKi8KPiArCUlOVEVMX0hXQ09ORklHX01BWF9VUkJf U0laRV9DQ1NfSU5fQllURVMsCQkvKiA0MyAqLwo+ICsJSU5URUxfSFdDT05GSUdfVlNfTUlOX0RF UkVGX0JMT0NLX1NJWkVfSEFORExFX0NPVU5ULAkvKiA0NCAqLwo+ICsJSU5URUxfSFdDT05GSUdf RFNfTUlOX0RFUkVGX0JMT0NLX1NJWkVfSEFORExFX0NPVU5ULAkvKiA0NSAqLwo+ICsJSU5URUxf SFdDT05GSUdfTlVNX1JUX1NUQUNLU19QRVJfRFNTLAkJCS8qIDQ2ICovCj4gKwlJTlRFTF9IV0NP TkZJR19NQVhfVVJCX1NUQVJUSU5HX0FERFJFU1MsCQkvKiA0NyAqLwo+ICsJSU5URUxfSFdDT05G SUdfTUlOX0NTX1VSQl9FTlRSSUVTLAkJCS8qIDQ4ICovCj4gKwlJTlRFTF9IV0NPTkZJR19NQVhf Q1NfVVJCX0VOVFJJRVMsCQkJLyogNDkgKi8KPiArCUlOVEVMX0hXQ09ORklHX0wzX0FMTE9DX1BF Ul9CQU5LX1VSQiwJCQkvKiA1MCAqLwo+ICsJSU5URUxfSFdDT05GSUdfTDNfQUxMT0NfUEVSX0JB TktfUkVTVCwJCQkvKiA1MSAqLwo+ICsJSU5URUxfSFdDT05GSUdfTDNfQUxMT0NfUEVSX0JBTktf REMsCQkJLyogNTIgKi8KPiArCUlOVEVMX0hXQ09ORklHX0wzX0FMTE9DX1BFUl9CQU5LX1JPLAkJ CS8qIDUzICovCj4gKwlJTlRFTF9IV0NPTkZJR19MM19BTExPQ19QRVJfQkFOS19aLAkJCS8qIDU0 ICovCj4gKwlJTlRFTF9IV0NPTkZJR19MM19BTExPQ19QRVJfQkFOS19DT0xPUiwJCQkvKiA1NSAq Lwo+ICsJSU5URUxfSFdDT05GSUdfTDNfQUxMT0NfUEVSX0JBTktfVU5JRklFRF9USUxFX0NBQ0hF LAkvKiA1NiAqLwo+ICsJSU5URUxfSFdDT05GSUdfTDNfQUxMT0NfUEVSX0JBTktfQ09NTUFORF9C VUZGRVIsCS8qIDU3ICovCj4gKwlJTlRFTF9IV0NPTkZJR19MM19BTExPQ19QRVJfQkFOS19SVywJ CQkvKiA1OCAqLwo+ICsJSU5URUxfSFdDT05GSUdfTUFYX05VTV9MM19DT05GSUdTLAkJCS8qIDU5 ICovCj4gKwlJTlRFTF9IV0NPTkZJR19CSU5ETEVTU19TVVJGQUNFX09GRlNFVF9CSVRfQ09VTlQs CS8qIDYwICovCj4gKwlJTlRFTF9IV0NPTkZJR19SRVNFUlZFRF9DQ1NfV0FZUywJCQkvKiA2MSAq Lwo+ICsJSU5URUxfSFdDT05GSUdfQ1NSX1NJWkVfSU5fTUIsCQkJCS8qIDYyICovCj4gKwlJTlRF TF9IV0NPTkZJR19HRU9NRVRSWV9QSVBFU19QRVJfU0xJQ0UsCQkvKiA2MyAqLwo+ICsJSU5URUxf SFdDT05GSUdfTDNfQkFOS19TSVpFX0lOX0tCLAkJCS8qIDY0ICovCj4gKwlJTlRFTF9IV0NPTkZJ R19TTE1fU0laRV9QRVJfRFNTLAkJCS8qIDY1ICovCj4gKwlJTlRFTF9IV0NPTkZJR19NQVhfUElY RUxfRklMTF9SQVRFX1BFUl9TTElDRSwJCS8qIDY2ICovCj4gKwlJTlRFTF9IV0NPTkZJR19NQVhf UElYRUxfRklMTF9SQVRFX1BFUl9EU1MsCQkvKiA2NyAqLwo+ICsJSU5URUxfSFdDT05GSUdfVVJC X1NJWkVfUEVSX1NMSUNFX0lOX0tCLAkJLyogNjggKi8KPiArCUlOVEVMX0hXQ09ORklHX1VSQl9T SVpFX1BFUl9MM19CQU5LX0NPVU5UX0lOX0tCLAkvKiA2OSAqLwo+ICsJSU5URUxfSFdDT05GSUdf TUFYX1NVQlNMSUNFLAkJCQkvKiA3MCAqLwo+ICsJSU5URUxfSFdDT05GSUdfTUFYX0VVX1BFUl9T VUJTTElDRSwJCQkvKiA3MSAqLwo+ICsJSU5URUxfSFdDT05GSUdfUkFNQk9fTDNfQkFOS19TSVpF X0lOX0tCLAkJLyogNzIgKi8KPiArCUlOVEVMX0hXQ09ORklHX1NMTV9TSVpFX1BFUl9TU19JTl9L QiwJCQkvKiA3MyAqLwo+ICsJX19JTlRFTF9IV0NPTkZJR19MSU1JVAoKd2hhdCdzIHRoZSBwdXJw b3NlIG9mIHRoaXMgJ2xpbWl0JyA/Cgo+ICt9Owo+ICsKCmJlbG93IGFyZSB2YWx1ZXMgZGVmaW5p dGlvbnMganVzdCBmb3IgdHdvIGtleXMsCndoYXQgYWJvdXQgb3RoZXJzIGxpa2UgTUFYX1BJWEVM X0ZJTExfUkFURSA/CmVpdGhlciBhZGQgdGhlbSBhbGwgb3IgaW50cm9kdWNlIGJ5IG9uZSB3aGls ZSBhZGRpbmcgc3VwcG9ydAoKPiArZW51bSB7Cj4gKwlJTlRFTF9IV0NPTkZJR19NRU1PUllfVFlQ RV9MUEREUjQgPSAwLAo+ICsJSU5URUxfSFdDT05GSUdfTUVNT1JZX1RZUEVfTFBERFI1LAo+ICt9 Owo+ICsKPiArI2RlZmluZSBJTlRFTF9IV0NPTkZJR19DQUNIRV9UWVBFX0wzCUJJVCgwKQo+ICsj ZGVmaW5lIElOVEVMX0hXQ09ORklHX0NBQ0hFX1RZUEVfTExDCUJJVCgxKQo+ICsjZGVmaW5lIElO VEVMX0hXQ09ORklHX0NBQ0hFX1RZUEVfRURSQU0JQklUKDIpCgp3aHkgbWl4aW5nIHN0eWxlIGZv ciBLTFYgdmFsdWVzID8geW91IGNhbiBzdGlsbCB1c2UgZW51bToKCmVudW0gewoJSU5URUxfSFdD T05GSUdfQ0FDSEVfVFlQRV9MMyA9IEJJVCgwKSwKCUlOVEVMX0hXQ09ORklHX0NBQ0hFX1RZUEVf TExDID0gQklUKDEpLAoJSU5URUxfSFdDT05GSUdfQ0FDSEVfVFlQRV9FRFJBTQk9IEJJVCgyKSwK fTsKCmFuZCBhcyB5b3UncmUgdXNpbmcgQklUIG1hY3JvIHRoZW4gbGlrZWx5IHlvdSBzaG91bGQg ZWFybGllciBhZGQ6CgojaW5jbHVkZSA8bGludXgvYml0cy5oPgoKCj4gKwo+ICsjZW5kaWYgLyog X0lOVEVMX0hXQ09ORklHX1RZUEVTX0hfICovCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2d0L3VjL2FiaS9ndWNfYWN0aW9uc19hYmkuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2d0L3VjL2FiaS9ndWNfYWN0aW9uc19hYmkuaAo+IGluZGV4IDkwZWZlZjhhNzNlNC4uMDc1ZjU2 YTA0MGI3IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2FiaS9ndWNf YWN0aW9uc19hYmkuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2FiaS9ndWNf YWN0aW9uc19hYmkuaAo+IEBAIC0xOSw2ICsxOSw3IEBAIGVudW0gaW50ZWxfZ3VjX2FjdGlvbiB7 Cj4gIAlJTlRFTF9HVUNfQUNUSU9OX0VYSVRfU19TVEFURSA9IDB4NTAyLAo+ICAJSU5URUxfR1VD X0FDVElPTl9TTFBDX1JFUVVFU1QgPSAweDMwMDMsCj4gIAlJTlRFTF9HVUNfQUNUSU9OX0FVVEhF TlRJQ0FURV9IVUMgPSAweDQwMDAsCj4gKwlJTlRFTF9HVUNfQUNUSU9OX0dFVF9IV0NPTkZJRyA9 IDB4NDEwMCwKPiAgCUlOVEVMX0dVQ19BQ1RJT05fUkVHSVNURVJfQ09NTUFORF9UUkFOU1BPUlRf QlVGRkVSID0gMHg0NTA1LAo+ICAJSU5URUxfR1VDX0FDVElPTl9ERVJFR0lTVEVSX0NPTU1BTkRf VFJBTlNQT1JUX0JVRkZFUiA9IDB4NDUwNiwKPiAgCUlOVEVMX0dVQ19BQ1RJT05fTElNSVQKPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvYWJpL2d1Y19lcnJvcnNfYWJp LmggYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9hYmkvZ3VjX2Vycm9yc19hYmkuaAo+IGlu ZGV4IDQ4OGI2MDYxZWU4OS4uZjllMmE2YWFlZjRhIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2d0L3VjL2FiaS9ndWNfZXJyb3JzX2FiaS5oCj4gKysrIGIvZHJpdmVycy9ncHUv ZHJtL2k5MTUvZ3QvdWMvYWJpL2d1Y19lcnJvcnNfYWJpLmgKPiBAQCAtOCw2ICs4LDEwIEBACj4g IAo+ICBlbnVtIGludGVsX2d1Y19yZXNwb25zZV9zdGF0dXMgewo+ICAJSU5URUxfR1VDX1JFU1BP TlNFX1NUQVRVU19TVUNDRVNTID0gMHgwLAo+ICsJSU5URUxfR1VDX1JFU1BPTlNFX05PVF9TVVBQ T1JURUQgPSAweDIwLAo+ICsJSU5URUxfR1VDX1JFU1BPTlNFX05PX0FUVFJJQlVURV9UQUJMRSA9 IDB4MjAxLAo+ICsJSU5URUxfR1VDX1JFU1BPTlNFX05PX0RFQ1JZUFRJT05fS0VZID0gMHgyMDIs Cj4gKwlJTlRFTF9HVUNfUkVTUE9OU0VfREVDUllQVElPTl9GQUlMRUQgPSAweDIwNCwKPiAgCUlO VEVMX0dVQ19SRVNQT05TRV9TVEFUVVNfR0VORVJJQ19GQUlMID0gMHhGMDAwLAo+ICB9Owo+ICAK PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjLmMgYi9k cml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF9ndWMuYwo+IGluZGV4IGYxNDdjYjM4OWEy MC4uMDE4MzlkNWViMTMwIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3Vj L2ludGVsX2d1Yy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3Vj LmMKPiBAQCAtNDA3LDEzICs0MDcsMTQgQEAgaW50IGludGVsX2d1Y19zZW5kX21taW8oc3RydWN0 IGludGVsX2d1YyAqZ3VjLCBjb25zdCB1MzIgKmFjdGlvbiwgdTMyIGxlbiwKPiAgCS8qCj4gIAkg KiBObyBHdUMgY29tbWFuZCBzaG91bGQgZXZlciB0YWtlIGxvbmdlciB0aGFuIDEwbXMuCj4gIAkg KiBGYXN0IGNvbW1hbmRzIHNob3VsZCBzdGlsbCBjb21wbGV0ZSBpbiAxMHVzLgo+ICsJICogRXhj ZXB0IGZvciB0aGUgaHdjb25maWcgdGFibGUgcXVlcnksIHdoaWNoIHRha2VzIH41MG1zLgoKSSBh c3N1bWUgdGhpcyBpcyBhIGxpbWl0YXRpb24gb2YgdGhlIHNwZWNpZmljIGZ3IHJlbGVhc2UgYW5k IHdpbGwgYmUKZml4ZWQgaW4gbmV4dCByZWxlYXNlcywgc28gbWF5YmUgd29ydGggdG8gYWRkIHNv bWUgRklYTUUgdG8gZG9uJ3QgZm9yZ2V0CnRvIGRyb3AgdGhpcyBoYWNrIG9uY2UgZncgaXMgZml4 ZWQgPwoKPiAgCSAqLwo+ICAJcmV0ID0gX19pbnRlbF93YWl0X2Zvcl9yZWdpc3Rlcl9mdyh1bmNv cmUsCj4gIAkJCQkJICAgZ3VjX3NlbmRfcmVnKGd1YywgMCksCj4gIAkJCQkJICAgSU5URUxfR1VD X01TR19UWVBFX01BU0ssCj4gIAkJCQkJICAgSU5URUxfR1VDX01TR19UWVBFX1JFU1BPTlNFIDw8 Cj4gIAkJCQkJICAgSU5URUxfR1VDX01TR19UWVBFX1NISUZULAo+IC0JCQkJCSAgIDEwLCAxMCwg JnN0YXR1cyk7Cj4gKwkJCQkJICAgMTAsIDEwMCwgJnN0YXR1cyk7Cj4gIAkvKiBJZiBHdUMgZXhw bGljaXRseSByZXR1cm5lZCBhbiBlcnJvciwgY29udmVydCBpdCB0byAtRUlPICovCj4gIAlpZiAo IXJldCAmJiAhSU5URUxfR1VDX01TR19JU19SRVNQT05TRV9TVUNDRVNTKHN0YXR1cykpCj4gIAkJ cmV0ID0gLUVJTzsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50 ZWxfZ3VjLmggYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF9ndWMuaAo+IGluZGV4 IDRhYmM1OWY2ZjNjZC4uODMwN2RlNDYzYWYwIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2d0L3VjL2ludGVsX2d1Yy5oCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3Qv dWMvaW50ZWxfZ3VjLmgKPiBAQCAtMTIsNiArMTIsNyBAQAo+ICAjaW5jbHVkZSAiaW50ZWxfZ3Vj X2N0LmgiCj4gICNpbmNsdWRlICJpbnRlbF9ndWNfbG9nLmgiCj4gICNpbmNsdWRlICJpbnRlbF9n dWNfcmVnLmgiCj4gKyNpbmNsdWRlICJpbnRlbF9ndWNfaHdjb25maWcuaCIKPiAgI2luY2x1ZGUg ImludGVsX3VjX2Z3LmgiCj4gICNpbmNsdWRlICJpOTE1X3V0aWxzLmgiCj4gICNpbmNsdWRlICJp OTE1X3ZtYS5oIgo+IEBAIC0yNyw2ICsyOCw3IEBAIHN0cnVjdCBpbnRlbF9ndWMgewo+ICAJc3Ry dWN0IGludGVsX3VjX2Z3IGZ3Owo+ICAJc3RydWN0IGludGVsX2d1Y19sb2cgbG9nOwo+ICAJc3Ry dWN0IGludGVsX2d1Y19jdCBjdDsKPiArCXN0cnVjdCBpbnRlbF9ndWNfaHdjb25maWcgaHdjb25m aWc7Cj4gIAo+ICAJLyogaW50ZWxfZ3VjX3JlY3YgaW50ZXJydXB0IHJlbGF0ZWQgc3RhdGUgKi8K PiAgCXNwaW5sb2NrX3QgaXJxX2xvY2s7Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3Qv dWMvaW50ZWxfZ3VjX2h3Y29uZmlnLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAw MDAwMDAwMDAwMC4uOTM4YjFlZGI3MjA5Cj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMv Z3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5jCj4gQEAgLTAsMCArMSwxNjcg QEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IE1JVAo+ICsvKgo+ICsgKiBDb3B5cmln aHQgwqkgMjAyMCBJbnRlbCBDb3Jwb3JhdGlvbgoKMjAyMQoKPiArICovCj4gKwo+ICsjaW5jbHVk ZSAiZ3QvaW50ZWxfZ3QuaCIKPiArI2luY2x1ZGUgImd0L2ludGVsX2h3Y29uZmlnX3R5cGVzLmgi Cj4gKyNpbmNsdWRlICJpOTE1X2Rydi5oIgo+ICsjaW5jbHVkZSAiaTkxNV9tZW1jcHkuaCIKPiAr I2luY2x1ZGUgImludGVsX2d1Y19od2NvbmZpZy5oIgo+ICsKPiArc3RhdGljCj4gK2lubGluZSBz dHJ1Y3QgaW50ZWxfZ3VjICpod2NvbmZpZ190b19ndWMoc3RydWN0IGludGVsX2d1Y19od2NvbmZp ZyAqaHdjb25maWcpCgpubyBuZWVkIHRvIChiYWRseSkgc3BsaXQgbGluZXMsIGNvbHVtbiBsaW1p dCBpcyAxMDAKCj4gK3sKPiArCXJldHVybiBjb250YWluZXJfb2YoaHdjb25maWcsIHN0cnVjdCBp bnRlbF9ndWMsIGh3Y29uZmlnKTsKPiArfQo+ICsKPiArLyoqCgp0aGlzIGRvZXNuJ3QgbG9va3Mg bGlrZSBrZXJuZWwgZG9jCgo+ICsgKiBHdUMgaGFzIGEgYmxvYiBjb250YWluaW5nIGhhcmR3YXJl IGNvbmZpZ3VyYXRpb24gaW5mb3JtYXRpb24gKGh3Y29uZmlnKS4KCmxhdGVyIHlvdSBhcmUgdXNp bmcgIkhXQ29uZmlnIiBuYW1lCgo+ICsgKiBUaGlzIGlzIGZvcm1hdHRlZCBhcyBhIHNpbXBsZSBh bmQgZmxleGlibGUgS0xWIChLZXkvTGVuZ3RoL1ZhbHVlKSB0YWJsZS4KCmluIGZpbGUgaW50ZWxf aHdjb25maWdfdHlwZXMuaCB0aGVyZSB3YXMgc3RhdGVtZW50CgkiSW50ZWwgZGV2aWNlcyBwcm92 aWRlIGEgS0xWIC4uLiIKc28gbWF5YmUgd2UgZG9uJ3QgaGF2ZSB0byByZXBlYXQgdGhhdCBoZXJl IGFuZCBhbHNvIGp1c3QgbW92ZSBleGFtcGxlCmJlbG93IHRvIC5oIHdoZXJlIHdob2xlIGNvbmNl cHQgY291bGQgYmUgZXhwbGFpbmVkIGluIG9uZSBwbGFjZS4KCj4gKyAqCj4gKyAqIEZvciBleGFt cGxlLCBhIG1pbmltYWwgdmVyc2lvbiBjb3VsZCBiZToKPiArICogICBlbnVtIGRldmljZV9hdHRy IHsKPiArICogICAgIEFUVFJfU09NRV9WQUxVRSA9IDAsCj4gKyAqICAgICBBVFRSX1NPTUVfTUFT SyAgPSAxLAo+ICsgKiAgIH07Cj4gKyAqCj4gKyAqICAgc3RhdGljIGNvbnN0IHUzMiBod2NvbmZp Z1tdID0gewo+ICsgKiAgICAgQVRUUl9TT01FX1ZBTFVFLAo+ICsgKiAgICAgMSwJCS8vIFZhbHVl IExlbmd0aCBpbiBEV29yZHMKPiArICogICAgIDgsCQkvLyBWYWx1ZQo+ICsgKgo+ICsgKiAgICAg QVRUUl9TT01FX01BU0ssCj4gKyAqICAgICAzLAo+ICsgKiAgICAgMHgwMEZGRkZGRkZGLCAweEZG RkZGRkZGLCAweEZGMDAwMDAwLAo+ICsgKiAgIH07Cj4gKyAqCj4gKyAqIFRoZSBhdHRyaWJ1dGUg aWRzIGFyZSBkZWZpbmVkIGluIGEgaGFyZHdhcmUgc3BlYy4gVGhlIGN1cnJlbnQgbGlzdCBhcwo+ ICsgKiBrbm93biB0byB0aGUgaTkxNSBkcml2ZXIgY2FuIGJlIGZvdW5kIGluIGk5MTUvZ3QvaW50 ZWxfZ3VjX2h3Y29uZmlnX3R5cGVzLmgKPiArICovCj4gKwo+ICtzdGF0aWMgaW50IF9fZ3VjX2Fj dGlvbl9nZXRfaHdjb25maWcoc3RydWN0IGludGVsX2d1Y19od2NvbmZpZyAqaHdjb25maWcsCgph bGwgb3RoZXIgImd1Y19hY3Rpb24iIGZ1bmN0aW9ucyB0YWtlIGRpcmVjdGx5ICJndWMiIGFzIHBh cmFtCgo+ICsJCQkJICAgICB1MzIgZ2d0dF9vZmZzZXQsIHUzMiBnZ3R0X3NpemUpCj4gK3sKPiAr CXN0cnVjdCBpbnRlbF9ndWMgKmd1YyA9IGh3Y29uZmlnX3RvX2d1Yyhod2NvbmZpZyk7Cj4gKwlz dHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqaTkxNSA9IGd1Y190b19ndChndWMpLT5pOTE1Owo+ICsJ dTMyIGFjdGlvbltdID0gewo+ICsJCUlOVEVMX0dVQ19BQ1RJT05fR0VUX0hXQ09ORklHLAo+ICsJ CWdndHRfb2Zmc2V0LAo+ICsJCWdndHRfc2l6ZSwKPiArCQkoSU5URUxfREVWSUQoaTkxNSkgPDwg MTYpIHwgSU5URUxfUkVWSUQoaTkxNSksCj4gKwl9Owo+ICsJaW50IHJldDsKPiArCj4gKwlyZXQg PSBpbnRlbF9ndWNfc2VuZF9tbWlvKGd1YywgYWN0aW9uLCBBUlJBWV9TSVpFKGFjdGlvbiksIE5V TEwsIDApOwoKd2h5IHRoaXMgaXMgb3ZlciBNTUlPPwphcyB5b3UgbmVlZCB0byBwYXNzIEdHVFQg dGhlbiBDVEIgaXMgYWxzbyBhbHJlYWR5IGF2YWlsYWJsZS4uLgoKPiArCWlmIChyZXQgPT0gLUVO WElPKQo+ICsJCXJldHVybiAtRU5PRU5UOwo+ICsKPiArCWlmICghZ2d0dF9zaXplICYmICFyZXQp Cj4gKwkJcmV0ID0gLUVJTlZBTDsKPiArCj4gKwlyZXR1cm4gcmV0Owo+ICt9Cj4gKwo+ICtzdGF0 aWMgaW50IGd1Y19od2NvbmZpZ19kaXNjb3Zlcl9zaXplKHN0cnVjdCBpbnRlbF9ndWNfaHdjb25m aWcgKmh3Y29uZmlnKQo+ICt7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCS8qIFNlbmRpbmcgYSBxdWVy eSB3aXRoIHRvbyBzbWFsbCBhIHRhYmxlIHdpbGwgcmV0dXJuIHRoZSBzaXplIG9mIHRoZSB0YWJs ZSAqLwoKbGlrZWx5OiAiU2VuZGluZyBhIHF1ZXJ5IHdpdGggemVybyBidWZmZXIgc2l6ZSB3aWxs IHJldHVybiAuLiIKCj4gKwlyZXQgPSBfX2d1Y19hY3Rpb25fZ2V0X2h3Y29uZmlnKGh3Y29uZmln LCAwLCAwKTsKPiArCWlmIChyZXQgPCAwKQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJaHdjb25m aWctPnNpemUgPSByZXQ7Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIGludCBndWNf aHdjb25maWdfZmlsbF9idWZmZXIoc3RydWN0IGludGVsX2d1Y19od2NvbmZpZyAqaHdjb25maWcp Cj4gK3sKPiArCXN0cnVjdCBpbnRlbF9ndWMgKmd1YyA9IGh3Y29uZmlnX3RvX2d1Yyhod2NvbmZp Zyk7Cj4gKwlzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqaTkxNSA9IGd1Y190b19ndChndWMpLT5p OTE1Owo+ICsJdTMyIGdndHRfb2Zmc2V0Owo+ICsJaW50IHJldDsKPiArCXN0cnVjdCBpOTE1X3Zt YSAqdm1hOwo+ICsJdm9pZCAqdmFkZHI7CgpuaXQ6IHNvbWUgd291bGQgcHJlZmVyIHRoaXMgb3Jk ZXI6CgoJc3RydWN0IGk5MTVfdm1hICp2bWE7Cgl1MzIgZ2d0dF9vZmZzZXQ7Cgl2b2lkICp2YWRk cjsKCWludCByZXQ7Cgo+ICsKPiArCUdFTV9CVUdfT04oIWh3Y29uZmlnLT5zaXplKTsKPiArCj4g KwlyZXQgPSBpbnRlbF9ndWNfYWxsb2NhdGVfYW5kX21hcF92bWEoZ3VjLCBod2NvbmZpZy0+c2l6 ZSwgJnZtYSwgJnZhZGRyKTsKPiArCWlmIChyZXQpIHsKPiArCQlkcm1fZXJyKCZpOTE1LT5kcm0s ICJIV0NvbmZpZzogRmFpbGVkIHRvIGFsbG9jYXRlIGJ1ZmZlcjogJWQhXG4iLCByZXQpOwoKd2Ug Y2FuIGZhaWwgaW4gbWFueSBkaWZmZXJlbnQgd2F5cywgYWxzbyBpbiBvdGhlciBwbGFjZXMsIHdo eSBvbmx5IHRoaXMKY2FzZSBoYXMgZGVkaWNhdGVkIGVycm9yIG1lc3NhZ2UgPwoKbml0OiB0byBi ZSBtb3JlIGZyaWVuZGx5IHdlIGNhbiBwcmludCBlcnJvciBjb2RlIHdpdGggJXBlCgo+ICsJCXJl dHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJZ2d0dF9vZmZzZXQgPSBpbnRlbF9ndWNfZ2d0dF9vZmZz ZXQoZ3VjLCB2bWEpOwo+ICsKPiArCXJldCA9IF9fZ3VjX2FjdGlvbl9nZXRfaHdjb25maWcoaHdj b25maWcsIGdndHRfb2Zmc2V0LCBod2NvbmZpZy0+c2l6ZSk7Cj4gKwlpZiAocmV0ID49IDApCj4g KwkJbWVtY3B5KGh3Y29uZmlnLT5wdHIsIHZhZGRyLCBod2NvbmZpZy0+c2l6ZSk7CgpkbyB5b3Ug cGxhbiB0byBhZGQgc29tZSB2YWxpZGF0aW9uIG9mIHRoZSByZWNlaXZlZCBrbHZzID8KbGlrZSBp ZiBsYXN0IG9uZSBpcyBub3QgdHJ1bmNhdGVkID8KCmFuZCB0byAoZGVidWcpIHByaW50IGl0IGFu eXdoZXJlID8KCmFuZCBtYXliZSB0byBhZGQgdG8gZXJyb3IgY2FwdHVyZT8KCj4gKwo+ICsJaTkx NV92bWFfdW5waW5fYW5kX3JlbGVhc2UoJnZtYSwgSTkxNV9WTUFfUkVMRUFTRV9NQVApOwo+ICsK PiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBib29sIGhhc190YWJsZShzdHJ1Y3Qg ZHJtX2k5MTVfcHJpdmF0ZSAqaTkxNSkKPiArewo+ICsJaWYgKElTX0FMREVSTEFLRV9QKGk5MTUp KSB7Cj4gKwkJaWYgKElTX0FETFBfR1RfU1RFUChpOTE1LCBTVEVQX0EwLCBTVEVQX0EwKSkKPiAr CQkJcmV0dXJuIDA7Cj4gKwo+ICsJCXJldHVybiAxOwoKbml0OiB0aGlzIGNvdWxkIGJlIHNpbmds ZSBsaW5lOgoKCXJldHVybiAhSVNfQURMUF9HVF9TVEVQKGk5MTUsIFNURVBfQTAsIFNURVBfQTAp OwoKYW5kIG1heWJlIGFkZCBmZXcgd29yZHMgYXMgaW4gY29tbWl0IG1lc3NhZ2UgeW91IHNhaWQg YWxsIEFEUC1QIGhhdmUgaXQKCj4gKwl9Cj4gKwo+ICsJcmV0dXJuIDA7CgpzaW5jZSB5b3UgZGVm aW5lZCBmdW5jdGlvbiBhcyByZXR1cm5pbmcgYm9vbCwgdGhlbiB1c2UgdHJ1ZS9mYWxzZQoKPiAr fQo+ICsKPiArLyoqCj4gKyAqIGludGVsX2d1Y19od2NvbmZpZ19pbml0IC0gSW5pdGlhbGl6ZSB0 aGUgSFdDb25maWcKPiArICoKPiArICogUmV0cmlldmUgdGhlIEhXQ29uZmlnIHRhYmxlIGZyb20g dGhlIEd1QyBhbmQgc2F2ZSBpdCBhd2F5IGluIGEgbG9jYWwgbWVtb3J5Cj4gKyAqIGFsbG9jYXRp b24uIEl0IGNhbiB0aGVuIGJlIHF1ZXJpZWQgb24gZGVtYW5kIGJ5IG90aGVyIHVzZXJzIGxhdGVy IG9uLgo+ICsgKi8KPiAraW50IGludGVsX2d1Y19od2NvbmZpZ19pbml0KHN0cnVjdCBpbnRlbF9n dWNfaHdjb25maWcgKmh3Y29uZmlnKQo+ICt7Cj4gKwlzdHJ1Y3QgaW50ZWxfZ3VjICpndWMgPSBo d2NvbmZpZ190b19ndWMoaHdjb25maWcpOwo+ICsJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmk5 MTUgPSBndWNfdG9fZ3QoZ3VjKS0+aTkxNTsKPiArCWludCByZXQ7Cj4gKwo+ICsJaWYgKCFoYXNf dGFibGUoaTkxNSkpCj4gKwkJcmV0dXJuIDA7Cj4gKwo+ICsJcmV0ID0gZ3VjX2h3Y29uZmlnX2Rp c2NvdmVyX3NpemUoaHdjb25maWcpOwo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0Owo+ICsK PiArCWh3Y29uZmlnLT5wdHIgPSBrbWFsbG9jKGh3Y29uZmlnLT5zaXplLCBHRlBfS0VSTkVMKTsK PiArCWlmICghaHdjb25maWctPnB0cikgewo+ICsJCWh3Y29uZmlnLT5zaXplID0gMDsKPiArCQly ZXR1cm4gLUVOT01FTTsKPiArCX0KPiArCj4gKwlyZXQgPSBndWNfaHdjb25maWdfZmlsbF9idWZm ZXIoaHdjb25maWcpOwo+ICsJaWYgKHJldCA8IDApIHsKPiArCQlrZnJlZShod2NvbmZpZy0+cHRy KTsKPiArCQlod2NvbmZpZy0+c2l6ZSA9IDA7Cj4gKwkJaHdjb25maWctPnB0ciA9IE5VTEw7Cj4g KwkJcmV0dXJuIHJldDsKCm1heWJlIHVzZSBvbmlvbiBjbGVhbnVwID8KCj4gKwl9Cj4gKwo+ICsJ cmV0dXJuIDA7Cj4gK30KPiArCj4gKy8qKgo+ICsgKiBpbnRlbF9ndWNfaHdjb25maWdfZmluaSAt IEZpbmFsaXplIHRoZSBIV0NvbmZpZwo+ICsgKgo+ICsgKiBGcmVlIHVwIHRoZSBtZW1vcnkgYWxs b2NhdGlvbiBob2xkaW5nIHRoZSB0YWJsZS4KPiArICovCj4gK3ZvaWQgaW50ZWxfZ3VjX2h3Y29u ZmlnX2Zpbmkoc3RydWN0IGludGVsX2d1Y19od2NvbmZpZyAqaHdjb25maWcpCj4gK3sKPiArCWlm ICghaHdjb25maWctPnNpemUpCj4gKwkJcmV0dXJuOwoKbm90IG5lZWRlZCwga2ZyZWUgd2lsbCB3 b3JrIHdpdGggbnVsbAoKPiArCj4gKwlrZnJlZShod2NvbmZpZy0+cHRyKTsKPiArCWh3Y29uZmln LT5zaXplID0gMDsKPiArCWh3Y29uZmlnLT5wdHIgPSBOVUxMOwo+ICt9Cj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5oIGIvZHJpdmVy cy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjX2h3Y29uZmlnLmgKPiBuZXcgZmlsZSBtb2Rl IDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMC4uOTFlOTZkODhkNzEzCj4gLS0tIC9kZXYvbnVs bAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19od2NvbmZpZy5o Cj4gQEAgLTAsMCArMSwxOSBAQAo+ICsvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogTUlUICov Cj4gKy8qCj4gKyAqIENvcHlyaWdodCDCqSAyMDIwIEludGVsIENvcnBvcmF0aW9uCgoyMDIxCgo+ ICsgKi8KPiArCj4gKyNpZm5kZWYgX0lOVEVMX0dVQ19IV0NPTkZJR19IXwo+ICsjZGVmaW5lIF9J TlRFTF9HVUNfSFdDT05GSUdfSF8KPiArCj4gKyNpbmNsdWRlIDxsaW51eC90eXBlcy5oPgo+ICsK PiArc3RydWN0IGludGVsX2d1Y19od2NvbmZpZyB7Cj4gKwl1MzIgc2l6ZTsKCnNpemUgaW4gYnl0 ZXMgb3IgZHdvcmRzID8KCj4gKwl2b2lkICpwdHI7CgpuaXQ6IGFzIHRoaXMgaXMgcHRyIHRvIGts diBkd29yZHMsIG1heWJlOgoKCXUzMiAqa2xzOwoKPiArfTsKPiArCj4gK2ludCBpbnRlbF9ndWNf aHdjb25maWdfaW5pdChzdHJ1Y3QgaW50ZWxfZ3VjX2h3Y29uZmlnICpod2NvbmZpZyk7Cj4gK3Zv aWQgaW50ZWxfZ3VjX2h3Y29uZmlnX2Zpbmkoc3RydWN0IGludGVsX2d1Y19od2NvbmZpZyAqaHdj b25maWcpOwo+ICsKPiArI2VuZGlmIC8qIF9JTlRFTF9HVUNfSFdDT05GSUdfSF8gKi8KPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfdWMuYyBiL2RyaXZlcnMv Z3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX3VjLmMKPiBpbmRleCA2ZDhiOTIzMzIxNGUuLmIyODk2 OTNmOTc2NyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF91 Yy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfdWMuYwo+IEBAIC01 MDIsNiArNTAyLDEwIEBAIHN0YXRpYyBpbnQgX191Y19pbml0X2h3KHN0cnVjdCBpbnRlbF91YyAq dWMpCj4gIAo+ICAJaW50ZWxfaHVjX2F1dGgoaHVjKTsKPiAgCj4gKwlyZXQgPSBpbnRlbF9ndWNf aHdjb25maWdfaW5pdCgmZ3VjLT5od2NvbmZpZyk7Cj4gKwlpZiAocmV0KQo+ICsJCWdvdG8gZXJy X2xvZ19jYXB0dXJlOwo+ICsKPiAgCWlmIChpbnRlbF91Y191c2VzX2d1Y19zdWJtaXNzaW9uKHVj KSkKPiAgCQlpbnRlbF9ndWNfc3VibWlzc2lvbl9lbmFibGUoZ3VjKTsKPiAgCj4gQEAgLTU1Miw2 ICs1NTYsOCBAQCBzdGF0aWMgdm9pZCBfX3VjX2ZpbmlfaHcoc3RydWN0IGludGVsX3VjICp1YykK PiAgCWlmIChpbnRlbF91Y191c2VzX2d1Y19zdWJtaXNzaW9uKHVjKSkKPiAgCQlpbnRlbF9ndWNf c3VibWlzc2lvbl9kaXNhYmxlKGd1Yyk7Cj4gIAo+ICsJaW50ZWxfZ3VjX2h3Y29uZmlnX2Zpbmko Jmd1Yy0+aHdjb25maWcpOwo+ICsKPiAgCV9fdWNfc2FuaXRpemUodWMpOwo+ICB9Cj4gIAo+IApf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZngg bWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK