From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nadav Amit <nadav.amit@gmail.com>
Subject: Re: x86: Question regarding the reset value of LINT0
Date: Wed, 8 Apr 2015 19:59:44 +0300
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References: <2B474EEE-85C9-47C3-89FF-C56754CFEC0D@gmail.com> <55255AF2.2070706@siemens.com>
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To: Jan Kiszka <jan.kiszka@siemens.com>,
	Avi Kivity <avi.kivity@gmail.com>
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Jan Kiszka <jan.kiszka@siemens.com> wrote:

> On 2015-04-08 18:40, Nadav Amit wrote:
>> Hi,
>>=20
>> I would appreciate if someone explains the reason for enabling LINT0=
 during
>> APIC reset. This does not correspond with Intel SDM Figure 10-8: =E2=
=80=9CLocal
>> Vector Table=E2=80=9D that says all LVT registers are reset to 0x100=
00.
>>=20
>> In kvm_lapic_reset, I see:
>>=20
>> 	apic_set_reg(apic, APIC_LVT0,
>> 		SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
>>=20
>> Which is actually pretty similar to QEMU=E2=80=99s apic_reset_common=
:
>>=20
>>    if (bsp) {
>>        /*
>>         * LINT0 delivery mode on CPU #0 is set to ExtInt at initiali=
zation
>>         * time typically by BIOS, so PIC interrupt can be delivered =
to the
>>         * processor when local APIC is enabled.
>>         */
>>        s->lvt[APIC_LVT_LINT0] =3D 0x700;
>>    }
>>=20
>> Yet, in both cases, I miss the point - if it is typically done by th=
e BIOS,
>> why does QEMU or KVM enable it?
>>=20
>> BTW: KVM seems to run fine without it, and I think setting it causes=
 me
>> problems in certain cases.
>=20
> I suspect it has some historic BIOS backgrounds. Already tried to fin=
d
> more information in the git logs of both code bases? Or something tha=
t
> indicates of SeaBIOS or BochsBIOS once didn't do this initialization?
Thanks. I found no indication of such thing.

QEMU=E2=80=99s commit message (0e21e12bb311c4c1095d0269dc2ef81196ccb60a=
) says:

    Don't route PIC interrupts through the local APIC if the local APIC
    config says so. By Ari Kivity.
   =20
Maybe Avi Kivity knows this guy.

Regards,
Nadav