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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?dFFIbzJUaTQySi9naVdQaGFnNGoxSGFpa2g4eFlpU1JYS2ZMUFp6UDZ5S0Zu?= =?utf-8?B?bzRJQlVGQVRkNHpwWnYzQldRSG9od0VOaDlqTjUvVXZmc3lzcE4zVzE3bk0v?= =?utf-8?B?bU8wbENDU0kvUktGQ2RTcjFuQ1ZEVkpMdENkZGhlYWh6TmplV2hkNFJBWWF0?= =?utf-8?B?WWE1NVFhTEpEckE2ZTcyak5yaDlmWFFhclMrL0k2aGZLVTRsTnZQaExXOC94?= =?utf-8?B?aEExY1JVR09FSGVUT3dzRmV6R3A3V04xb01Zb2V2bWFWOHMwYmprNHVIWVBt?= =?utf-8?B?Y3ZvYVVuU0R3eVJwQ1NSQkFENXYrYzVRSVBtM0RRcDhxT1MwK2VZKzB0dnlt?= =?utf-8?B?eUxoMzcrVUEzNmtBTVlnbFFqMUg2UWhOY0NvT2d1aGxSMlNQY1BWZkV5ZUE4?= =?utf-8?B?M1BYNFlSSEpRUDVLdU5JRms1N1N6aUx5ZmNjRllUbERiVkVWd1diVnlWamFj?= =?utf-8?B?aWQrdDlCVWRjOEtMWXJXbFVQZWZER0pKT1ZLZEhRLzN5Q3VGd2FxWlpYVkhL?= =?utf-8?B?dGYwa3ovdkZGVlptWUF4NEFJYVRTR1Z0NWI0TnBybDhKakR2VjdOemVDUWpH?= =?utf-8?B?RE1zWGxEd0p5RGFIT1Q0WDBqa2pGOE5uaGk3MjhBS3FsV05rRThqTVI1akdZ?= =?utf-8?B?Z3h6MFM1SWdNdWZSMjd3Z3VuWC9oMGJ4dzhxbGZia240KzhCL0ZTNTUzL2Z1?= =?utf-8?B?MmdScW45a1FKaTI5bzRzQzJBSFBKbCs1TzRBN2tIbk55WitFVWVUYkYrYkp3?= =?utf-8?B?UVdSUWFuMHlERGM0ZGF1dVJXQ1NhbVJ1amxTQlFuelhPNkVIbkYwVWRyUDVK?= =?utf-8?B?TUh0VkQ5UjhtVnZ6WDR0STBsQUdZeUt2SU5pTkxrL0hHMGpqUHpiVmlTR1Vk?= =?utf-8?B?Q3VwSks2eXozQU0vTmtMYnRkQW1Ca0xDa1VBdFFwa3krekFXREw0TUV6Q1Vs?= =?utf-8?B?L2kyR0pJTDFLYll5ZXhRSHlrMFBGOFRuTUFOQWorVGRIalFPWmtkaExiUGNz?= =?utf-8?B?YTZ0SVcxaWhVcVNEL20zNXNmR0xObUtPSkhvclkzcGhRTys3Z1ZiV09UN1Fj?= =?utf-8?B?SWpWT0pyMmRBcHlCS0RMRzY2dncrSjNuWGVmeFJsYU9WK004Y05yT1h5NEs3?= =?utf-8?B?T1ZsdGlEaDZiQ2dTVUdUZFVUZHZMSmZZeHdpdm5YeU5BZGcvYWlYR0FhYStX?= =?utf-8?B?NmxFTENNYVBQazFYY2xjbExENkxOUEp4aDZIaTVkNnFMeFhrWG95UkIzdTFq?= =?utf-8?B?UncwSUhSeFA4azlWRTNzWHZPRnlRWGVNNTJpQllFTU8yejBBMldWMElMNG84?= =?utf-8?B?bEpIbFloL05KejNVQ3UvTzdLOTFhVlRDdWFyVjBkTEJBR25hd2p3QjZIS2l4?= =?utf-8?B?L2NHcWhWUFRNcE5sZUtrZ1FmZEQ0dUdOdXlGQjJRMkZiL3JOVEo5cy9VcjdD?= =?utf-8?B?aXN3VFFRT3JLMVJNY0RFOEM2RVYyb29VZmx0bk1XQ2gyUzE0K3RMc094bXVI?= =?utf-8?B?WGZ1aXlYSE1mOGRGb05HWkIxaVlNdG1MenlDaUxkZ3g0VEZ3K1FKWmpNcHYv?= =?utf-8?B?T25CSVhnM2xkaWxKTCtZRHo3ZUFWWmoxZVVMck54WUJkVERqZjI5RFBja1dN?= =?utf-8?B?enIzQ2s5T3pERjJBcDQzczVESmJVMytqaXFSM0NMQU5LaWxLVHJpd2tiOExT?= =?utf-8?B?bjFlc3VlZGpxSWYrek9XZGp2YzVmT0RRWjlPRi9pUUJNWklHcHR1Y2pDQzRy?= =?utf-8?Q?thQrBz9M8a7Lv2I91O17waZFzctT57I3qwbqENl?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: d628c139-df86-4d36-cd8a-08d9468e35ad X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2021 06:11:25.1547 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3NYJTziu6M1FiGn9qhWlee2S5FRP4gcqdMCSMpkdkez3yXxtQzNt0c+kzF6fr1GaaG4iO7TptT+2o4y42ndyDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3535 On 13.07.2021 18:33, Julien Grall wrote: > Hi, > > On 13/07/2021 17:27, Jan Beulich wrote: >> On 13.07.2021 18:15, Julien Grall wrote: >>> On 13/07/2021 16:52, Jan Beulich wrote: >>>> On 13.07.2021 16:33, Julien Grall wrote: >>>>> On 13/07/2021 15:23, Jan Beulich wrote: >>>>>> On 13.07.2021 16:19, Julien Grall wrote: >>>>>>> On 13/07/2021 15:14, Jan Beulich wrote: >>>>>>>>> And I don't think it should be named XC_PAGE_*, but rather XEN_PAGE_*. >>>>>>>> >>>>>>>> Even that doesn't seem right to me, at least in principle. There shouldn't >>>>>>>> be a build time setting when it may vary at runtime. IOW on Arm I think a >>>>>>>> runtime query to the hypervisor would be needed instead. >>>>>>> >>>>>>> Yes, we want to be able to use the same userspace/OS without rebuilding >>>>>>> to a specific hypervisor page size. >>>>>>> >>>>>>>> And thinking >>>>>>>> even more generally, perhaps there could also be mixed (base) page sizes >>>>>>>> in use at run time, so it may need to be a bit mask which gets returned. >>>>>>> >>>>>>> I am not sure to understand this. Are you saying the hypervisor may use >>>>>>> at the same time different page size? >>>>>> >>>>>> I think so, yes. And I further think the hypervisor could even allow its >>>>>> guests to do so. >>>>> >>>>> This is already the case on Arm. We need to differentiate between the >>>>> page size used by the guest and the one used by Xen for the stage-2 page >>>>> table (what you call EPT on x86). >>>>> >>>>> In this case, we are talking about the page size used by the hypervisor >>>>> to configure the stage-2 page table >>>>> >>>>>> There would be a distinction between the granularity at >>>>>> which RAM gets allocated and the granularity at which page mappings (RAM >>>>>> or other) can be established. Which yields an environment which I'd say >>>>>> has no clear "system page size". >>>>> >>>>> I don't quite understand why you would allocate and etablish the memory >>>>> with a different page size in the hypervisor. Can you give an example? >>>> >>>> Pages may get allocated in 16k chunks, but there may be ways to map >>>> 4k MMIO regions, 4k grants, etc. Due to the 16k allocation granularity >>>> you'd e.g. still balloon pages in and out at 16k granularity. >>> Right, 16KB is a multiple of 4KB, so a guest could say "Please allocate >>> a contiguous chunk of 4 4KB pages". >>> >>> From my understanding, you are suggesting to tell the guest that we >>> "support 4KB, 16KB, 64KB...". However, it should be sufficient to say >>> "we support 4KB and all its multiple". >> >> No - in this case it could legitimately expect to be able to balloon >> out a single 4k page. Yet that's not possible with 16k allocation >> granularity. > > I am confused... why would you want to put such restriction? IOW, what > are you trying to protect against? Protect? It may simply be that the most efficient page size is 16k. Hence accounting of pages may be done at 16k granularity. IOW there then is one struct page_info per 16k page. How would you propose a guest would alloc/free 4k pages in such a configuration? Jan