From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH 09/14] KVM: PPC: Add generic single register ioctls Date: Mon, 19 Dec 2011 13:58:32 +0100 Message-ID: <0709DF5F-8C3B-4B40-A91A-D7CD41854AF8@suse.de> References: <1320047596-20577-1-git-send-email-agraf@suse.de> <1320047596-20577-10-git-send-email-agraf@suse.de> <20111110160536.GD7554@amt.cnet> <4EBC00A6.6040803@suse.de> <20111110173505.GA13747@amt.cnet> <35750AAB-B919-4F7B-B60E-C4ADE9124048@suse.de> <20111123124708.GA13448@amt.cnet> Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Cc: kvm-ppc@vger.kernel.org, kvm list , Avi Kivity To: Marcelo Tosatti Return-path: In-Reply-To: <20111123124708.GA13448@amt.cnet> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 23.11.2011, at 13:47, Marcelo Tosatti wrote: > On Wed, Nov 16, 2011 at 12:45:45AM +0100, Alexander Graf wrote: >> >> On 10.11.2011, at 18:35, Marcelo Tosatti wrote: >> >>> On Thu, Nov 10, 2011 at 05:49:42PM +0100, Alexander Graf wrote: >>>>>> Documentation/virtual/kvm/api.txt | 47 ++++++++++++++++++++++++++++++++++ >>>>>> arch/powerpc/kvm/powerpc.c | 51 +++++++++++++++++++++++++++++++++++++ >>>>>> include/linux/kvm.h | 32 +++++++++++++++++++++++ >>>>>> 3 files changed, 130 insertions(+), 0 deletions(-) >>>>> I don't see the benefit of this generalization, the current structure where >>>>> context information is hardcoded in the data transmitted works well. >>>> >>>> Well, unfortunately it doesn't work quite as well for us because we >>>> are a much more evolving platform. Also, there are a lot of edges >>>> and corners of the architecture that simply aren't implemented in >>>> KVM as of now. I want to have something extensible enough so we >>>> don't break the ABI along the way. >>> >>> You still have to agree on format between userspace and kernel, right? >>> If either party fails to conform to that, you're doomed. >> >> Yes, but we can shove registers back and forth without allocating 8kb of ram each time. If all we need to do is poke one register, we poke one register. If we poke 10, we poke the 10 we need to touch. >> >>> The problem with two interfaces is potential ambiguity: is >>> register X implemented through KVM_GET_ONE_REG and also through >>> KVM_GET_XYZ_REGISTER_SET ? If its accessible by two interfaces, what is >>> the register writeback order? Is there a plan to convert, etc. >> >> Why writeback order? Register modification operations should always happen from the same thread the vCPU would run on at the end of the day, no? > > Yes, but there is a specified order which the registers must be written > back, in case there are dependencies between them (the QEMU x86's code > does its best to document these dependencies). > > All i'm saying is that two distinct interfaces make it potentially > confusing for the programmer. That said, its up to Avi to decide. I still don't fully understand. You pass in a list of register modifications. The same would happen from guest code. You have a code stream of register modifications. They should both end up calling the same functions in the kernel at the end of the day with the same order. If you call XYZ_REGISTER_SET and then GET_ONE_REG, you get the same the guest would get. If it's difficult to implement for specific registers then just don't implement those with the ONE_REG interface. You're not forced to implement all registers with either interface - it's mostly a nicely extensible interface for architectures that evolve quite a bit with people implementing things only partially and then later realizing what's missing :). In other words, it should work great for us ppc folks and I'm fairly sure the ARM guys will appreciate it too. X86 is rather stable and well-exploited, so I can see how it doesn't make sense to use it there. Alex From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Mon, 19 Dec 2011 12:58:32 +0000 Subject: Re: [PATCH 09/14] KVM: PPC: Add generic single register ioctls Message-Id: <0709DF5F-8C3B-4B40-A91A-D7CD41854AF8@suse.de> List-Id: References: <1320047596-20577-1-git-send-email-agraf@suse.de> <1320047596-20577-10-git-send-email-agraf@suse.de> <20111110160536.GD7554@amt.cnet> <4EBC00A6.6040803@suse.de> <20111110173505.GA13747@amt.cnet> <35750AAB-B919-4F7B-B60E-C4ADE9124048@suse.de> <20111123124708.GA13448@amt.cnet> In-Reply-To: <20111123124708.GA13448@amt.cnet> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Marcelo Tosatti Cc: kvm-ppc@vger.kernel.org, kvm list , Avi Kivity On 23.11.2011, at 13:47, Marcelo Tosatti wrote: > On Wed, Nov 16, 2011 at 12:45:45AM +0100, Alexander Graf wrote: >> >> On 10.11.2011, at 18:35, Marcelo Tosatti wrote: >> >>> On Thu, Nov 10, 2011 at 05:49:42PM +0100, Alexander Graf wrote: >>>>>> Documentation/virtual/kvm/api.txt | 47 ++++++++++++++++++++++++++++++++++ >>>>>> arch/powerpc/kvm/powerpc.c | 51 +++++++++++++++++++++++++++++++++++++ >>>>>> include/linux/kvm.h | 32 +++++++++++++++++++++++ >>>>>> 3 files changed, 130 insertions(+), 0 deletions(-) >>>>> I don't see the benefit of this generalization, the current structure where >>>>> context information is hardcoded in the data transmitted works well. >>>> >>>> Well, unfortunately it doesn't work quite as well for us because we >>>> are a much more evolving platform. Also, there are a lot of edges >>>> and corners of the architecture that simply aren't implemented in >>>> KVM as of now. I want to have something extensible enough so we >>>> don't break the ABI along the way. >>> >>> You still have to agree on format between userspace and kernel, right? >>> If either party fails to conform to that, you're doomed. >> >> Yes, but we can shove registers back and forth without allocating 8kb of ram each time. If all we need to do is poke one register, we poke one register. If we poke 10, we poke the 10 we need to touch. >> >>> The problem with two interfaces is potential ambiguity: is >>> register X implemented through KVM_GET_ONE_REG and also through >>> KVM_GET_XYZ_REGISTER_SET ? If its accessible by two interfaces, what is >>> the register writeback order? Is there a plan to convert, etc. >> >> Why writeback order? Register modification operations should always happen from the same thread the vCPU would run on at the end of the day, no? > > Yes, but there is a specified order which the registers must be written > back, in case there are dependencies between them (the QEMU x86's code > does its best to document these dependencies). > > All i'm saying is that two distinct interfaces make it potentially > confusing for the programmer. That said, its up to Avi to decide. I still don't fully understand. You pass in a list of register modifications. The same would happen from guest code. You have a code stream of register modifications. They should both end up calling the same functions in the kernel at the end of the day with the same order. If you call XYZ_REGISTER_SET and then GET_ONE_REG, you get the same the guest would get. If it's difficult to implement for specific registers then just don't implement those with the ONE_REG interface. You're not forced to implement all registers with either interface - it's mostly a nicely extensible interface for architectures that evolve quite a bit with people implementing things only partially and then later realizing what's missing :). In other words, it should work great for us ppc folks and I'm fairly sure the ARM guys will appreciate it too. X86 is rather stable and well-exploited, so I can see how it doesn't make sense to use it there. Alex