From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31DA6C4167B for ; Mon, 7 Dec 2020 10:39:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E74C923339 for ; Mon, 7 Dec 2020 10:39:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726249AbgLGKjA (ORCPT ); Mon, 7 Dec 2020 05:39:00 -0500 Received: from foss.arm.com ([217.140.110.172]:46632 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726195AbgLGKjA (ORCPT ); Mon, 7 Dec 2020 05:39:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 854FF1042; Mon, 7 Dec 2020 02:38:14 -0800 (PST) Received: from [10.57.63.221] (unknown [10.57.63.221]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3AF4F3F66B; Mon, 7 Dec 2020 02:38:13 -0800 (PST) Subject: Re: [PATCH v5] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM To: Qi Liu , Mathieu Poirier Cc: mike.leach@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com References: <1606397670-15657-1-git-send-email-liuqi115@huawei.com> <20201204185551.GB1424711@xps15> <448eb009-da3e-b918-984d-cf563a64f31d@huawei.com> From: Suzuki K Poulose Message-ID: <07243eef-dbcf-6500-a66b-5c0e1689ece9@arm.com> Date: Mon, 7 Dec 2020 10:38:09 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <448eb009-da3e-b918-984d-cf563a64f31d@huawei.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/7/20 2:08 AM, Qi Liu wrote: > Hi Mathieu, > > On 2020/12/5 2:55, Mathieu Poirier wrote: >> On Thu, Nov 26, 2020 at 09:34:30PM +0800, Qi Liu wrote: >>> The ETM device can't keep up with the core pipeline when cpu core >>> is at full speed. This may cause overflow within core and its ETM. >>> This is a common phenomenon on ETM devices. >>> >>> On HiSilicon Hip08 platform, a specific feature is added to set >>> core pipeline. So commit rate can be reduced manually to avoid ETM >>> overflow. >>> >>> Signed-off-by: Qi Liu >>> --- >>> Change since v1: >>> - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON >>> to keep specific feature off platforms which don't use it. >>> Change since v2: >>> - remove some unused variable. >>> Change since v3: >>> - use read/write_sysreg_s() to access register. >>> Change since v4: >>> - rename the call back function to a more generic name, and fix some >>> compile warnings. >>> >>> drivers/hwtracing/coresight/Kconfig | 9 +++ >>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 88 ++++++++++++++++++++++ >>> drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++ >>> 3 files changed, 105 insertions(+) >>> >>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >>> index c119824..1cc3601 100644 >>> --- a/drivers/hwtracing/coresight/Kconfig >>> +++ b/drivers/hwtracing/coresight/Kconfig >>> @@ -110,6 +110,15 @@ config CORESIGHT_SOURCE_ETM4X >>> To compile this driver as a module, choose M here: the >>> module will be called coresight-etm4x. >>> >>> +config ETM4X_IMPDEF_FEATURE >>> + bool "Control overflow impdef support in CoreSight ETM 4.x driver " >>> + depends on CORESIGHT_SOURCE_ETM4X >>> + help >>> + This control provides overflow implement define for CoreSight >>> + ETM 4.x tracer module which could not reduce commit race >>> + automatically, and could avoid overflow within ETM tracer module >>> + and its cpu core. >>> + >>> config CORESIGHT_STM >>> tristate "CoreSight System Trace Macrocell driver" >>> depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index abd706b..fcee27a 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -3,6 +3,7 @@ >>> * Copyright (c) 2014, The Linux Foundation. All rights reserved. >>> */ >>> >>> +#include >>> #include >>> #include >>> #include >>> @@ -28,7 +29,9 @@ >>> #include >>> #include >>> #include >>> + >>> #include >>> +#include >>> #include >>> #include >>> >>> @@ -103,6 +106,87 @@ struct etm4_enable_arg { >>> int rc; >>> }; >>> >>> +#ifdef CONFIG_ETM4X_IMPDEF_FEATURE >>> + >>> +#define HISI_HIP08_AMBA_ID 0x000b6d01 >>> +#define ETM4_AMBA_MASK 0xfffff >>> +#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000 >> >> Here bit 12 and 13 are cleared but in etm4_hisi_config_core_commit() only bit 12 >> is set - is this intentional? What is bit 13 for? >> > bit 12 and 13 are used together to set core-commit, 2'b00 means cpu is at full speed, > 2'b01, 2'b10, 2'b11 means reduce the speed of cpu pipeline, and 2'b01 means speed is > reduced to minimum value. So bit 12 and 13 should be cleared together in > etm4_hisi_config_core_commit(). Please could you document this in the function. > > Qi > >>> +#define HISI_HIP08_CORE_COMMIT_SHIFT 12 >>> +#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) >>> + >>> +struct etm4_arch_features { >>> + void (*arch_callback)(bool enable); >>> +}; >>> + >>> +static bool etm4_hisi_match_pid(unsigned int id) >>> +{ >>> + return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; >>> +} >>> + >>> +static void etm4_hisi_config_core_commit(bool enable) >>> +{ >>> + u64 val; >>> + >>> + val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); >>> + val &= ~HISI_HIP08_CORE_COMMIT_CLEAR; >>> + val |= enable << HISI_HIP08_CORE_COMMIT_SHIFT; I would use the explicitly masked values when you update a register. With the above: Reviewed-by: Suzuki K Poulose From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CF35C4361B for ; Mon, 7 Dec 2020 10:39:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0246E23339 for ; Mon, 7 Dec 2020 10:39:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0246E23339 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RUehOif47er2NCPqqdI5lV4P3sbhCyoKKfcKEMbwHe4=; b=hKhFvlHDRA5k0NAy89Ej3xn8Q 4dfgkWDLSQ9pY3oCqCJQcJvim5jGL1Zf10kXiqoeoXhNl/98jJ3/FFugzJVNAEwF/ZQw+5Vttngph 0SJsnEaeKjSYm93eD+OHrnxVm96/jbekiao4k65d40/rDv0bxXu6rShYP9tVyiUBX4n7WKhoiWOof hSBZETVU67o16r0fP3S+K1Z/npDniJxGuVZZpr+/DFj/PKxxHIlpRxwCbaYmbHwbf7n2vcMgI3Fal 438jKDdzmyoGISjCNvA4eEyIMwEluMjnzdeiE2KpaGWKiOAcgqPLilelyBJLxyoOzLZmplYzfvgi3 8HCUEujBQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmDuU-0007Ai-54; Mon, 07 Dec 2020 10:38:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmDuQ-0007AD-TD for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2020 10:38:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 854FF1042; Mon, 7 Dec 2020 02:38:14 -0800 (PST) Received: from [10.57.63.221] (unknown [10.57.63.221]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3AF4F3F66B; Mon, 7 Dec 2020 02:38:13 -0800 (PST) Subject: Re: [PATCH v5] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM To: Qi Liu , Mathieu Poirier References: <1606397670-15657-1-git-send-email-liuqi115@huawei.com> <20201204185551.GB1424711@xps15> <448eb009-da3e-b918-984d-cf563a64f31d@huawei.com> From: Suzuki K Poulose Message-ID: <07243eef-dbcf-6500-a66b-5c0e1689ece9@arm.com> Date: Mon, 7 Dec 2020 10:38:09 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <448eb009-da3e-b918-984d-cf563a64f31d@huawei.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_053823_090468_94EF3C1F X-CRM114-Status: GOOD ( 22.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linuxarm@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/7/20 2:08 AM, Qi Liu wrote: > Hi Mathieu, > > On 2020/12/5 2:55, Mathieu Poirier wrote: >> On Thu, Nov 26, 2020 at 09:34:30PM +0800, Qi Liu wrote: >>> The ETM device can't keep up with the core pipeline when cpu core >>> is at full speed. This may cause overflow within core and its ETM. >>> This is a common phenomenon on ETM devices. >>> >>> On HiSilicon Hip08 platform, a specific feature is added to set >>> core pipeline. So commit rate can be reduced manually to avoid ETM >>> overflow. >>> >>> Signed-off-by: Qi Liu >>> --- >>> Change since v1: >>> - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON >>> to keep specific feature off platforms which don't use it. >>> Change since v2: >>> - remove some unused variable. >>> Change since v3: >>> - use read/write_sysreg_s() to access register. >>> Change since v4: >>> - rename the call back function to a more generic name, and fix some >>> compile warnings. >>> >>> drivers/hwtracing/coresight/Kconfig | 9 +++ >>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 88 ++++++++++++++++++++++ >>> drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++ >>> 3 files changed, 105 insertions(+) >>> >>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >>> index c119824..1cc3601 100644 >>> --- a/drivers/hwtracing/coresight/Kconfig >>> +++ b/drivers/hwtracing/coresight/Kconfig >>> @@ -110,6 +110,15 @@ config CORESIGHT_SOURCE_ETM4X >>> To compile this driver as a module, choose M here: the >>> module will be called coresight-etm4x. >>> >>> +config ETM4X_IMPDEF_FEATURE >>> + bool "Control overflow impdef support in CoreSight ETM 4.x driver " >>> + depends on CORESIGHT_SOURCE_ETM4X >>> + help >>> + This control provides overflow implement define for CoreSight >>> + ETM 4.x tracer module which could not reduce commit race >>> + automatically, and could avoid overflow within ETM tracer module >>> + and its cpu core. >>> + >>> config CORESIGHT_STM >>> tristate "CoreSight System Trace Macrocell driver" >>> depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index abd706b..fcee27a 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -3,6 +3,7 @@ >>> * Copyright (c) 2014, The Linux Foundation. All rights reserved. >>> */ >>> >>> +#include >>> #include >>> #include >>> #include >>> @@ -28,7 +29,9 @@ >>> #include >>> #include >>> #include >>> + >>> #include >>> +#include >>> #include >>> #include >>> >>> @@ -103,6 +106,87 @@ struct etm4_enable_arg { >>> int rc; >>> }; >>> >>> +#ifdef CONFIG_ETM4X_IMPDEF_FEATURE >>> + >>> +#define HISI_HIP08_AMBA_ID 0x000b6d01 >>> +#define ETM4_AMBA_MASK 0xfffff >>> +#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000 >> >> Here bit 12 and 13 are cleared but in etm4_hisi_config_core_commit() only bit 12 >> is set - is this intentional? What is bit 13 for? >> > bit 12 and 13 are used together to set core-commit, 2'b00 means cpu is at full speed, > 2'b01, 2'b10, 2'b11 means reduce the speed of cpu pipeline, and 2'b01 means speed is > reduced to minimum value. So bit 12 and 13 should be cleared together in > etm4_hisi_config_core_commit(). Please could you document this in the function. > > Qi > >>> +#define HISI_HIP08_CORE_COMMIT_SHIFT 12 >>> +#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) >>> + >>> +struct etm4_arch_features { >>> + void (*arch_callback)(bool enable); >>> +}; >>> + >>> +static bool etm4_hisi_match_pid(unsigned int id) >>> +{ >>> + return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; >>> +} >>> + >>> +static void etm4_hisi_config_core_commit(bool enable) >>> +{ >>> + u64 val; >>> + >>> + val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); >>> + val &= ~HISI_HIP08_CORE_COMMIT_CLEAR; >>> + val |= enable << HISI_HIP08_CORE_COMMIT_SHIFT; I would use the explicitly masked values when you update a register. With the above: Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel