From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Date: Fri, 12 Apr 2019 14:32:24 +0000 Message-ID: <07f2ae212b046534cd00202b13a2cfd42d8b518a.camel@intel.com> References: <20190411230815.30083-1-rodrigo.vivi@intel.com> <060a5c9af847cfdc0f855066b2b318d56b4cd91a.camel@intel.com> <20190411235147.GA24830@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0741797194==" Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 855F589993 for ; Fri, 12 Apr 2019 14:32:26 +0000 (UTC) In-Reply-To: <20190411235147.GA24830@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Vivi, Rodrigo" Cc: "intel-gfx@lists.freedesktop.org" , "De Marchi, Lucas" List-Id: intel-gfx@lists.freedesktop.org --===============0741797194== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-U1ZKqUdQydiOsb+GJEog" --=-U1ZKqUdQydiOsb+GJEog Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2019-04-11 at 16:51 -0700, Rodrigo Vivi wrote: > On Thu, Apr 11, 2019 at 04:16:41PM -0700, Souza, Jose wrote: > > On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote: > > > From: Bob Paauwe > > >=20 > > > Most of the conditional code for ICELAKE also applies to > > > ELKHARTLAKE > > > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now. > > >=20 > > > v2: - Rename commit (Jose) > > > - Include a wm workaround (Jose and Lucas) > > > - Include display core init (Jose and Lucas) > > >=20 > > > Cc: Jos=C3=A9 Roberto de Souza > > > Cc: Lucas De Marchi > > > Signed-off-by: Bob Paauwe > > > Signed-off-by: Rodrigo Vivi > > > --- > > > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++--- > > > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++---- > > > 3 files changed, 10 insertions(+), 10 deletions(-) > > >=20 > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index 8e826a6ab62e..7357bddf9ad9 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct > > > intel_crtc_state > > > *cstate, > > > memset(&wm->wm[level], 0, sizeof(wm- > > > > wm[level])); > > > =20 > > > /* > > > - * Wa_1408961008:icl > > > + * Wa_1408961008:icl, ehl > > > * Underruns with WM1+ disabled > > > */ > > > - if (IS_ICELAKE(dev_priv) && > > > + if (IS_GEN(dev_priv, 11) && > > > level =3D=3D 1 && wm->wm[0].plane_en) { > > > wm->wm[level].plane_res_b =3D wm- > > > > wm[0].plane_res_b; > > > wm->wm[level].plane_res_l =3D wm- > > > > wm[0].plane_res_l; > > > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct > > > drm_i915_private *dev_priv) > > > */ > > > void intel_init_clock_gating_hooks(struct drm_i915_private > > > *dev_priv) > > > { > > > - if (IS_ICELAKE(dev_priv)) > > > + if (IS_GEN(dev_priv, 11)) > > > dev_priv->display.init_clock_gating =3D > > > icl_init_clock_gating; > > > else if (IS_CANNONLAKE(dev_priv)) > > > dev_priv->display.init_clock_gating =3D > > > cnl_init_clock_gating; > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > > > b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > index 3107a742d8ad..fcd388e8978b 100644 > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct > > > drm_i915_private *dev_priv) > > > * The enabling order will be from lower to higher indexed > > > wells, > > > * the disabling order is reversed. > > > */ > > > - if (IS_ICELAKE(dev_priv)) { > > > + if (IS_GEN(dev_priv, 11)) { > > > err =3D set_power_wells(power_domains, icl_power_wells); > > > } else if (IS_CANNONLAKE(dev_priv)) { > > > err =3D set_power_wells(power_domains, cnl_power_wells); > > > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct > > > drm_i915_private *i915, bool resume) > > > =20 > > > power_domains->initializing =3D true; > > > =20 > > > - if (IS_ICELAKE(i915)) { > > > + if (INTEL_GEN(i915) >=3D 11) { > > > icl_display_core_init(i915, resume); > > > } else if (IS_CANNONLAKE(i915)) { > > > cnl_display_core_init(i915, resume); > > > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct > > > drm_i915_private *i915, > > > intel_power_domains_verify_state(i915); > > > } > > > =20 > > > - if (IS_ICELAKE(i915)) > > > + if (IS_GEN(i915, 11)) > >=20 > > To be consistent with init: if (INTEL_GEN(i915) >=3D 11) >=20 > hmmm... I tried to keep power well stuff not using this > greater-than behaviour on purpose... Because so far all > platforms had different wells, besides gen9_bc group of course... >=20 > But even display_10 glk and cnl are different on display wells :/ I guess you are talking about different things, I'm talking about the icl_display_core_uninit() call. if (INTEL_GEN(i915) >=3D 11) { icl_display_core_init(i915, resume); if (IS_GEN(i915, 11)) icl_display_core_uninit(i915); And for core_init/uninit we are able to share the sequence between several platforms of the same GEN. >=20 > > Other than that: > >=20 > > Reviewed-by: Jos=C3=A9 Roberto de Souza > >=20 > > > icl_display_core_uninit(i915); > > > else if (IS_CANNONLAKE(i915)) > > > cnl_display_core_uninit(i915); > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c > > > b/drivers/gpu/drm/i915/intel_workarounds.c > > > index a04dbc58ec1c..c0977036db79 100644 > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct > > > intel_engine_cs *engine) > > > =20 > > > wa_init_start(wal, "context"); > > > =20 > > > - if (IS_ICELAKE(i915)) > > > + if (IS_GEN(i915, 11)) > > > icl_ctx_workarounds_init(engine); > > > else if (IS_CANNONLAKE(i915)) > > > cnl_ctx_workarounds_init(engine); > > > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct > > > drm_i915_private > > > *i915, struct i915_wa_list *wal) > > > static void > > > gt_init_workarounds(struct drm_i915_private *i915, struct > > > i915_wa_list *wal) > > > { > > > - if (IS_ICELAKE(i915)) > > > + if (IS_GEN(i915, 11)) > > > icl_gt_workarounds_init(i915, wal); > > > else if (IS_CANNONLAKE(i915)) > > > cnl_gt_workarounds_init(i915, wal); > > > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct > > > intel_engine_cs *engine) > > > =20 > > > wa_init_start(w, "whitelist"); > > > =20 > > > - if (IS_ICELAKE(i915)) > > > + if (IS_GEN(i915, 11)) > > > icl_whitelist_build(w); > > > else if (IS_CANNONLAKE(i915)) > > > cnl_whitelist_build(w); > > > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal) > > > { > > > struct drm_i915_private *i915 =3D engine->i915; > > > =20 > > > - if (IS_ICELAKE(i915)) { > > > + if (IS_GEN(i915, 11)) { > > > /* This is not an Wa. Enable for better image quality > > > */ > > > wa_masked_en(wal, > > > _3D_CHICKEN3, >=20 >=20 --=-U1ZKqUdQydiOsb+GJEog Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlywoXcACgkQVenbO/mO Wknaxwf/R2NkkfKEyIKqjj8mrwPsbzPE3aFVFUH/BLEBWMUWGj4n7285Vmh62glX o1JnhInNMOXUnAFNhLtPS3/MLEGztVo+VCOz5W3vUu+BBKepC2pvxM85q4tVVLVk NrKA0coIT68Im7rrTRd3589N2L+486A6sM0Oz/WvZEh6MAlfIdx4mCM8KfRIZ8s5 n77B/c/Ujjm+6rqpq2zoyLBbB/+qw5WMlD3MBGgvUt5/+g1bT5TXS9APS6k5yMOR kGgmheYiBzr2ZwO9WEcrGwX89vFbD5Sr2D6F1+5qyCx8INNl80wkGFA3trNc2K45 vMXrA63tT3v0kRA7kpQfAmnyqNsRUA== =HTlI -----END PGP SIGNATURE----- --=-U1ZKqUdQydiOsb+GJEog-- --===============0741797194== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============0741797194==--