From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:48727) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFC9y-0001p4-0N for qemu-devel@nongnu.org; Sat, 13 Apr 2019 02:29:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hFC9x-0008Oi-2y for qemu-devel@nongnu.org; Sat, 13 Apr 2019 02:29:05 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:44803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hFC9w-0008OA-Mn for qemu-devel@nongnu.org; Sat, 13 Apr 2019 02:29:05 -0400 Received: by mail-pl1-x642.google.com with SMTP id g12so6116778pll.11 for ; Fri, 12 Apr 2019 23:29:04 -0700 (PDT) References: <20190411100836.646-1-david@redhat.com> <20190411100836.646-42-david@redhat.com> From: Richard Henderson Message-ID: <0871b6f8-6073-4311-78a5-4772817a009e@linaro.org> Date: Fri, 12 Apr 2019 20:28:53 -1000 MIME-Version: 1.0 In-Reply-To: <20190411100836.646-42-david@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v1 41/41] s390x/tcg: Implement VECTOR TEST UNDER MASK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Hildenbrand , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Cornelia Huck , Thomas Huth , Richard Henderson On 4/11/19 12:08 AM, David Hildenbrand wrote: > +void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env, > + uint32_t desc) > +{ > + S390Vector tmp; > + > + s390_vec_and(&tmp, v1, v2); > + if (s390_vec_is_zero(&tmp)) { > + /* Selected bits all zeros; or all mask bits zero */ > + env->cc_op = 0; > + } else if (s390_vec_equal(&tmp, v2)) { > + /* Selected bits all ones */ > + env->cc_op = 3; > + } else { > + /* Selected bits a mix of zeros and ones */ > + env->cc_op = 1; > + } > +} Reviewed-by: Richard Henderson However, if you return this value, then you can do DEF_HELPER_FLAGS_4(gvec_vtm, TCG_CALL_NO_RWG_SE, i32, cptr, cptr) static DisasJumpType op_vtm(DisasContext *s, DisasOps *o) { TCGv_ptr p1 = tcg_temp_new_ptr(); TCGv_ptr p2 = tcg_temp_new_ptr(); tcg_gen_addi_ptr(p1, cpu_env, vec_full_reg_offset(get_field(s->fields, v1))); tcg_gen_addi_ptr(p2, cpu_env, vec_full_reg_offset(get_field(s->fields, v2))); gen_helper_gvec_vtm(cc_op, p1, p2); tcg_temp_free_ptr(p1); tcg_temp_free_ptr(p2); set_cc_static(s); return DISAS_NEXT; } Perhaps it doesn't matter though, since use of vtm probably implies a jump, which implies end of TB, which means that registers are going to get saved to backing store anyway. r~