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Sat, 15 Jan 2022 15:31:24 +0000 (GMT) From: "Alim Akhtar" To: "'Rob Herring'" List-Id: Cc: "'linux-arm-kernel'" , , "'SoC Team'" , "'linux-clk'" , , "'Olof Johansson'" , "'Linus Walleij'" , "'Catalin Marinas'" , "'Krzysztof Kozlowski'" , "'Sylwester Nawrocki'" , "'linux-samsung-soc'" , "'Pankaj Dubey'" , , "'Arjun K V'" , "'Aswani Reddy'" , "'Ajay Kumar'" , "'Sriranjani P'" , "'Chandrasekar R'" , "'Shashank Prashar'" In-Reply-To: Subject: RE: [PATCH 14/23] arm64: dts: fsd: Add initial device tree support Date: Sat, 15 Jan 2022 21:01:24 +0530 Message-ID: <08ba01d80a24$f79a88f0$e6cf9ad0$@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIO4TNY4CmXUn6BI0nWbR2hr69QagKuNmZ/AcRhnYYBgiKLY6vG4Thw Content-Language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA02TeVATZxjG/TbZTWAm7Rpg+ARH6DogYMFEQvohR50RMSozxKo9rDO4AzuB kstsoB4MZTi0ImIVqyUjoCKowAglUGOoFhFbLUg5FG1LiwcO96EggwWlCYst//3e45n3fb5D yBMPE27CBK2RMWhpNUU48n+46evj3973hJZkdgei+tEbfHThkpWPGsy1AjRamgNQUWMLjr4f nsLQiZkLGKp+2omj5zl/4+jxwCeow3qaQN/9dh1Dvz4YJ9C52gkBMrVacJR1rVGAbg4dxFGh pQCgpw9mCPTn0GV8rbOiorACKExpRwhFddkhQtHV+SOhMJ//SnHvdjquyK0pA4o36QUCxXj1 MqXDjsTQeIaOYwyejDZWF5egVYVRm7fGrIsJkkuk/tJg9AHlqaU1TBgVEaX0j0xQ25xRnsm0 OsmWUtIsS60KDzXokoyMZ7yONYZRjD5OrZfpA1hawyZpVQFaxrhGKpGsDrI17kqMn62K0+e/ wfZM3w1JA5X3QTZwEEJSBnuPPyGygaNQTNYB+PpyL+CCFwC+zOrBuWAcwDt1Lby3kompNAFX sAI4kNstsBfEZD+A5kyJnQnSH1qKDxB2diZ9YPHglTkBj2wjYO3YcdxecCC3wBvFNZidncjN MGvQPJfnk16wPOvu3IIiMhiO9oxhHC+Gd/J7+HbmkSth6dnB+Y084atnpTg3LBJml57ncT2u sP9W49xgSOY5wH+aO/icIAL2vj5EcOwEB36pEXDsBsdHrtnyQhsnwhxrIJdOgSWFP89LP4T1 907z7S080hdWWldxo96BR6Z7ME4pgl8fEHPdXjBj5P680h0eO3wY51gBb/3egn8D3jMtMGZa YMy0wIDp/2FnAL8MLGH0rEbFsEH61Vrmy//uO1anqQZz795vkwU8fjQW0AAwIWgAUMijnEVH Dd20WBRH793HGHQxhiQ1wzaAINtpH+O5ucTqbB9Ha4yRyoIlMrlcLgsOlEspV1GTqooWkyra yCQyjJ4xvNVhQge3NOz6imf6geTlm8JDSppfMusnP2r02L6zO299ZsNP1iVVsm2tFdNFbdH7 J0sqG9dkTHxrLNr9mXAb4+LVIhopZsr/eN6x87ZTyqCLuws5I/P+/GJu5ZjL7ETEhr9SfeXJ EwWLK/JbplL7T+lDpF2XlqUz0WOnvBctj/aLal8qwJuuvDD5TnqE7mDNZQ+HVpLeF1t3mVyp fSkHT1a+r/ziqlPh0t0fF4AzD8s3yqNivUevllgySkKjzj56tWU7O7uuLdLiPC7t60vYeqJ+ xblU9y6s4FPHjEUq3KM50b1TYhbs3Rjre1KS0T68592iOnH42vAgZ2xDqynPJ7g718mk9DYb 9muaKD4bT0v9eAaW/hftCtjigAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA02ReUiTYRzHed6977t3A+n1CJ9mdIyyMNK0hKdD6SB7zYIOSMrChr2ouU15 t7LEcEVTXKYWYfaWmlqzpnnMrGVqtVloUHaY6zJTV/OqKWZomcRcgf994Hv8vvCjBB7vcQkV r1SznFIml5Ji/I5FOn/5y74e2Qr7GEIPHY9wVHazHkfm2johcuizACpqfk6gmm/jGLowWYYh Y28HgUayPhGoeyASva6/QqL8tiYMPbWOkqik7ocQ8S9MBNI2NguRZSiDQIWmAoB6rZMk+jBU Saz3YioKKwDDa86SjNGQSTIfOxpIpvZaGtPecopgsm8bADN1qkDIjBrn7RDtE687xMrjj7Jc QOhBcdxURg2ZND6CHauyVGAakNUKdEBEQXoV/DGuEeqAmPKgTQAaLnX+E3ygtSZX6GJPeHPK /s9kBzCvzTEtkPRyaCpNJ53sRS+FpYN3p00CupOETzLvA1dCi8EW3RWB0yWid8JHpbcxJ3vS EVA7WEs4GacXw3Lts+nTbvRq6LANYy52h62XbLiTBfQyeLZbC/6zvnhQ4Jq3AE580ROuFWFQ p78mcHm8Yf/jZmEu8ORnVPEzqvgZVfyMyFWAG8AcNkmliFWoApOClGyyv0qmUB1RxvrHJCqM YPr9fn4m0GAY9jcDjAJmACmB1Msth+uSebgdkh1PYbnEaO6InFWZgQ+FS73dXuhaoz3oWJma TWDZJJb7r2KUSKLB2BLlguf6fQnWG+7lPmFv46pDlkgvhzt2jb4USRgOiPm+ZN+1ayL2JC5U 183SfI3/aTxJLFS2NgU9DH1Q3JmjTI5o6kmFWyeke4nvvd0XN554U4l9vmMrmfxONtxqC7Yn b94vCfjdcr6/MTGm+lf6cUlQu3Vr4Uclq2IXfTsg316WMldcrm2LVKeChFXcubFF2f1jYxeL T/tWeXblvvtUZMYVUburPqgbN0VvocJ6QiavvzNt10d5cXExze20ruhLZIdkJPDwhmAYmi6q zu9y37GNt802zvqalun9c+XaP7/PZHR5D9y7a2HDXw2d5CYi80LsBcE2ueW9cUM+bw6W4qo4 WaCfgFPJ/gIokuhDbQMAAA== X-CMS-MailID: 20220115153128epcas5p1eaf67a9a43b88d6d27bd1e46f60ecba4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122413epcas5p46cb2cafb73936c423017240f98f72845 References: <20220113121143.22280-1-alim.akhtar@samsung.com> <20220113121143.22280-15-alim.akhtar@samsung.com> >-----Original Message----- >From: Rob Herring =5Bmailto:robh+dt=40kernel.org=5D >Sent: Friday, January 14, 2022 8:16 AM >To: Alim Akhtar >Cc: linux-arm-kernel ; linux- >kernel=40vger.kernel.org; SoC Team ; linux-clk clk=40vger.kernel.org>; devicetree=40vger.kernel.org; Olof Johansson >; Linus Walleij ; Catalin Ma= rinas >; Krzysztof Kozlowski >; Sylwester Nawrocki >; linux-samsung-soc soc=40vger.kernel.org>; Pankaj Dubey ; linux- >fsd=40tesla.com; Arjun K V ; Aswani Reddy >; Ajay Kumar ; >Sriranjani P ; Chandrasekar R >; Shashank Prashar >Subject: Re: =5BPATCH 14/23=5D arm64: dts: fsd: Add initial device tree su= pport > >On Thu, Jan 13, 2022 at 6:24 AM Alim Akhtar >wrote: >> >> Add initial device tree support for =22Full Self-Driving=22 (FSD) SoC Th= is >> SoC contain three clusters of four cortex-a72 CPUs and various >> peripheral IPs. > >Please make sure you run this thru 'make dtbs_check'. Fix schema warnings = as >much as possible and all dtc warnings. If shared with Samsung, there's >probably a bit still missing. I see several warnings so I won't bother man= ually >reporting them here. > Thanks Rob for review, let me fix them in patch set v2. >> Cc: linux-fsd=40tesla.com >> Signed-off-by: Arjun K V >> Signed-off-by: Aswani Reddy >> Signed-off-by: Ajay Kumar >> Signed-off-by: Sriranjani P >> Signed-off-by: Chandrasekar R >> Signed-off-by: Shashank Prashar >> Signed-off-by: Alim Akhtar >> --- >> MAINTAINERS =7C 8 + >> arch/arm64/Kconfig.platforms =7C 6 + >> arch/arm64/boot/dts/Makefile =7C 1 + >> arch/arm64/boot/dts/tesla/Makefile =7C 3 + >> arch/arm64/boot/dts/tesla/fsd.dts =7C 140 ++++++ >> arch/arm64/boot/dts/tesla/fsd.dtsi =7C 715 >+++++++++++++++++++++++++++++ >> 6 files changed, 873 insertions(+) >> create mode 100644 arch/arm64/boot/dts/tesla/Makefile >> create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts create mode >> 100644 arch/arm64/boot/dts/tesla/fsd.dtsi >> >> diff --git a/MAINTAINERS b/MAINTAINERS index >> fb18ce7168aa..02d56909c5e2 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> =40=40 -2726,6 +2726,14 =40=40 S: Maintained >> F: Documentation/devicetree/bindings/media/tegra-cec.txt >> F: drivers/media/cec/platform/tegra/ >> >> +ARM/TESLA FSD SoC SUPPORT >> +M: Alim Akhtar >> +M: linux-fsd=40tesla.com >> +L: linux-arm-kernel=40lists.infradead.org (moderated for non-subscr= ibers) >> +L: linux-samsung-soc=40vger.kernel.org >> +S: Maintained >> +F: arch/arm64/boot/dts/tesla* >> + >> ARM/TETON BGA MACHINE SUPPORT >> M: =22Mark F. Brown=22 >> L: linux-arm-kernel=40lists.infradead.org (moderated for non-subscr= ibers) >> diff --git a/arch/arm64/Kconfig.platforms >> b/arch/arm64/Kconfig.platforms index 54e3910e8b9b..bb8a047c2359 100644 >> --- a/arch/arm64/Kconfig.platforms >> +++ b/arch/arm64/Kconfig.platforms >> =40=40 -267,6 +267,12 =40=40 config ARCH_TEGRA >> help >> This enables support for the NVIDIA Tegra SoC family. >> >> +config ARCH_TESLA_FSD >> + bool =22ARMv8 based Tesla platform=22 >> + select ARCH_EXYNOS >> + help >> + Support for ARMv8 based Tesla platforms. >> + >> config ARCH_SPRD >> bool =22Spreadtrum SoC platform=22 >> help >> diff --git a/arch/arm64/boot/dts/Makefile >> b/arch/arm64/boot/dts/Makefile index 639e01a4d855..1ba04e31a438 >100644 >> --- a/arch/arm64/boot/dts/Makefile >> +++ b/arch/arm64/boot/dts/Makefile >> =40=40 -27,6 +27,7 =40=40 subdir-y +=3D rockchip subdir-y +=3D socionex= t >> subdir-y +=3D sprd subdir-y +=3D synaptics >> +subdir-y +=3D tesla >> subdir-y +=3D ti >> subdir-y +=3D toshiba >> subdir-y +=3D xilinx >> diff --git a/arch/arm64/boot/dts/tesla/Makefile >> b/arch/arm64/boot/dts/tesla/Makefile >> new file mode 100644 >> index 000000000000..a9818cda6b08 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/Makefile >> =40=40 -0,0 +1,3 =40=40 >> +=23 SPDX-License-Identifier: GPL-2.0 >> +dtb-=24(CONFIG_ARCH_TESLA_FSD) +=3D =5C >> + fsd.dtb >> diff --git a/arch/arm64/boot/dts/tesla/fsd.dts >> b/arch/arm64/boot/dts/tesla/fsd.dts >> new file mode 100644 >> index 000000000000..e9bbd3284de9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/fsd.dts >> =40=40 -0,0 +1,140 =40=40 >> +// SPDX-License-Identifier: GPL-2.0 > >Dual license dts files please. > >> +/* >> + * Tesla FSD board device tree source >> + * >> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. >> + * https://www.samsung.com >> + * Copyright (c) 2017-2021 Tesla, Inc. >> + * https://www.tesla.com >> + */ >> + >> +/dts-v1/; >> +=23include =22fsd.dtsi=22 >> + >> +/ =7B >> + model =3D =22Tesla Full Self-Driving (FSD) SoC=22; >> + compatible =3D =22tesla,fsd=22; >> + >> + aliases =7B >> + serial0 =3D &serial_0; >> + serial1 =3D &serial_1; >> + =7D; >> + >> + chosen =7B >> + stdout-path =3D &serial_0; > >> + linux,initrd-start =3D <0xE0000000>; >> + linux,initrd-end =3D <0xE4F00000>; > >Bootloaders set these. > >> + bootargs =3D =22console=3DttySAC0,115200n8 > >Not needed with stdout-path. > >> + earlycon=3Dexynos4210,0x14180000 root=3D/dev/ram= 0 > >earlycon is a debug option. > >> + init=3D/linuxrc=22; > >init and rootfs are user settings. > >> + =7D; >> + >> + memory=4080000000 =7B >> + device_type =3D =22memory=22; >> + reg =3D <0x0 0x80000000 0x2 0x00000000>; >> + =7D; >> +=7D; >> + >> +&fin_pll =7B >> + clock-frequency =3D <24000000>; >> +=7D; >> + >> +&serial_0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&serial_1 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&clock_cmu =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&clock_imem =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&clock_peric =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&smmu_isp =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&clock_fsys0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&clock_fsys1 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&smmu_peric =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&smmu_imem =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&smmu_fsys0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_1 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_2 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_3 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_4 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_5 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_6 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&hsi2c_7 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&pwm_0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&pwm_1 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&mdma0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&mdma1 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&pdma0 =7B >> + status =3D =22okay=22; >> +=7D; >> + >> +&pdma1 =7B >> + status =3D =22okay=22; >> +=7D; >> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi >> b/arch/arm64/boot/dts/tesla/fsd.dtsi >> new file mode 100644 >> index 000000000000..47cd9f20566e >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi >> =40=40 -0,0 +1,715 =40=40 >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Tesla Full Self-Driving SoC device tree source >> + * >> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. >> + * https://www.samsung.com >> + * Copyright (c) 2017-2022 Tesla, Inc. >> + * https://www.tesla.com >> + */ >> + >> +=23include =23include >> + >> + >> +/ =7B >> + compatible =3D =22tesla,fsd=22; >> + interrupt-parent =3D <&gic>; >> + =23address-cells =3D <2>; >> + =23size-cells =3D <2>; >> + >> + aliases =7B >> + watchdog0 =3D &watchdog_0; >> + watchdog1 =3D &watchdog_1; >> + watchdog2 =3D &watchdog_2; >> + hsi2c0 =3D &hsi2c_0; >> + hsi2c1 =3D &hsi2c_1; >> + hsi2c2 =3D &hsi2c_2; >> + hsi2c3 =3D &hsi2c_3; >> + hsi2c4 =3D &hsi2c_4; >> + hsi2c5 =3D &hsi2c_5; >> + hsi2c6 =3D &hsi2c_6; >> + hsi2c7 =3D &hsi2c_7; > >Drop all these non-standard aliases. > >> + =7D; >> + >> + cpus =7B >> + =23address-cells =3D <2>; >> + =23size-cells =3D <0>; >> + >> + cpu-map =7B >> + cluster0 =7B >> + core0 =7B >> + cpu =3D <&cpucl0_0>; >> + =7D; >> + core1 =7B >> + cpu =3D <&cpucl0_1>; >> + =7D; >> + core2 =7B >> + cpu =3D <&cpucl0_2>; >> + =7D; >> + core3 =7B >> + cpu =3D <&cpucl0_3>; >> + =7D; >> + =7D; >> + >> + cluster1 =7B >> + core0 =7B >> + cpu =3D <&cpucl1_0>; >> + =7D; >> + core1 =7B >> + cpu =3D <&cpucl1_1>; >> + =7D; >> + core2 =7B >> + cpu =3D <&cpucl1_2>; >> + =7D; >> + core3 =7B >> + cpu =3D <&cpucl1_3>; >> + =7D; >> + =7D; >> + >> + cluster2 =7B >> + core0 =7B >> + cpu =3D <&cpucl2_0>; >> + =7D; >> + core1 =7B >> + cpu =3D <&cpucl2_1>; >> + =7D; >> + core2 =7B >> + cpu =3D <&cpucl2_2>; >> + =7D; >> + core3 =7B >> + cpu =3D <&cpucl2_3>; >> + =7D; >> + =7D; >> + =7D; >> + >> + /* Cluster 0 */ >> + cpucl0_0: cpu=400 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x000>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl0_1: cpu=401 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x001>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl0_2: cpu=402 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x002>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl0_3: cpu=403 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x003>; >> + enable-method =3D =22psci=22; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + /* Cluster 1 */ >> + cpucl1_0: cpu=40100 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x100>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl1_1: cpu=40101 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x101>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl1_2: cpu=40102 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x102>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl1_3: cpu=40103 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x103>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + /* Cluster 2 */ >> + cpucl2_0: cpu=40200 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x200>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl2_1: cpu=40201 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x201>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl2_2: cpu=40202 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x202>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + cpucl2_3: cpu=40203 =7B >> + device_type =3D =22cpu=22; >> + compatible =3D =22arm,cortex-a72=22; >> + reg =3D <0x0 0x203>; >> + enable-method =3D =22psci=22; >> + clock-frequency =3D <2400000000>; >> + cpu-idle-states =3D <&CPU_SLEEP>; >> + next-level-cache =3D <&L2_0>; >> + =7D; >> + >> + idle-states =7B >> + entry-method =3D =22arm,psci=22; >> + >> + CPU_SLEEP: cpu-sleep =7B >> + idle-state-name =3D =22c2=22; >> + compatible =3D =22arm,idle-state=22; >> + local-timer-stop; >> + arm,psci-suspend-param =3D <0x0010000>; >> + entry-latency-us =3D <30>; >> + exit-latency-us =3D <75>; >> + min-residency-us =3D <300>; >> + status =3D =22okay=22; >> + =7D; >> + =7D; >> + >> + L2_0: l2-cache0 =7B >> + compatible =3D =22cache=22; >> + =7D; >> + =7D; >> + >> + arm-pmu =7B >> + compatible =3D =22arm,armv8-pmuv3=22; >> + interrupts =3D , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-affinity =3D <&cpucl0_0>, <&cpucl0_1>, <&cpucl= 0_2>, >> + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_= 1>, >> + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_= 0>, >> + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_= 3>; >> + =7D; >> + >> + psci =7B >> + compatible =3D =22arm,psci=22; >> + method =3D =22smc=22; > >> + cpu_on =3D <0xC4000003>; >> + cpu_suspend =3D <0xC4000001>; >> + cpu_off =3D <0x84000002>; > >These codes are standardized since forever. Fix your firmware. > >> + =7D; >> + >> + timer =7B >> + compatible =3D =22arm,armv8-timer=22; >> + interrupts =3D , >> + , >> + , >> + ; >> + =7D; >> + >> + fin_pll: clock =7B >> + compatible =3D =22fixed-clock=22; >> + clock-output-names =3D =22fin_pll=22; >> + =23clock-cells =3D <0>; >> + =7D; >> + >> + soc: soc =7B > >soc=400 > >You should see a warning for this. > >> + compatible =3D =22simple-bus=22; >> + =23address-cells =3D <2>; >> + =23size-cells =3D <2>; >> + ranges =3D <0x0 0x0 0x0 0x0 0x0 0x18000000>; >> + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; >> + >> + gic: interrupt-controller=4010400000 =7B >> + compatible =3D =22arm,gic-v3=22; >> + =23interrupt-cells =3D <3>; >> + interrupt-controller; >> + reg =3D <0x0 0x10400000 0x0 0x10000>, /* GICD = */ >> + <0x0 0x10600000 0x0 0x200000>; /* GICR_R= D+GICR_SGI */ >> + =7D; >> + >> + smmu_isp: iommu=4012100000 =7B >> + compatible =3D =22arm,mmu-500=22; >> + reg =3D <0x0 0x12100000 0x0 0x10000>; >> + =23iommu-cells =3D <2>; >> + =23global-interrupts =3D <11>; >> + interrupts =3D = , /* Global >secure fault */ >> + , = /* Global non- >secure fault */ >> + , = /* Combined >secure interrupt */ >> + , = /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts *= / >> + , = /* for CAM_CSI >*/ >> + , = /* for CAM_DP_0 >*/ >> + , = /* for CAM_DP_1 >*/ >> + , = /* for >CAM_ISP_0 */ >> + , = /* for >CAM_ISP_1 */ >> + , = /* for >CAM_MFC_0 */ >> + , = /* for >CAM_MFC_1 */ >> + /* Per context non-secure context i= nterrupts, 0-7 >interrupts */ >> + , = /* for >CONTEXT_0 */ >> + , = /* for >CONTEXT_1 */ >> + , = /* for >CONTEXT_2 */ >> + , = /* for >CONTEXT_3 */ >> + , = /* for >CONTEXT_4 */ >> + , = /* for >CONTEXT_5 */ >> + , = /* for >CONTEXT_6 */ >> + ; = /* for >CONTEXT_7 */ >> + status =3D =22disabled=22; > >IOMMU isn't really board specific, should it really be disabled? > >> + =7D; >> + >> + smmu_imem: iommu=4010200000 =7B >> + compatible =3D =22arm,mmu-500=22; >> + reg =3D <0x0 0x10200000 0x0 0x10000>; >> + =23iommu-cells =3D <2>; >> + =23global-interrupts =3D <7>; >> + interrupts =3D = , /* Global >secure fault */ >> + , = /* Global non- >secure fault */ >> + , = /* Combined >secure interrupt */ >> + , = /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts *= / >> + , = /* for FSYS1_0 */ >> + , = /* for FSYS1_1 */ >> + , = /* for IMEM_0 >*/ >> + /* Per context non-secure context i= nterrupts, 0-3 >interrupts */ >> + , = /* for >CONTEXT_0 */ >> + , = /* for >CONTEXT_1 */ >> + , = /* for >CONTEXT_2 */ >> + ; = /* for >CONTEXT_3 */ >> + status =3D =22disabled=22; >> + =7D; >> + >> + smmu_peric: iommu=4014900000 =7B >> + compatible =3D =22arm,mmu-500=22; >> + reg =3D <0x0 0x14900000 0x0 0x10000>; >> + =23iommu-cells =3D <2>; >> + =23global-interrupts =3D <5>; >> + interrupts =3D = , /* Global >secure fault */ >> + , = /* Global non- >secure fault */ >> + , = /* Combined >secure interrupt */ >> + , = /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts *= / >> + , = /* for PERIC */ >> + /* Per context non-secure context i= nterrupts, 0-1 >interrupts */ >> + , = /* for >CONTEXT_0 */ >> + ; = /* for >CONTEXT_1 */ >> + status =3D =22disabled=22; >> + =7D; >> + >> + smmu_fsys0: iommu=4015450000 =7B >> + compatible =3D =22arm,mmu-500=22; >> + reg =3D <0x0 0x15450000 0x0 0x10000>; >> + =23iommu-cells =3D <2>; >> + =23global-interrupts =3D <5>; >> + interrupts =3D = , /* Global >secure fault */ >> + , /= * Global non- >secure fault */ >> + , /= * Combined >secure interrupt */ >> + , /= * Combined non- >secure interrupt */ >> + /* Performance counter interrupts *= / >> + , = /* for FSYS0 */ >> + /* Per context non-secure context i= nterrupts, 0-1 >interrupts */ >> + , /= * for CONTEXT_0 >*/ >> + ; /= * for CONTEXT_1 >*/ >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_cmu: clock-controller=4011C10000 =7B > >Lowercase hex for unit-addresses. > >Also, arrange nodes in address order. > >> + compatible =3D =22tesla,fsd-clock-cmu=22; >> + reg =3D <0x0 0x11C10000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22fin_pll=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_imem: clock-controller=4010010000 =7B >> + compatible =3D =22tesla,fsd-clock-imem=22; >> + reg =3D <0x0 0x10010000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>, >> + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, >> + <&clock_cmu DOUT_CMU_IMEM_ACLK>, >> + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; >> + clock-names =3D =22fin_pll=22, >> + =22dout_cmu_imem_tcuclk=22, >> + =22dout_cmu_imem_aclk=22, >> + =22dout_cmu_imem_dmaclk=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_peric: clock-controller=4014010000 =7B >> + compatible =3D =22tesla,fsd-clock-peric=22; >> + reg =3D <0x0 0x14010000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>, >> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, >> + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>= , >> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_T= BUCLK>, >> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>= , >> + <&clock_cmu >DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; >> + clock-names =3D =22fin_pll=22, >> + =22dout_cmu_pll_shared0_div4=22, >> + =22dout_cmu_peric_shared1div36=22, >> + =22dout_cmu_peric_shared0div3_tbuclk=22, >> + =22dout_cmu_peric_shared0div20=22, >> + =22dout_cmu_peric_shared1div4_dmaclk=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_fsys0: clock-controller=4015010000 =7B >> + compatible =3D =22tesla,fsd-clock-fsys0=22; >> + reg =3D <0x0 0x15010000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>, >> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, >> + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, >> + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; >> + clock-names =3D =22fin_pll=22, >> + =22dout_cmu_pll_shared0_div6=22, >> + =22dout_cmu_fsys0_shared1div4=22, >> + =22dout_cmu_fsys0_shared0div4=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_fsys1: clock-controller=4016810000 =7B >> + compatible =3D =22tesla,fsd-clock-fsys1=22; >> + reg =3D <0x0 0x16810000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>, >> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, >> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; >> + clock-names =3D =22fin_pll=22, >> + =22dout_cmu_fsys1_shared0div8=22, >> + =22dout_cmu_fsys1_shared0div4=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_mfc: clock-controller=4012810000 =7B >> + compatible =3D =22tesla,fsd-clock-mfc=22; >> + reg =3D <0x0 0x12810000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22fin_pll=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + clock_csi: clock-controller=4012610000 =7B >> + compatible =3D =22tesla,fsd-clock-cam_csi=22; >> + reg =3D <0x0 0x12610000 0x0 0x3000>; >> + =23clock-cells =3D <1>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22fin_pll=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + mdma0: mdma=4010100000 =7B >> + compatible =3D =22arm,pl330=22, =22arm,primecell= =22; >> + reg =3D <0x0 0x10100000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23dma-cells =3D <1>; >> + =23dma-channels =3D <8>; >> + =23dma-requests =3D <32>; >> + clocks =3D <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK= >; >> + clock-names =3D =22apb_pclk=22; >> + iommus =3D <&smmu_imem 0x800 0x0>; >> + status =3D =22disabled=22; >> + =7D; >> + >> + mdma1: mdma=4010110000 =7B >> + compatible =3D =22arm,pl330=22, =22arm,primecell= =22; >> + reg =3D <0x0 0x10110000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23dma-cells =3D <1>; >> + =23dma-channels =3D <8>; >> + =23dma-requests =3D <32>; >> + clocks =3D <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK= >; >> + clock-names =3D =22apb_pclk=22; >> + iommus =3D <&smmu_imem 0x801 0x0>; >> + status =3D =22disabled=22; >> + =7D; >> + >> + pdma0: pdma=4014280000 =7B >> + compatible =3D =22arm,pl330=22, =22arm,primecell= =22; >> + reg =3D <0x0 0x14280000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23dma-cells =3D <1>; >> + =23dma-channels =3D <8>; >> + =23dma-requests =3D <32>; >> + clocks =3D <&clock_peric PERIC_DMA0_IPCLKPORT_AC= LK>; >> + clock-names =3D =22apb_pclk=22; >> + iommus =3D <&smmu_peric 0x2 0x0>; >> + status =3D =22disabled=22; >> + =7D; >> + >> + pdma1: pdma=4014290000 =7B >> + compatible =3D =22arm,pl330=22, =22arm,primecell= =22; >> + reg =3D <0x0 0x14290000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23dma-cells =3D <1>; >> + =23dma-channels =3D <8>; >> + =23dma-requests =3D <32>; >> + clocks =3D <&clock_peric PERIC_DMA1_IPCLKPORT_AC= LK>; >> + clock-names =3D =22apb_pclk=22; >> + iommus =3D <&smmu_peric 0x1 0x0>; >> + status =3D =22disabled=22; >> + =7D; >> + >> + mct: mct=4010040000 =7B >> + compatible =3D =22samsung,exynos4210-mct=22; >> + reg =3D <0x0 0x10040000 0x0 0x800>; >> + interrupts =3D = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + clocks =3D <&fin_pll>, <&clock_imem IMEM_MCT_PCL= K>; >> + clock-names =3D =22fin_pll=22, =22mct=22; >> + =7D; >> + >> + serial_0: serial=4014180000 =7B >> + compatible =3D =22samsung,exynos4210-uart=22; >> + reg =3D <0x0 0x14180000 0x0 0x100>; >> + interrupts =3D = ; >> + dmas =3D <&pdma1 0>, <&pdma1 1>; >> + dma-names =3D =22tx=22, =22rx=22; >> + clocks =3D <&clock_peric PERIC_PCLK_UART0>, >> + <&clock_peric PERIC_SCLK_UART0>; >> + clock-names =3D =22uart=22, =22clk_uart_baud0=22= ; >> + status =3D =22disabled=22; >> + =7D; >> + >> + serial_1: serial=4014190000 =7B >> + compatible =3D =22samsung,exynos4210-uart=22; >> + reg =3D <0x0 0x14190000 0x0 0x100>; >> + interrupts =3D = ; >> + dmas =3D <&pdma1 2>, <&pdma1 3>; >> + dma-names =3D =22tx=22, =22rx=22; >> + clocks =3D <&clock_peric PERIC_PCLK_UART1>, >> + <&clock_peric PERIC_SCLK_UART1>; >> + clock-names =3D =22uart=22, =22clk_uart_baud0=22= ; >> + status =3D =22disabled=22; >> + =7D; >> + >> + pmu_system_controller: system-controller=4011400000 =7B >> + compatible =3D =22samsung,exynos7-pmu=22, =22sys= con=22; >> + reg =3D <0x0 0x11400000 0x0 0x5000>; >> + =7D; >> + >> + watchdog_0: watchdog=40100A0000 =7B >> + compatible =3D =22samsung,exynos7-wdt=22; >> + reg =3D <0x0 0x100A0000 0x0 0x100>; >> + interrupts =3D = ; >> + samsung,syscon-phandle =3D <&pmu_system_controll= er>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22watchdog=22; >> + interrupt-mode =3D <1>; >> + =7D; >> + >> + watchdog_1: watchdog=40100B0000 =7B >> + compatible =3D =22samsung,exynos7-wdt=22; >> + reg =3D <0x0 0x100B0000 0x0 0x100>; >> + interrupts =3D = ; >> + samsung,syscon-phandle =3D <&pmu_system_controll= er>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22watchdog=22; >> + interrupt-mode =3D <1>; >> + =7D; >> + >> + watchdog_2: watchdog=40100C0000 =7B >> + compatible =3D =22samsung,exynos7-wdt=22; >> + reg =3D <0x0 0x100C0000 0x0 0x100>; >> + interrupts =3D = ; >> + samsung,syscon-phandle =3D <&pmu_system_controll= er>; >> + clocks =3D <&fin_pll>; >> + clock-names =3D =22watchdog=22; >> + interrupt-mode =3D <1>; >> + =7D; >> + >> + pwm_0: pwm=4014100000 =7B >> + compatible =3D =22samsung,exynos4210-pwm=22; >> + reg =3D <0x0 0x14100000 0x0 0x100>; >> + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; >> + =23pwm-cells =3D <3>; >> + clocks =3D <&clock_peric PERIC_PWM0_IPCLKPORT_I_= PCLK_S0>; >> + clock-names =3D =22timers=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + pwm_1: pwm=4014110000 =7B >> + compatible =3D =22samsung,exynos4210-pwm=22; >> + reg =3D <0x0 0x14110000 0x0 0x100>; >> + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; >> + =23pwm-cells =3D <3>; >> + clocks =3D <&clock_peric PERIC_PWM1_IPCLKPORT_I_= PCLK_S0>; >> + clock-names =3D =22timers=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_0: hsi2c=4014200000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14200000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c0_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C0>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_1: hsi2c=4014210000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14210000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c1_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C1>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_2: hsi2c=4014220000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14220000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c2_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C2>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_3: hsi2c=4014230000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14230000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c3_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C3>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_4: hsi2c=4014240000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14240000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c4_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C4>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_5: hsi2c=4014250000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14250000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c5_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C5>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_6: hsi2c=4014260000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14260000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c6_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C6>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + >> + hsi2c_7: hsi2c=4014270000 =7B >> + compatible =3D =22samsung,exynos7-hsi2c=22; >> + reg =3D <0x0 0x14270000 0x0 0x1000>; >> + interrupts =3D = ; >> + =23address-cells =3D <1>; >> + =23size-cells =3D <0>; >> + pinctrl-names =3D =22default=22; >> + pinctrl-0 =3D <&hs_i2c7_bus>; >> + clocks =3D <&clock_peric PERIC_PCLK_HSI2C7>; >> + clock-names =3D =22hsi2c=22; >> + status =3D =22disabled=22; >> + =7D; >> + =7D; >> +=7D; >> -- >> 2.17.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C01EC433EF for ; Sat, 15 Jan 2022 15:33:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:References:MIME-Version:Message-ID:Date :Subject:In-Reply-To:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Sun, 16 Jan 2022 00:31:30 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20220115153128epcas5p1eaf67a9a43b88d6d27bd1e46f60ecba4~Ke2VB11lQ2352023520epcas5p1D; Sat, 15 Jan 2022 15:31:28 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220115153128epsmtrp2cf42acd00e212040137d2a4fb286cc33~Ke2U7foCB1909819098epsmtrp2m; Sat, 15 Jan 2022 15:31:28 +0000 (GMT) X-AuditID: b6c32a4a-dfbff7000000b6e6-28-61e2e8d2f3ce Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 63.09.08738.1D8E2E16; Sun, 16 Jan 2022 00:31:29 +0900 (KST) Received: from alimakhtar03 (unknown [107.122.12.5]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220115153124epsmtip29068f73df514eee36c15e1f57b8f57e0~Ke2Q2uhzQ2982429824epsmtip2q; Sat, 15 Jan 2022 15:31:24 +0000 (GMT) From: "Alim Akhtar" To: "'Rob Herring'" Cc: "'linux-arm-kernel'" , , "'SoC Team'" , "'linux-clk'" , , "'Olof Johansson'" , "'Linus Walleij'" , "'Catalin Marinas'" , "'Krzysztof Kozlowski'" , "'Sylwester Nawrocki'" , "'linux-samsung-soc'" , "'Pankaj Dubey'" , , "'Arjun K V'" , "'Aswani Reddy'" , "'Ajay Kumar'" , "'Sriranjani P'" , "'Chandrasekar R'" , "'Shashank Prashar'" In-Reply-To: Subject: RE: [PATCH 14/23] arm64: dts: fsd: Add initial device tree support Date: Sat, 15 Jan 2022 21:01:24 +0530 Message-ID: <08ba01d80a24$f79a88f0$e6cf9ad0$@samsung.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIO4TNY4CmXUn6BI0nWbR2hr69QagKuNmZ/AcRhnYYBgiKLY6vG4Thw Content-Language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA02TeVATZxjG/TbZTWAm7Rpg+ARH6DogYMFEQvohR50RMSozxKo9rDO4AzuB kstsoB4MZTi0ImIVqyUjoCKowAglUGOoFhFbLUg5FG1LiwcO96EggwWlCYst//3e45n3fb5D yBMPE27CBK2RMWhpNUU48n+46evj3973hJZkdgei+tEbfHThkpWPGsy1AjRamgNQUWMLjr4f nsLQiZkLGKp+2omj5zl/4+jxwCeow3qaQN/9dh1Dvz4YJ9C52gkBMrVacJR1rVGAbg4dxFGh pQCgpw9mCPTn0GV8rbOiorACKExpRwhFddkhQtHV+SOhMJ//SnHvdjquyK0pA4o36QUCxXj1 MqXDjsTQeIaOYwyejDZWF5egVYVRm7fGrIsJkkuk/tJg9AHlqaU1TBgVEaX0j0xQ25xRnsm0 OsmWUtIsS60KDzXokoyMZ7yONYZRjD5OrZfpA1hawyZpVQFaxrhGKpGsDrI17kqMn62K0+e/ wfZM3w1JA5X3QTZwEEJSBnuPPyGygaNQTNYB+PpyL+CCFwC+zOrBuWAcwDt1Lby3kompNAFX sAI4kNstsBfEZD+A5kyJnQnSH1qKDxB2diZ9YPHglTkBj2wjYO3YcdxecCC3wBvFNZidncjN MGvQPJfnk16wPOvu3IIiMhiO9oxhHC+Gd/J7+HbmkSth6dnB+Y084atnpTg3LBJml57ncT2u sP9W49xgSOY5wH+aO/icIAL2vj5EcOwEB36pEXDsBsdHrtnyQhsnwhxrIJdOgSWFP89LP4T1 907z7S080hdWWldxo96BR6Z7ME4pgl8fEHPdXjBj5P680h0eO3wY51gBb/3egn8D3jMtMGZa YMy0wIDp/2FnAL8MLGH0rEbFsEH61Vrmy//uO1anqQZz795vkwU8fjQW0AAwIWgAUMijnEVH Dd20WBRH793HGHQxhiQ1wzaAINtpH+O5ucTqbB9Ha4yRyoIlMrlcLgsOlEspV1GTqooWkyra yCQyjJ4xvNVhQge3NOz6imf6geTlm8JDSppfMusnP2r02L6zO299ZsNP1iVVsm2tFdNFbdH7 J0sqG9dkTHxrLNr9mXAb4+LVIhopZsr/eN6x87ZTyqCLuws5I/P+/GJu5ZjL7ETEhr9SfeXJ EwWLK/JbplL7T+lDpF2XlqUz0WOnvBctj/aLal8qwJuuvDD5TnqE7mDNZQ+HVpLeF1t3mVyp fSkHT1a+r/ziqlPh0t0fF4AzD8s3yqNivUevllgySkKjzj56tWU7O7uuLdLiPC7t60vYeqJ+ xblU9y6s4FPHjEUq3KM50b1TYhbs3Rjre1KS0T68592iOnH42vAgZ2xDqynPJ7g718mk9DYb 9muaKD4bT0v9eAaW/hftCtjigAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA02ReUiTYRzHed6977t3A+n1CJ9mdIyyMNK0hKdD6SB7zYIOSMrChr2ouU15 t7LEcEVTXKYWYfaWmlqzpnnMrGVqtVloUHaY6zJTV/OqKWZomcRcgf994Hv8vvCjBB7vcQkV r1SznFIml5Ji/I5FOn/5y74e2Qr7GEIPHY9wVHazHkfm2johcuizACpqfk6gmm/jGLowWYYh Y28HgUayPhGoeyASva6/QqL8tiYMPbWOkqik7ocQ8S9MBNI2NguRZSiDQIWmAoB6rZMk+jBU Saz3YioKKwDDa86SjNGQSTIfOxpIpvZaGtPecopgsm8bADN1qkDIjBrn7RDtE687xMrjj7Jc QOhBcdxURg2ZND6CHauyVGAakNUKdEBEQXoV/DGuEeqAmPKgTQAaLnX+E3ygtSZX6GJPeHPK /s9kBzCvzTEtkPRyaCpNJ53sRS+FpYN3p00CupOETzLvA1dCi8EW3RWB0yWid8JHpbcxJ3vS EVA7WEs4GacXw3Lts+nTbvRq6LANYy52h62XbLiTBfQyeLZbC/6zvnhQ4Jq3AE580ROuFWFQ p78mcHm8Yf/jZmEu8ORnVPEzqvgZVfyMyFWAG8AcNkmliFWoApOClGyyv0qmUB1RxvrHJCqM YPr9fn4m0GAY9jcDjAJmACmB1Msth+uSebgdkh1PYbnEaO6InFWZgQ+FS73dXuhaoz3oWJma TWDZJJb7r2KUSKLB2BLlguf6fQnWG+7lPmFv46pDlkgvhzt2jb4USRgOiPm+ZN+1ayL2JC5U 183SfI3/aTxJLFS2NgU9DH1Q3JmjTI5o6kmFWyeke4nvvd0XN554U4l9vmMrmfxONtxqC7Yn b94vCfjdcr6/MTGm+lf6cUlQu3Vr4Uclq2IXfTsg316WMldcrm2LVKeChFXcubFF2f1jYxeL T/tWeXblvvtUZMYVUburPqgbN0VvocJ6QiavvzNt10d5cXExze20ruhLZIdkJPDwhmAYmi6q zu9y37GNt802zvqalun9c+XaP7/PZHR5D9y7a2HDXw2d5CYi80LsBcE2ueW9cUM+bw6W4qo4 WaCfgFPJ/gIokuhDbQMAAA== X-CMS-MailID: 20220115153128epcas5p1eaf67a9a43b88d6d27bd1e46f60ecba4 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122413epcas5p46cb2cafb73936c423017240f98f72845 References: <20220113121143.22280-1-alim.akhtar@samsung.com> <20220113121143.22280-15-alim.akhtar@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220115_073142_933717_169AC030 X-CRM114-Status: GOOD ( 20.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org >-----Original Message----- >From: Rob Herring [mailto:robh+dt@kernel.org] >Sent: Friday, January 14, 2022 8:16 AM >To: Alim Akhtar >Cc: linux-arm-kernel ; linux- >kernel@vger.kernel.org; SoC Team ; linux-clk clk@vger.kernel.org>; devicetree@vger.kernel.org; Olof Johansson >; Linus Walleij ; Catalin Marinas >; Krzysztof Kozlowski >; Sylwester Nawrocki >; linux-samsung-soc soc@vger.kernel.org>; Pankaj Dubey ; linux- >fsd@tesla.com; Arjun K V ; Aswani Reddy >; Ajay Kumar ; >Sriranjani P ; Chandrasekar R >; Shashank Prashar >Subject: Re: [PATCH 14/23] arm64: dts: fsd: Add initial device tree support > >On Thu, Jan 13, 2022 at 6:24 AM Alim Akhtar >wrote: >> >> Add initial device tree support for "Full Self-Driving" (FSD) SoC This >> SoC contain three clusters of four cortex-a72 CPUs and various >> peripheral IPs. > >Please make sure you run this thru 'make dtbs_check'. Fix schema warnings as >much as possible and all dtc warnings. If shared with Samsung, there's >probably a bit still missing. I see several warnings so I won't bother manually >reporting them here. > Thanks Rob for review, let me fix them in patch set v2. >> Cc: linux-fsd@tesla.com >> Signed-off-by: Arjun K V >> Signed-off-by: Aswani Reddy >> Signed-off-by: Ajay Kumar >> Signed-off-by: Sriranjani P >> Signed-off-by: Chandrasekar R >> Signed-off-by: Shashank Prashar >> Signed-off-by: Alim Akhtar >> --- >> MAINTAINERS | 8 + >> arch/arm64/Kconfig.platforms | 6 + >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/tesla/Makefile | 3 + >> arch/arm64/boot/dts/tesla/fsd.dts | 140 ++++++ >> arch/arm64/boot/dts/tesla/fsd.dtsi | 715 >+++++++++++++++++++++++++++++ >> 6 files changed, 873 insertions(+) >> create mode 100644 arch/arm64/boot/dts/tesla/Makefile >> create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts create mode >> 100644 arch/arm64/boot/dts/tesla/fsd.dtsi >> >> diff --git a/MAINTAINERS b/MAINTAINERS index >> fb18ce7168aa..02d56909c5e2 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -2726,6 +2726,14 @@ S: Maintained >> F: Documentation/devicetree/bindings/media/tegra-cec.txt >> F: drivers/media/cec/platform/tegra/ >> >> +ARM/TESLA FSD SoC SUPPORT >> +M: Alim Akhtar >> +M: linux-fsd@tesla.com >> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) >> +L: linux-samsung-soc@vger.kernel.org >> +S: Maintained >> +F: arch/arm64/boot/dts/tesla* >> + >> ARM/TETON BGA MACHINE SUPPORT >> M: "Mark F. Brown" >> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) >> diff --git a/arch/arm64/Kconfig.platforms >> b/arch/arm64/Kconfig.platforms index 54e3910e8b9b..bb8a047c2359 100644 >> --- a/arch/arm64/Kconfig.platforms >> +++ b/arch/arm64/Kconfig.platforms >> @@ -267,6 +267,12 @@ config ARCH_TEGRA >> help >> This enables support for the NVIDIA Tegra SoC family. >> >> +config ARCH_TESLA_FSD >> + bool "ARMv8 based Tesla platform" >> + select ARCH_EXYNOS >> + help >> + Support for ARMv8 based Tesla platforms. >> + >> config ARCH_SPRD >> bool "Spreadtrum SoC platform" >> help >> diff --git a/arch/arm64/boot/dts/Makefile >> b/arch/arm64/boot/dts/Makefile index 639e01a4d855..1ba04e31a438 >100644 >> --- a/arch/arm64/boot/dts/Makefile >> +++ b/arch/arm64/boot/dts/Makefile >> @@ -27,6 +27,7 @@ subdir-y += rockchip subdir-y += socionext >> subdir-y += sprd subdir-y += synaptics >> +subdir-y += tesla >> subdir-y += ti >> subdir-y += toshiba >> subdir-y += xilinx >> diff --git a/arch/arm64/boot/dts/tesla/Makefile >> b/arch/arm64/boot/dts/tesla/Makefile >> new file mode 100644 >> index 000000000000..a9818cda6b08 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/Makefile >> @@ -0,0 +1,3 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +dtb-$(CONFIG_ARCH_TESLA_FSD) += \ >> + fsd.dtb >> diff --git a/arch/arm64/boot/dts/tesla/fsd.dts >> b/arch/arm64/boot/dts/tesla/fsd.dts >> new file mode 100644 >> index 000000000000..e9bbd3284de9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/fsd.dts >> @@ -0,0 +1,140 @@ >> +// SPDX-License-Identifier: GPL-2.0 > >Dual license dts files please. > >> +/* >> + * Tesla FSD board device tree source >> + * >> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. >> + * https://www.samsung.com >> + * Copyright (c) 2017-2021 Tesla, Inc. >> + * https://www.tesla.com >> + */ >> + >> +/dts-v1/; >> +#include "fsd.dtsi" >> + >> +/ { >> + model = "Tesla Full Self-Driving (FSD) SoC"; >> + compatible = "tesla,fsd"; >> + >> + aliases { >> + serial0 = &serial_0; >> + serial1 = &serial_1; >> + }; >> + >> + chosen { >> + stdout-path = &serial_0; > >> + linux,initrd-start = <0xE0000000>; >> + linux,initrd-end = <0xE4F00000>; > >Bootloaders set these. > >> + bootargs = "console=ttySAC0,115200n8 > >Not needed with stdout-path. > >> + earlycon=exynos4210,0x14180000 root=/dev/ram0 > >earlycon is a debug option. > >> + init=/linuxrc"; > >init and rootfs are user settings. > >> + }; >> + >> + memory@80000000 { >> + device_type = "memory"; >> + reg = <0x0 0x80000000 0x2 0x00000000>; >> + }; >> +}; >> + >> +&fin_pll { >> + clock-frequency = <24000000>; >> +}; >> + >> +&serial_0 { >> + status = "okay"; >> +}; >> + >> +&serial_1 { >> + status = "okay"; >> +}; >> + >> +&clock_cmu { >> + status = "okay"; >> +}; >> + >> +&clock_imem { >> + status = "okay"; >> +}; >> + >> +&clock_peric { >> + status = "okay"; >> +}; >> + >> +&smmu_isp { >> + status = "okay"; >> +}; >> + >> +&clock_fsys0 { >> + status = "okay"; >> +}; >> + >> +&clock_fsys1 { >> + status = "okay"; >> +}; >> + >> +&smmu_peric { >> + status = "okay"; >> +}; >> + >> +&smmu_imem { >> + status = "okay"; >> +}; >> + >> +&smmu_fsys0 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_0 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_1 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_2 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_3 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_4 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_5 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_6 { >> + status = "okay"; >> +}; >> + >> +&hsi2c_7 { >> + status = "okay"; >> +}; >> + >> +&pwm_0 { >> + status = "okay"; >> +}; >> + >> +&pwm_1 { >> + status = "okay"; >> +}; >> + >> +&mdma0 { >> + status = "okay"; >> +}; >> + >> +&mdma1 { >> + status = "okay"; >> +}; >> + >> +&pdma0 { >> + status = "okay"; >> +}; >> + >> +&pdma1 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi >> b/arch/arm64/boot/dts/tesla/fsd.dtsi >> new file mode 100644 >> index 000000000000..47cd9f20566e >> --- /dev/null >> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi >> @@ -0,0 +1,715 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Tesla Full Self-Driving SoC device tree source >> + * >> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. >> + * https://www.samsung.com >> + * Copyright (c) 2017-2022 Tesla, Inc. >> + * https://www.tesla.com >> + */ >> + >> +#include #include >> + >> + >> +/ { >> + compatible = "tesla,fsd"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + watchdog0 = &watchdog_0; >> + watchdog1 = &watchdog_1; >> + watchdog2 = &watchdog_2; >> + hsi2c0 = &hsi2c_0; >> + hsi2c1 = &hsi2c_1; >> + hsi2c2 = &hsi2c_2; >> + hsi2c3 = &hsi2c_3; >> + hsi2c4 = &hsi2c_4; >> + hsi2c5 = &hsi2c_5; >> + hsi2c6 = &hsi2c_6; >> + hsi2c7 = &hsi2c_7; > >Drop all these non-standard aliases. > >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpucl0_0>; >> + }; >> + core1 { >> + cpu = <&cpucl0_1>; >> + }; >> + core2 { >> + cpu = <&cpucl0_2>; >> + }; >> + core3 { >> + cpu = <&cpucl0_3>; >> + }; >> + }; >> + >> + cluster1 { >> + core0 { >> + cpu = <&cpucl1_0>; >> + }; >> + core1 { >> + cpu = <&cpucl1_1>; >> + }; >> + core2 { >> + cpu = <&cpucl1_2>; >> + }; >> + core3 { >> + cpu = <&cpucl1_3>; >> + }; >> + }; >> + >> + cluster2 { >> + core0 { >> + cpu = <&cpucl2_0>; >> + }; >> + core1 { >> + cpu = <&cpucl2_1>; >> + }; >> + core2 { >> + cpu = <&cpucl2_2>; >> + }; >> + core3 { >> + cpu = <&cpucl2_3>; >> + }; >> + }; >> + }; >> + >> + /* Cluster 0 */ >> + cpucl0_0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x000>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl0_1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x001>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl0_2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x002>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl0_3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x003>; >> + enable-method = "psci"; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + /* Cluster 1 */ >> + cpucl1_0: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl1_1: cpu@101 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x101>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl1_2: cpu@102 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x102>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl1_3: cpu@103 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x103>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + /* Cluster 2 */ >> + cpucl2_0: cpu@200 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x200>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl2_1: cpu@201 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x201>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl2_2: cpu@202 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x202>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpucl2_3: cpu@203 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72"; >> + reg = <0x0 0x203>; >> + enable-method = "psci"; >> + clock-frequency = <2400000000>; >> + cpu-idle-states = <&CPU_SLEEP>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + idle-states { >> + entry-method = "arm,psci"; >> + >> + CPU_SLEEP: cpu-sleep { >> + idle-state-name = "c2"; >> + compatible = "arm,idle-state"; >> + local-timer-stop; >> + arm,psci-suspend-param = <0x0010000>; >> + entry-latency-us = <30>; >> + exit-latency-us = <75>; >> + min-residency-us = <300>; >> + status = "okay"; >> + }; >> + }; >> + >> + L2_0: l2-cache0 { >> + compatible = "cache"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, >> + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, >> + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, >> + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; >> + }; >> + >> + psci { >> + compatible = "arm,psci"; >> + method = "smc"; > >> + cpu_on = <0xC4000003>; >> + cpu_suspend = <0xC4000001>; >> + cpu_off = <0x84000002>; > >These codes are standardized since forever. Fix your firmware. > >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; >> + }; >> + >> + fin_pll: clock { >> + compatible = "fixed-clock"; >> + clock-output-names = "fin_pll"; >> + #clock-cells = <0>; >> + }; >> + >> + soc: soc { > >soc@0 > >You should see a warning for this. > >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; >> + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; >> + >> + gic: interrupt-controller@10400000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ >> + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ >> + }; >> + >> + smmu_isp: iommu@12100000 { >> + compatible = "arm,mmu-500"; >> + reg = <0x0 0x12100000 0x0 0x10000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <11>; >> + interrupts = , /* Global >secure fault */ >> + , /* Global non- >secure fault */ >> + , /* Combined >secure interrupt */ >> + , /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts */ >> + , /* for CAM_CSI >*/ >> + , /* for CAM_DP_0 >*/ >> + , /* for CAM_DP_1 >*/ >> + , /* for >CAM_ISP_0 */ >> + , /* for >CAM_ISP_1 */ >> + , /* for >CAM_MFC_0 */ >> + , /* for >CAM_MFC_1 */ >> + /* Per context non-secure context interrupts, 0-7 >interrupts */ >> + , /* for >CONTEXT_0 */ >> + , /* for >CONTEXT_1 */ >> + , /* for >CONTEXT_2 */ >> + , /* for >CONTEXT_3 */ >> + , /* for >CONTEXT_4 */ >> + , /* for >CONTEXT_5 */ >> + , /* for >CONTEXT_6 */ >> + ; /* for >CONTEXT_7 */ >> + status = "disabled"; > >IOMMU isn't really board specific, should it really be disabled? > >> + }; >> + >> + smmu_imem: iommu@10200000 { >> + compatible = "arm,mmu-500"; >> + reg = <0x0 0x10200000 0x0 0x10000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <7>; >> + interrupts = , /* Global >secure fault */ >> + , /* Global non- >secure fault */ >> + , /* Combined >secure interrupt */ >> + , /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts */ >> + , /* for FSYS1_0 */ >> + , /* for FSYS1_1 */ >> + , /* for IMEM_0 >*/ >> + /* Per context non-secure context interrupts, 0-3 >interrupts */ >> + , /* for >CONTEXT_0 */ >> + , /* for >CONTEXT_1 */ >> + , /* for >CONTEXT_2 */ >> + ; /* for >CONTEXT_3 */ >> + status = "disabled"; >> + }; >> + >> + smmu_peric: iommu@14900000 { >> + compatible = "arm,mmu-500"; >> + reg = <0x0 0x14900000 0x0 0x10000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <5>; >> + interrupts = , /* Global >secure fault */ >> + , /* Global non- >secure fault */ >> + , /* Combined >secure interrupt */ >> + , /* Combined >non-secure interrupt */ >> + /* Performance counter interrupts */ >> + , /* for PERIC */ >> + /* Per context non-secure context interrupts, 0-1 >interrupts */ >> + , /* for >CONTEXT_0 */ >> + ; /* for >CONTEXT_1 */ >> + status = "disabled"; >> + }; >> + >> + smmu_fsys0: iommu@15450000 { >> + compatible = "arm,mmu-500"; >> + reg = <0x0 0x15450000 0x0 0x10000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <5>; >> + interrupts = , /* Global >secure fault */ >> + , /* Global non- >secure fault */ >> + , /* Combined >secure interrupt */ >> + , /* Combined non- >secure interrupt */ >> + /* Performance counter interrupts */ >> + , /* for FSYS0 */ >> + /* Per context non-secure context interrupts, 0-1 >interrupts */ >> + , /* for CONTEXT_0 >*/ >> + ; /* for CONTEXT_1 >*/ >> + status = "disabled"; >> + }; >> + >> + clock_cmu: clock-controller@11C10000 { > >Lowercase hex for unit-addresses. > >Also, arrange nodes in address order. > >> + compatible = "tesla,fsd-clock-cmu"; >> + reg = <0x0 0x11C10000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>; >> + clock-names = "fin_pll"; >> + status = "disabled"; >> + }; >> + >> + clock_imem: clock-controller@10010000 { >> + compatible = "tesla,fsd-clock-imem"; >> + reg = <0x0 0x10010000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>, >> + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, >> + <&clock_cmu DOUT_CMU_IMEM_ACLK>, >> + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; >> + clock-names = "fin_pll", >> + "dout_cmu_imem_tcuclk", >> + "dout_cmu_imem_aclk", >> + "dout_cmu_imem_dmaclk"; >> + status = "disabled"; >> + }; >> + >> + clock_peric: clock-controller@14010000 { >> + compatible = "tesla,fsd-clock-peric"; >> + reg = <0x0 0x14010000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>, >> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, >> + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, >> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, >> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, >> + <&clock_cmu >DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; >> + clock-names = "fin_pll", >> + "dout_cmu_pll_shared0_div4", >> + "dout_cmu_peric_shared1div36", >> + "dout_cmu_peric_shared0div3_tbuclk", >> + "dout_cmu_peric_shared0div20", >> + "dout_cmu_peric_shared1div4_dmaclk"; >> + status = "disabled"; >> + }; >> + >> + clock_fsys0: clock-controller@15010000 { >> + compatible = "tesla,fsd-clock-fsys0"; >> + reg = <0x0 0x15010000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>, >> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, >> + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, >> + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; >> + clock-names = "fin_pll", >> + "dout_cmu_pll_shared0_div6", >> + "dout_cmu_fsys0_shared1div4", >> + "dout_cmu_fsys0_shared0div4"; >> + status = "disabled"; >> + }; >> + >> + clock_fsys1: clock-controller@16810000 { >> + compatible = "tesla,fsd-clock-fsys1"; >> + reg = <0x0 0x16810000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>, >> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, >> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; >> + clock-names = "fin_pll", >> + "dout_cmu_fsys1_shared0div8", >> + "dout_cmu_fsys1_shared0div4"; >> + status = "disabled"; >> + }; >> + >> + clock_mfc: clock-controller@12810000 { >> + compatible = "tesla,fsd-clock-mfc"; >> + reg = <0x0 0x12810000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>; >> + clock-names = "fin_pll"; >> + status = "disabled"; >> + }; >> + >> + clock_csi: clock-controller@12610000 { >> + compatible = "tesla,fsd-clock-cam_csi"; >> + reg = <0x0 0x12610000 0x0 0x3000>; >> + #clock-cells = <1>; >> + clocks = <&fin_pll>; >> + clock-names = "fin_pll"; >> + status = "disabled"; >> + }; >> + >> + mdma0: mdma@10100000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0x10100000 0x0 0x1000>; >> + interrupts = ; >> + #dma-cells = <1>; >> + #dma-channels = <8>; >> + #dma-requests = <32>; >> + clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; >> + clock-names = "apb_pclk"; >> + iommus = <&smmu_imem 0x800 0x0>; >> + status = "disabled"; >> + }; >> + >> + mdma1: mdma@10110000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0x10110000 0x0 0x1000>; >> + interrupts = ; >> + #dma-cells = <1>; >> + #dma-channels = <8>; >> + #dma-requests = <32>; >> + clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; >> + clock-names = "apb_pclk"; >> + iommus = <&smmu_imem 0x801 0x0>; >> + status = "disabled"; >> + }; >> + >> + pdma0: pdma@14280000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0x14280000 0x0 0x1000>; >> + interrupts = ; >> + #dma-cells = <1>; >> + #dma-channels = <8>; >> + #dma-requests = <32>; >> + clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; >> + clock-names = "apb_pclk"; >> + iommus = <&smmu_peric 0x2 0x0>; >> + status = "disabled"; >> + }; >> + >> + pdma1: pdma@14290000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0x14290000 0x0 0x1000>; >> + interrupts = ; >> + #dma-cells = <1>; >> + #dma-channels = <8>; >> + #dma-requests = <32>; >> + clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; >> + clock-names = "apb_pclk"; >> + iommus = <&smmu_peric 0x1 0x0>; >> + status = "disabled"; >> + }; >> + >> + mct: mct@10040000 { >> + compatible = "samsung,exynos4210-mct"; >> + reg = <0x0 0x10040000 0x0 0x800>; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; >> + clock-names = "fin_pll", "mct"; >> + }; >> + >> + serial_0: serial@14180000 { >> + compatible = "samsung,exynos4210-uart"; >> + reg = <0x0 0x14180000 0x0 0x100>; >> + interrupts = ; >> + dmas = <&pdma1 0>, <&pdma1 1>; >> + dma-names = "tx", "rx"; >> + clocks = <&clock_peric PERIC_PCLK_UART0>, >> + <&clock_peric PERIC_SCLK_UART0>; >> + clock-names = "uart", "clk_uart_baud0"; >> + status = "disabled"; >> + }; >> + >> + serial_1: serial@14190000 { >> + compatible = "samsung,exynos4210-uart"; >> + reg = <0x0 0x14190000 0x0 0x100>; >> + interrupts = ; >> + dmas = <&pdma1 2>, <&pdma1 3>; >> + dma-names = "tx", "rx"; >> + clocks = <&clock_peric PERIC_PCLK_UART1>, >> + <&clock_peric PERIC_SCLK_UART1>; >> + clock-names = "uart", "clk_uart_baud0"; >> + status = "disabled"; >> + }; >> + >> + pmu_system_controller: system-controller@11400000 { >> + compatible = "samsung,exynos7-pmu", "syscon"; >> + reg = <0x0 0x11400000 0x0 0x5000>; >> + }; >> + >> + watchdog_0: watchdog@100A0000 { >> + compatible = "samsung,exynos7-wdt"; >> + reg = <0x0 0x100A0000 0x0 0x100>; >> + interrupts = ; >> + samsung,syscon-phandle = <&pmu_system_controller>; >> + clocks = <&fin_pll>; >> + clock-names = "watchdog"; >> + interrupt-mode = <1>; >> + }; >> + >> + watchdog_1: watchdog@100B0000 { >> + compatible = "samsung,exynos7-wdt"; >> + reg = <0x0 0x100B0000 0x0 0x100>; >> + interrupts = ; >> + samsung,syscon-phandle = <&pmu_system_controller>; >> + clocks = <&fin_pll>; >> + clock-names = "watchdog"; >> + interrupt-mode = <1>; >> + }; >> + >> + watchdog_2: watchdog@100C0000 { >> + compatible = "samsung,exynos7-wdt"; >> + reg = <0x0 0x100C0000 0x0 0x100>; >> + interrupts = ; >> + samsung,syscon-phandle = <&pmu_system_controller>; >> + clocks = <&fin_pll>; >> + clock-names = "watchdog"; >> + interrupt-mode = <1>; >> + }; >> + >> + pwm_0: pwm@14100000 { >> + compatible = "samsung,exynos4210-pwm"; >> + reg = <0x0 0x14100000 0x0 0x100>; >> + samsung,pwm-outputs = <0>, <1>, <2>, <3>; >> + #pwm-cells = <3>; >> + clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; >> + clock-names = "timers"; >> + status = "disabled"; >> + }; >> + >> + pwm_1: pwm@14110000 { >> + compatible = "samsung,exynos4210-pwm"; >> + reg = <0x0 0x14110000 0x0 0x100>; >> + samsung,pwm-outputs = <0>, <1>, <2>, <3>; >> + #pwm-cells = <3>; >> + clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; >> + clock-names = "timers"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_0: hsi2c@14200000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14200000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c0_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C0>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_1: hsi2c@14210000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14210000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c1_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C1>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_2: hsi2c@14220000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14220000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c2_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C2>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_3: hsi2c@14230000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14230000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c3_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C3>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_4: hsi2c@14240000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14240000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c4_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C4>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_5: hsi2c@14250000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14250000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c5_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C5>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_6: hsi2c@14260000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14260000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c6_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C6>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + >> + hsi2c_7: hsi2c@14270000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x0 0x14270000 0x0 0x1000>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hs_i2c7_bus>; >> + clocks = <&clock_peric PERIC_PCLK_HSI2C7>; >> + clock-names = "hsi2c"; >> + status = "disabled"; >> + }; >> + }; >> +}; >> -- >> 2.17.1 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel