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[173.11.255.51]) by smtp.gmail.com with ESMTPSA id a8-20020ac86108000000b003435bb7fe9csm8443384qtm.78.2022.08.15.13.26.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Aug 2022 13:26:58 -0700 (PDT) Message-ID: <08d41c28-728a-0ef2-c528-b55c4984ca2b@linaro.org> Date: Mon, 15 Aug 2022 15:26:55 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 7/7] target/riscv: Honour -semihosting-config userspace=on and enable=on Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , Laurent Vivier , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Jiaxun Yang , Aleksandar Rikalo , Stefan Pejic , Chris Wulff , Marek Vasut , Palmer Dabbelt , Alistair Francis , Bin Meng , Max Filippov , Furquan Shaikh References: <20220815190303.2061559-1-peter.maydell@linaro.org> <20220815190303.2061559-8-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220815190303.2061559-8-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/15/22 14:03, Peter Maydell wrote: > The riscv target incorrectly enabled semihosting always, whether the > user asked for it or not. Call semihosting_enabled() passing the > correct value to the is_userspace argument, which fixes this and also > handles the userspace=on argument. > > Note that this is a behaviour change: we used to default to > semihosting being enabled, and now the user must pass > "-semihosting-config enable=on" if they want it. > > Signed-off-by: Peter Maydell > --- > target/riscv/cpu_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 59b3680b1b2..49c4ea98ac9 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -24,6 +24,7 @@ > #include "exec/exec-all.h" > #include "tcg/tcg-op.h" > #include "trace.h" > +#include "semihosting/semihost.h" > #include "semihosting/common-semi.h" > > int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) > @@ -1342,7 +1343,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > target_ulong mtval2 = 0; > > if (cause == RISCV_EXCP_SEMIHOST) { > - if (env->priv >= PRV_S) { > + if (semihosting_enabled(env->priv < PRV_S)) { > do_common_semihosting(cs); > env->pc += 4; > return; I think this should be done in translate. We should not have the overhead of checking the three insn sequence around ebreak unless semihosting is enabled. Note that ctx->mem_idx == env->priv, per cpu_mem_index(). r~