From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Date: Thu, 12 Dec 2019 04:43:53 +0300 Message-ID: <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> References: <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Peter De Schrijver Cc: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, sboyd@kernel.org, gregkh@linuxfoundation.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, allison@lohutok.net, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alexios.zavras@intel.com, alsa-devel@alsa-project.org List-Id: linux-tegra@vger.kernel.org 11.12.2019 18:10, Peter De Schrijver пишет: > On Tue, Dec 10, 2019 at 08:41:56PM +0300, Dmitry Osipenko wrote: > > .. > >>> >>> PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN >>> like explained above. >>> >>> CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to enable/disable >>> EXTPERIPH clock output to PMC CLK_OUT_1/2/3. >> >> [and to enable OSC as well] >> >>> So I believe we need to register as MUX and Gate rather than as a single >>> clock. Please confirm. >> >> 1. The force-enabling is applied to both OSC and EXTERN sources of >> PMC_CLK_OUT_x by PMC at once. >> >> 2. Both of PMC's force-enabling and OSC/EXTERN selection is internal to PMC. >> >> Should be better to define it as a single "pmc_clk_out_x". I don't see >> any good reasons for differentiating PMC's Gate from the MUX, it's a >> single hardware unit from a point of view of the rest of the system. >> >> Peter, do you have any objections? > > The reason to have separate gate and mux clocks, is to preserve compatibility > with existing users. > Otherwise the current users would need to figure out if there's a > single clock or 2 clocks to configure. I don't think adding that code in > each user is worth it only to have a sligthly nicer modelling of the > hardware. Could you please clarify what do you mean by the "existing users"? AFAIK, nothing in kernel uses mux clocks. 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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id i4sm2327370lji.0.2019.12.11.17.43.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 17:43:54 -0800 (PST) To: Peter De Schrijver References: <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> From: Dmitry Osipenko Message-ID: <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> Date: Thu, 12 Dec 2019 04:43:53 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> Content-Language: en-US X-Mailman-Approved-At: Thu, 12 Dec 2019 15:19:28 +0100 Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org, pgaikwad@nvidia.com, lgirdwood@gmail.com, mturquette@baylibre.com, mperttunen@nvidia.com, thierry.reding@gmail.com, josephl@nvidia.com, linux-clk@vger.kernel.org, mmaddireddy@nvidia.com, daniel.lezcano@linaro.org, krzk@kernel.org, jonathanh@nvidia.com, spujar@nvidia.com, devicetree@vger.kernel.org, arnd@arndb.de, markz@nvidia.com, alexios.zavras@intel.com, robh+dt@kernel.org, tiwai@suse.com, linux-tegra@vger.kernel.org, horms+renesas@verge.net.au, tglx@linutronix.de, allison@lohutok.net, sboyd@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, vidyas@nvidia.com, Jisheng.Zhang@synaptics.com, broonie@kernel.org, Sowjanya Komatineni Subject: Re: [alsa-devel] [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" MTEuMTIuMjAxOSAxODoxMCwgUGV0ZXIgRGUgU2NocmlqdmVyINC/0LjRiNC10YI6Cj4gT24gVHVl LCBEZWMgMTAsIDIwMTkgYXQgMDg6NDE6NTZQTSArMDMwMCwgRG1pdHJ5IE9zaXBlbmtvIHdyb3Rl Ogo+IAo+IC4uCj4gCj4+Pgo+Pj4gUE1DIGNsb2NrIGdhdGUgaXMgYmFzZWQgb24gdGhlIHN0YXRl IG9mIENMS3hfQUNDRVBUX1JFUSBhbmQgRk9SQ0VfRU4KPj4+IGxpa2UgZXhwbGFpbmVkIGFib3Zl Lgo+Pj4KPj4+IENMS3hfQUNDRVBUX1JFUSBpcyAwIGRlZmF1bHQgYW5kIEZPUkNFX0VOIGFjdHMg YXMgZ2F0ZSB0byBlbmFibGUvZGlzYWJsZQo+Pj4gRVhUUEVSSVBIIGNsb2NrIG91dHB1dCB0byBQ TUMgQ0xLX09VVF8xLzIvMy4KPj4KPj4gW2FuZCB0byBlbmFibGUgT1NDIGFzIHdlbGxdCj4+Cj4+ PiBTbyBJIGJlbGlldmUgd2UgbmVlZCB0byByZWdpc3RlciBhcyBNVVggYW5kIEdhdGUgcmF0aGVy IHRoYW4gYXMgYSBzaW5nbGUKPj4+IGNsb2NrLiBQbGVhc2UgY29uZmlybS4KPj4KPj4gMS4gVGhl IGZvcmNlLWVuYWJsaW5nIGlzIGFwcGxpZWQgdG8gYm90aCBPU0MgYW5kIEVYVEVSTiBzb3VyY2Vz IG9mCj4+IFBNQ19DTEtfT1VUX3ggYnkgUE1DIGF0IG9uY2UuCj4+Cj4+IDIuIEJvdGggb2YgUE1D J3MgZm9yY2UtZW5hYmxpbmcgYW5kIE9TQy9FWFRFUk4gc2VsZWN0aW9uIGlzIGludGVybmFsIHRv IFBNQy4KPj4KPj4gU2hvdWxkIGJlIGJldHRlciB0byBkZWZpbmUgaXQgYXMgYSBzaW5nbGUgInBt Y19jbGtfb3V0X3giLiBJIGRvbid0IHNlZQo+PiBhbnkgZ29vZCByZWFzb25zIGZvciBkaWZmZXJl bnRpYXRpbmcgUE1DJ3MgR2F0ZSBmcm9tIHRoZSBNVVgsIGl0J3MgYQo+PiBzaW5nbGUgaGFyZHdh cmUgdW5pdCBmcm9tIGEgcG9pbnQgb2YgdmlldyBvZiB0aGUgcmVzdCBvZiB0aGUgc3lzdGVtLgo+ Pgo+PiBQZXRlciwgZG8geW91IGhhdmUgYW55IG9iamVjdGlvbnM/Cj4gCj4gVGhlIHJlYXNvbiB0 byBoYXZlIHNlcGFyYXRlIGdhdGUgYW5kIG11eCBjbG9ja3MsIGlzIHRvIHByZXNlcnZlIGNvbXBh dGliaWxpdHkKPiB3aXRoIGV4aXN0aW5nIHVzZXJzLgo+IE90aGVyd2lzZSB0aGUgY3VycmVudCB1 c2VycyB3b3VsZCBuZWVkIHRvIGZpZ3VyZSBvdXQgaWYgdGhlcmUncyBhCj4gc2luZ2xlIGNsb2Nr IG9yIDIgY2xvY2tzIHRvIGNvbmZpZ3VyZS4gSSBkb24ndCB0aGluayBhZGRpbmcgdGhhdCBjb2Rl IGluCj4gZWFjaCB1c2VyIGlzIHdvcnRoIGl0IG9ubHkgdG8gaGF2ZSBhIHNsaWd0aGx5IG5pY2Vy IG1vZGVsbGluZyBvZiB0aGUKPiBoYXJkd2FyZS4KCkNvdWxkIHlvdSBwbGVhc2UgY2xhcmlmeSB3 aGF0IGRvIHlvdSBtZWFuIGJ5IHRoZSAiZXhpc3RpbmcgdXNlcnMiPwpBRkFJSywgbm90aGluZyBp biBrZXJuZWwgdXNlcyBtdXggY2xvY2tzLgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpBbHNhLWRldmVsIG1haWxpbmcgbGlzdApBbHNhLWRldmVsQGFsc2Et cHJvamVjdC5vcmcKaHR0cHM6Ly9tYWlsbWFuLmFsc2EtcHJvamVjdC5vcmcvbWFpbG1hbi9saXN0 aW5mby9hbHNhLWRldmVsCg==