* [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL
@ 2018-06-01 9:52 Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc Lionel Landwerlin
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Lionel Landwerlin @ 2018-06-01 9:52 UTC (permalink / raw)
To: intel-gfx
Hi all,
A small v2 to make Michel/Oscar's life easier with the rebasing of ICL
patches.
Cheers,
Lionel Landwerlin (2):
drm/i915: drop one bit on the hw_id when using guc
drm/i915/perf: fix ctx_id read with GuC & ICL
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem_context.c | 14 ++-
drivers/gpu/drm/i915/i915_perf.c | 123 ++++++++++++++++++------
drivers/gpu/drm/i915/intel_lrc.c | 7 +-
4 files changed, 114 insertions(+), 32 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
@ 2018-06-01 9:52 ` Lionel Landwerlin
2018-06-01 15:10 ` Chris Wilson
2018-06-01 9:52 ` [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL Lionel Landwerlin
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2018-06-01 9:52 UTC (permalink / raw)
To: intel-gfx
We currently using GuC as a proxy to the hardware. When Guc is used in
such mode, it consumes the bit 20 of the hw_id to indicate that the
workload was submitted by proxy.
So far we probably haven't seen the issue because we need to allocate
1048576+ contexts to hit this issue. Still, we should avoid allocating
the hw_id on that bit and restriction to bits [0:19] (i.e 20bits
instead of 21).
v2: Leave the max hw_id computation in i915_gem_context.c (Michel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
BSpec: 1237
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 14 +++++++++++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 38157df6ff5c..7088a1c3b6ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1841,6 +1841,7 @@ struct drm_i915_private {
*/
struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
+#define MAX_GUC_CONTEXT_HW_ID (1<<20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
} contexts;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 81f086397d10..fa732592e221 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -208,10 +208,18 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
int ret;
unsigned int max;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
max = GEN11_MAX_CONTEXT_HW_ID;
- else
- max = MAX_CONTEXT_HW_ID;
+ } else {
+ /*
+ * When using GuC in proxy submission, GuC consumes the
+ * highest bit in the context id to indicate proxy submission.
+ */
+ max = USES_GUC_SUBMISSION(dev_priv) ?
+ MAX_GUC_CONTEXT_HW_ID :
+ MAX_CONTEXT_HW_ID;
+ }
+
ret = ida_simple_get(&dev_priv->contexts.hw_ida,
0, max, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 517e92c6a70b..d09d2b79552f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -200,7 +200,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine,
*
* bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
* bits 12-31: LRCA, GTT address of (the HWSP of) this context
- * bits 32-52: ctx ID, a globally unique tag
+ * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
* bits 53-54: mbz, reserved for use by hardware
* bits 55-63: group ID, currently unused and set to 0
*
--
2.17.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc Lionel Landwerlin
@ 2018-06-01 9:52 ` Lionel Landwerlin
2018-06-01 15:18 ` Chris Wilson
2018-06-01 10:50 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: fix context filtering with GuC & ICL (rev2) Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2018-06-01 9:52 UTC (permalink / raw)
To: intel-gfx
One thing we didn't really understand about the OA report is that the
ContextID field (dword 2) is copy of the context descriptor (dword 1).
On Gen8->10 and without using GuC we didn't notice the issue because
we only checked the 21bits of the ContextID field in the OA reports
which matches exactly the hw_id stored into the context descriptor.
When using GuC submission we have an issue of a non matching hw_id
because GuC uses bit 20 of the hw_id to signal proxy submission. This
change introduces a mask to compare only the relevant bits.
On ICL the context descriptor format has changed and we failed to
address this. On top of using a mask we also need to shift the bits
properly.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252
BSpec: 1237
Testcase: igt/perf/gen8-unprivileged-single-ctx-counters
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 123 ++++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_lrc.c | 5 ++
3 files changed, 101 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7088a1c3b6ad..b363d5830a76 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1951,6 +1951,7 @@ struct drm_i915_private {
struct intel_context *pinned_ctx;
u32 specific_ctx_id;
+ u32 specific_ctx_id_mask;
struct hrtimer poll_check_timer;
wait_queue_head_t poll_wq;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4f0eb84b3c00..132ed3c67228 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -737,12 +737,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
continue;
}
- /*
- * XXX: Just keep the lower 21 bits for now since I'm not
- * entirely sure if the HW touches any of the higher bits in
- * this field
- */
- ctx_id = report32[2] & 0x1fffff;
+ ctx_id = report32[2] & dev_priv->perf.oa.specific_ctx_id_mask;
/*
* Squash whatever is in the CTX_ID field if it's marked as
@@ -1203,6 +1198,36 @@ static int i915_oa_read(struct i915_perf_stream *stream,
return dev_priv->perf.oa.ops.read(stream, buf, count, offset);
}
+static int oa_get_render_lrca(struct drm_i915_private *i915,
+ struct i915_gem_context *ctx,
+ u32 *lrca)
+{
+ struct intel_engine_cs *engine = i915->engine[RCS];
+ struct intel_context *ce;
+ int ret;
+
+ ret = i915_mutex_lock_interruptible(&i915->drm);
+ if (ret)
+ return ret;
+
+ /*
+ * As the ID is the gtt offset of the context's vma we
+ * pin the vma to ensure the ID remains fixed.
+ *
+ * NB: implied RCS engine...
+ */
+ ce = intel_context_pin(ctx, engine);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ i915->perf.oa.pinned_ctx = ce;
+
+ *lrca = i915_ggtt_offset(ce->state);
+
+ return 0;
+}
+
/**
* oa_get_render_ctx_id - determine and hold ctx hw id
* @stream: An i915-perf stream opened for OA metrics
@@ -1215,40 +1240,81 @@ static int i915_oa_read(struct i915_perf_stream *stream,
*/
static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
{
- struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct drm_i915_private *i915 = stream->dev_priv;
- if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
- dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id;
- } else {
- struct intel_engine_cs *engine = dev_priv->engine[RCS];
- struct intel_context *ce;
+ switch (INTEL_GEN(i915)) {
+ case 7: {
int ret;
- ret = i915_mutex_lock_interruptible(&dev_priv->drm);
+ ret = oa_get_render_lrca(i915, stream->ctx,
+ &i915->perf.oa.specific_ctx_id);
if (ret)
return ret;
/*
- * As the ID is the gtt offset of the context's vma we
- * pin the vma to ensure the ID remains fixed.
- *
- * NB: implied RCS engine...
+ * On Haswell we don't do any post processing of the reports
+ * and don't need to use the mask.
*/
- ce = intel_context_pin(stream->ctx, engine);
- mutex_unlock(&dev_priv->drm.struct_mutex);
- if (IS_ERR(ce))
- return PTR_ERR(ce);
+ i915->perf.oa.specific_ctx_id_mask = 0;
+ break;
+ }
- dev_priv->perf.oa.pinned_ctx = ce;
+ case 8:
+ case 9:
+ case 10:
+ if (USES_GUC_SUBMISSION(i915)) {
+ u32 lrca;
+ int ret;
- /*
- * Explicitly track the ID (instead of calling
- * i915_ggtt_offset() on the fly) considering the difference
- * with gen8+ and execlists
- */
- dev_priv->perf.oa.specific_ctx_id = i915_ggtt_offset(ce->state);
+ ret = oa_get_render_lrca(i915, stream->ctx, &lrca);
+ if (ret)
+ return ret;
+
+ /*
+ * The LRCA is aligned to a page. As a result the
+ * lower 12bits are always at 0 and reused in the
+ * context descriptor for some flags. They won't be
+ * part of the context ID in the OA reports, so squash
+ * those lower bits.
+ */
+ i915->perf.oa.specific_ctx_id =
+ (lrca + LRC_HEADER_PAGES * PAGE_SIZE) >> 12;
+
+ /*
+ * GuC uses the top bit to signal proxy submission, so
+ * ignore that bit if using GuC.
+ */
+ i915->perf.oa.specific_ctx_id_mask =
+ (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
+ } else {
+ i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
+ i915->perf.oa.specific_ctx_id_mask =
+ (1U << GEN8_CTX_ID_WIDTH) - 1;
+ }
+ break;
+
+ case 11: {
+ struct intel_engine_cs *engine = i915->engine[RCS];
+
+ i915->perf.oa.specific_ctx_id =
+ stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
+ engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
+ engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
+ i915->perf.oa.specific_ctx_id_mask =
+ ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
+ ((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
+ ((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) << (GEN11_ENGINE_CLASS_SHIFT - 32);
+ break;
}
+ default:
+ MISSING_CASE(INTEL_GEN(i915));
+ }
+
+ DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
+ i915->perf.oa.specific_ctx_id,
+ i915->perf.oa.specific_ctx_id_mask);
+
return 0;
}
@@ -1265,6 +1331,7 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
struct intel_context *ce;
dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
+ dev_priv->perf.oa.specific_ctx_id_mask = 0;
ce = fetch_and_zero(&dev_priv->perf.oa.pinned_ctx);
if (ce) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d09d2b79552f..eb25afa9694f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -233,6 +233,11 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
/* bits 12-31 */
GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
+ /*
+ * The following 32bits are copied into the OA reports (dword 2).
+ * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
+ * anything below.
+ */
if (INTEL_GEN(ctx->i915) >= 11) {
GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: fix context filtering with GuC & ICL (rev2)
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL Lionel Landwerlin
@ 2018-06-01 10:50 ` Patchwork
2018-06-01 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-01 10:50 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: fix context filtering with GuC & ICL (rev2)
URL : https://patchwork.freedesktop.org/series/44043/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46fbdfad6eee drm/i915: drop one bit on the hw_id when using guc
-:28: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#28: FILE: drivers/gpu/drm/i915/i915_drv.h:1844:
+#define MAX_GUC_CONTEXT_HW_ID (1<<20) /* exclusive */
^
total: 0 errors, 0 warnings, 1 checks, 36 lines checked
b6a655bcbadd drm/i915/perf: fix ctx_id read with GuC & ICL
-:182: WARNING:LONG_LINE: line over 100 characters
#182: FILE: drivers/gpu/drm/i915/i915_perf.c:1305:
+ ((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
total: 0 errors, 1 warnings, 0 checks, 177 lines checked
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915/perf: fix context filtering with GuC & ICL (rev2)
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
` (2 preceding siblings ...)
2018-06-01 10:50 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: fix context filtering with GuC & ICL (rev2) Patchwork
@ 2018-06-01 10:51 ` Patchwork
2018-06-01 11:08 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-06-01 14:00 ` ✓ Fi.CI.IGT: success " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-01 10:51 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: fix context filtering with GuC & ICL (rev2)
URL : https://patchwork.freedesktop.org/series/44043/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: drop one bit on the hw_id when using guc
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3665:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3666:16: warning: expression using sizeof(void)
Commit: drm/i915/perf: fix ctx_id read with GuC & ICL
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3666:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3667:16: warning: expression using sizeof(void)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/perf: fix context filtering with GuC & ICL (rev2)
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
` (3 preceding siblings ...)
2018-06-01 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-06-01 11:08 ` Patchwork
2018-06-01 14:00 ` ✓ Fi.CI.IGT: success " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-01 11:08 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: fix context filtering with GuC & ICL (rev2)
URL : https://patchwork.freedesktop.org/series/44043/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4269 -> Patchwork_9169 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9169 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9169, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/44043/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9169:
=== IGT changes ===
==== Possible regressions ====
igt@debugfs_test@read_all_entries:
fi-bdw-gvtdvm: PASS -> DMESG-WARN +2
== Known issues ==
Here are the changes found in Patchwork_9169 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-bdw-gvtdvm: PASS -> INCOMPLETE (fdo#105600)
fi-skl-gvtdvm: PASS -> INCOMPLETE (fdo#105600, fdo#104108)
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: PASS -> FAIL (fdo#102575)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-4200u: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
==== Possible fixes ====
igt@drv_module_reload@basic-reload-inject:
fi-glk-j4005: DMESG-WARN (fdo#106248, fdo#106725) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-skl-6700k2: INCOMPLETE (fdo#104108, k.org#199541, fdo#105524) -> PASS
igt@kms_busy@basic-flip-c:
fi-glk-j4005: FAIL (fdo#103182) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-kbl-7567u: FAIL (fdo#104724, fdo#103191) -> PASS
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103182 https://bugs.freedesktop.org/show_bug.cgi?id=103182
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541
== Participating hosts (43 -> 39) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-cnl-y3 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4269 -> Patchwork_9169
CI_DRM_4269: 25dda01a94cbf70d599be9b0f74c61f310858fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4503: ae0ea2a0cff1cf8516d18ada5b9db01c56b73ed9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9169: b6a655bcbaddeb31c824904d44c94e014c3f76ef @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b6a655bcbadd drm/i915/perf: fix ctx_id read with GuC & ICL
46fbdfad6eee drm/i915: drop one bit on the hw_id when using guc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9169/issues.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/perf: fix context filtering with GuC & ICL (rev2)
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
` (4 preceding siblings ...)
2018-06-01 11:08 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-06-01 14:00 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-01 14:00 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: fix context filtering with GuC & ICL (rev2)
URL : https://patchwork.freedesktop.org/series/44043/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4269_full -> Patchwork_9169_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9169_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9169_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/44043/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9169_full:
=== IGT changes ===
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
shard-kbl: PASS -> SKIP
igt@gem_mocs_settings@mocs-rc6-vebox:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9169_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
shard-apl: PASS -> DMESG-FAIL (fdo#106560)
igt@gem_eio@suspend:
shard-snb: PASS -> INCOMPLETE (fdo#105411)
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
shard-glk: PASS -> FAIL (fdo#105703)
==== Possible fixes ====
igt@kms_cursor_legacy@flip-vs-cursor-legacy:
shard-hsw: FAIL (fdo#102670) -> PASS
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-glk: FAIL (fdo#105363) -> PASS
igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@plain-flip-fb-recreate:
shard-glk: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
==== Warnings ====
igt@drv_selftest@live_gtt:
shard-glk: FAIL (fdo#105347) -> INCOMPLETE (k.org#198133, fdo#103359)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4269 -> Patchwork_9169
CI_DRM_4269: 25dda01a94cbf70d599be9b0f74c61f310858fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4503: ae0ea2a0cff1cf8516d18ada5b9db01c56b73ed9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9169: b6a655bcbaddeb31c824904d44c94e014c3f76ef @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9169/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc
2018-06-01 9:52 ` [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc Lionel Landwerlin
@ 2018-06-01 15:10 ` Chris Wilson
2018-06-01 19:24 ` Michel Thierry
0 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2018-06-01 15:10 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2018-06-01 10:52:14)
> We currently using GuC as a proxy to the hardware. When Guc is used in
> such mode, it consumes the bit 20 of the hw_id to indicate that the
> workload was submitted by proxy.
>
> So far we probably haven't seen the issue because we need to allocate
> 1048576+ contexts to hit this issue. Still, we should avoid allocating
> the hw_id on that bit and restriction to bits [0:19] (i.e 20bits
> instead of 21).
>
> v2: Leave the max hw_id computation in i915_gem_context.c (Michel)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> BSpec: 1237
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem_context.c | 14 +++++++++++---
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> 3 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 38157df6ff5c..7088a1c3b6ad 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1841,6 +1841,7 @@ struct drm_i915_private {
> */
> struct ida hw_ida;
> #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
> +#define MAX_GUC_CONTEXT_HW_ID (1<<20) /* exclusive */
> #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
> } contexts;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 81f086397d10..fa732592e221 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -208,10 +208,18 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
> int ret;
> unsigned int max;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> max = GEN11_MAX_CONTEXT_HW_ID;
> - else
> - max = MAX_CONTEXT_HW_ID;
> + } else {
> + /*
> + * When using GuC in proxy submission, GuC consumes the
> + * highest bit in the context id to indicate proxy submission.
> + */
> + max = USES_GUC_SUBMISSION(dev_priv) ?
> + MAX_GUC_CONTEXT_HW_ID :
> + MAX_CONTEXT_HW_ID;
I'm just going to say mixing if() and ternary ?: isn't great style.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL
2018-06-01 9:52 ` [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL Lionel Landwerlin
@ 2018-06-01 15:18 ` Chris Wilson
2018-06-01 17:08 ` Lionel Landwerlin
0 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2018-06-01 15:18 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2018-06-01 10:52:15)
> + /*
> + * The LRCA is aligned to a page. As a result the
> + * lower 12bits are always at 0 and reused in the
> + * context descriptor for some flags. They won't be
> + * part of the context ID in the OA reports, so squash
> + * those lower bits.
> + */
> + i915->perf.oa.specific_ctx_id =
> + (lrca + LRC_HEADER_PAGES * PAGE_SIZE) >> 12;
Hmm. I think what you want is lower_32_bits(ce->lrc_desc) as that is
what is being copied across.
> +
> + /*
> + * GuC uses the top bit to signal proxy submission, so
> + * ignore that bit if using GuC.
> + */
> + i915->perf.oa.specific_ctx_id_mask =
> + (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
> + } else {
> + i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
Imagine a ce->hw_id :)
Or for the time being ce->gem_context->hw_id;
I think I'm arguing for returning intel_context from oa_get_render_lrca()
and not lrca, and deriving all the different ctx_id from the pinned ce.
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL
2018-06-01 15:18 ` Chris Wilson
@ 2018-06-01 17:08 ` Lionel Landwerlin
2018-06-01 19:21 ` Michel Thierry
0 siblings, 1 reply; 13+ messages in thread
From: Lionel Landwerlin @ 2018-06-01 17:08 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 01/06/18 16:18, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2018-06-01 10:52:15)
>> + /*
>> + * The LRCA is aligned to a page. As a result the
>> + * lower 12bits are always at 0 and reused in the
>> + * context descriptor for some flags. They won't be
>> + * part of the context ID in the OA reports, so squash
>> + * those lower bits.
>> + */
>> + i915->perf.oa.specific_ctx_id =
>> + (lrca + LRC_HEADER_PAGES * PAGE_SIZE) >> 12;
> Hmm. I think what you want is lower_32_bits(ce->lrc_desc) as that is
> what is being copied across.
Well, in that case, this is GuC filling this. It appears to strip the
descriptor template :(
>
>> +
>> + /*
>> + * GuC uses the top bit to signal proxy submission, so
>> + * ignore that bit if using GuC.
>> + */
>> + i915->perf.oa.specific_ctx_id_mask =
>> + (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>> + } else {
>> + i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
> Imagine a ce->hw_id :)
>
> Or for the time being ce->gem_context->hw_id;
>
> I think I'm arguing for returning intel_context from oa_get_render_lrca()
> and not lrca, and deriving all the different ctx_id from the pinned ce.
> -Chris
Fair,
-
Lionel
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL
2018-06-01 17:08 ` Lionel Landwerlin
@ 2018-06-01 19:21 ` Michel Thierry
0 siblings, 0 replies; 13+ messages in thread
From: Michel Thierry @ 2018-06-01 19:21 UTC (permalink / raw)
To: Lionel Landwerlin, Chris Wilson, intel-gfx
On 6/1/2018 10:08 AM, Lionel Landwerlin wrote:
> On 01/06/18 16:18, Chris Wilson wrote:
>> Quoting Lionel Landwerlin (2018-06-01 10:52:15)
>>> + /*
>>> + * The LRCA is aligned to a page. As a result the
>>> + * lower 12bits are always at 0 and reused in the
>>> + * context descriptor for some flags. They won't be
>>> + * part of the context ID in the OA reports, so squash
>>> + * those lower bits.
>>> + */
>>> + i915->perf.oa.specific_ctx_id =
>>> + (lrca + LRC_HEADER_PAGES * PAGE_SIZE) >> 12;
>> Hmm. I think what you want is lower_32_bits(ce->lrc_desc) as that is
>> what is being copied across.
>
> Well, in that case, this is GuC filling this. It appears to strip the
> descriptor template :(
In this case 'lower_32_bits(ce->lrc_desc) >> 12' should be equivalent.
>
>>
>>> +
>>> + /*
>>> + * GuC uses the top bit to signal proxy submission, so
>>> + * ignore that bit if using GuC.
>>> + */
>>> + i915->perf.oa.specific_ctx_id_mask =
>>> + (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>>> + } else {
>>> + i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
>> Imagine a ce->hw_id :)
>>
>> Or for the time being ce->gem_context->hw_id;
>>
>> I think I'm arguing for returning intel_context from oa_get_render_lrca()
>> and not lrca, and deriving all the different ctx_id from the pinned ce.
>> -Chris
>
> Fair,
>
> -
> Lionel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc
2018-06-01 15:10 ` Chris Wilson
@ 2018-06-01 19:24 ` Michel Thierry
2018-06-01 23:57 ` Lionel Landwerlin
0 siblings, 1 reply; 13+ messages in thread
From: Michel Thierry @ 2018-06-01 19:24 UTC (permalink / raw)
To: Chris Wilson, Landwerlin, Lionel G, intel-gfx
On 6/1/2018 8:10 AM, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2018-06-01 10:52:14)
>> We currently using GuC as a proxy to the hardware. When Guc is used in
>> such mode, it consumes the bit 20 of the hw_id to indicate that the
>> workload was submitted by proxy.
>>
>> So far we probably haven't seen the issue because we need to allocate
>> 1048576+ contexts to hit this issue. Still, we should avoid allocating
>> the hw_id on that bit and restriction to bits [0:19] (i.e 20bits
>> instead of 21).
>>
>> v2: Leave the max hw_id computation in i915_gem_context.c (Michel)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> BSpec: 1237
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/i915_gem_context.c | 14 +++++++++++---
>> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
>> 3 files changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 38157df6ff5c..7088a1c3b6ad 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1841,6 +1841,7 @@ struct drm_i915_private {
>> */
>> struct ida hw_ida;
>> #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
>> +#define MAX_GUC_CONTEXT_HW_ID (1<<20) /* exclusive */
>> #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
>> } contexts;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
>> index 81f086397d10..fa732592e221 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -208,10 +208,18 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
>> int ret;
>> unsigned int max;
>>
>> - if (INTEL_GEN(dev_priv) >= 11)
>> + if (INTEL_GEN(dev_priv) >= 11) {
>> max = GEN11_MAX_CONTEXT_HW_ID;
>> - else
>> - max = MAX_CONTEXT_HW_ID;
>> + } else {
>> + /*
>> + * When using GuC in proxy submission, GuC consumes the
>> + * highest bit in the context id to indicate proxy submission.
>> + */
>> + max = USES_GUC_SUBMISSION(dev_priv) ?
>> + MAX_GUC_CONTEXT_HW_ID :
>> + MAX_CONTEXT_HW_ID;
>
> I'm just going to say mixing if() and ternary ?: isn't great style.
>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
My r-b from v1 still applies, but since I'm already writing this...
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc
2018-06-01 19:24 ` Michel Thierry
@ 2018-06-01 23:57 ` Lionel Landwerlin
0 siblings, 0 replies; 13+ messages in thread
From: Lionel Landwerlin @ 2018-06-01 23:57 UTC (permalink / raw)
To: Michel Thierry, Chris Wilson, intel-gfx
On 01/06/18 20:24, Michel Thierry wrote:
> On 6/1/2018 8:10 AM, Chris Wilson wrote:
>> Quoting Lionel Landwerlin (2018-06-01 10:52:14)
>>> We currently using GuC as a proxy to the hardware. When Guc is used in
>>> such mode, it consumes the bit 20 of the hw_id to indicate that the
>>> workload was submitted by proxy.
>>>
>>> So far we probably haven't seen the issue because we need to allocate
>>> 1048576+ contexts to hit this issue. Still, we should avoid allocating
>>> the hw_id on that bit and restriction to bits [0:19] (i.e 20bits
>>> instead of 21).
>>>
>>> v2: Leave the max hw_id computation in i915_gem_context.c (Michel)
>>>
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> BSpec: 1237
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>> drivers/gpu/drm/i915/i915_gem_context.c | 14 +++++++++++---
>>> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
>>> 3 files changed, 13 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 38157df6ff5c..7088a1c3b6ad 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1841,6 +1841,7 @@ struct drm_i915_private {
>>> */
>>> struct ida hw_ida;
>>> #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
>>> +#define MAX_GUC_CONTEXT_HW_ID (1<<20) /* exclusive */
>>> #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
>>> } contexts;
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
>>> b/drivers/gpu/drm/i915/i915_gem_context.c
>>> index 81f086397d10..fa732592e221 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>>> @@ -208,10 +208,18 @@ static int assign_hw_id(struct
>>> drm_i915_private *dev_priv, unsigned *out)
>>> int ret;
>>> unsigned int max;
>>> - if (INTEL_GEN(dev_priv) >= 11)
>>> + if (INTEL_GEN(dev_priv) >= 11) {
>>> max = GEN11_MAX_CONTEXT_HW_ID;
>>> - else
>>> - max = MAX_CONTEXT_HW_ID;
>>> + } else {
>>> + /*
>>> + * When using GuC in proxy submission, GuC consumes the
>>> + * highest bit in the context id to indicate proxy
>>> submission.
>>> + */
>>> + max = USES_GUC_SUBMISSION(dev_priv) ?
>>> + MAX_GUC_CONTEXT_HW_ID :
>>> + MAX_CONTEXT_HW_ID;
>>
>> I'm just going to say mixing if() and ternary ?: isn't great style.
>>
>> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> My r-b from v1 still applies, but since I'm already writing this...
>
> Reviewed-by: Michel Thierry <michel.thierry@intel.com>
>
>
>
Thanks, I should have added it.
-Lionel
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-06-01 23:57 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-01 9:52 [PATCH v2 0/2] drm/i915/perf: fix context filtering with GuC & ICL Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc Lionel Landwerlin
2018-06-01 15:10 ` Chris Wilson
2018-06-01 19:24 ` Michel Thierry
2018-06-01 23:57 ` Lionel Landwerlin
2018-06-01 9:52 ` [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL Lionel Landwerlin
2018-06-01 15:18 ` Chris Wilson
2018-06-01 17:08 ` Lionel Landwerlin
2018-06-01 19:21 ` Michel Thierry
2018-06-01 10:50 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: fix context filtering with GuC & ICL (rev2) Patchwork
2018-06-01 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-01 11:08 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-06-01 14:00 ` ✓ Fi.CI.IGT: success " Patchwork
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