From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932806AbcAYLzP (ORCPT ); Mon, 25 Jan 2016 06:55:15 -0500 Received: from mx2.suse.de ([195.135.220.15]:37137 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932556AbcAYLuf (ORCPT ); Mon, 25 Jan 2016 06:50:35 -0500 X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" From: Jiri Slaby To: stable@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Finn Thain , Geert Uytterhoeven , Oliver Neukum , Jiri Slaby Subject: [PATCH 3.12 21/39] m68k/mac: Make SCC reset work more reliably Date: Mon, 25 Jan 2016 12:50:02 +0100 Message-Id: <09fbd678e71b966ce48a6b41e0b19450e736a18d.1453722244.git.jslaby@suse.cz> X-Mailer: git-send-email 2.7.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Finn Thain 3.12-stable review patch. If anyone has any objections, please let me know. =============== commit 56931d73697c99ecf7aba6ae86c94d3a2d15d596 upstream. For SCC initialization we cannot assume that the control register is in the correct state to accept a register pointer. So first read from the control register in order to "sync" up. Signed-off-by: Finn Thain Signed-off-by: Geert Uytterhoeven Cc: Oliver Neukum Signed-off-by: Jiri Slaby --- arch/m68k/kernel/head.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index ac85f16534af..4180f8b20374 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -2909,7 +2909,9 @@ func_start serial_init,%d0/%d1/%a0/%a1 #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B) movel %pc@(L(mac_sccbase)),%a0 - /* Reset SCC device */ + /* Reset SCC register pointer */ + moveb %a0@(mac_scc_cha_a_ctrl_offset),%d0 + /* Reset SCC device: write register pointer then register value */ moveb #9,%a0@(mac_scc_cha_a_ctrl_offset) moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset) /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */ -- 2.7.0