From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Liu Yu-B13201" Subject: RE: [PATCH 7/9] KVM: PPC: Emulate trap SRR1 flags properly Date: Mon, 11 Jan 2010 14:58:34 +0800 Message-ID: <0A1FE637C2C7E148B9573BB60CC630E56C3F11@zch01exm26.fsl.freescale.net> References: <1262915889-11526-1-git-send-email-agraf@suse.de> <1262915889-11526-8-git-send-email-agraf@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: , "kvm-ppc" , "Benjamin Herrenschmidt" , "Liu Yu" To: "Hollis Blanchard" , "Alexander Graf" Return-path: Received: from az33egw02.freescale.net ([192.88.158.103]:50572 "EHLO az33egw02.freescale.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751387Ab0AKG6s convert rfc822-to-8bit (ORCPT ); Mon, 11 Jan 2010 01:58:48 -0500 Content-class: urn:content-classes:message In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: =20 > -----Original Message----- > From: kvm-ppc-owner@vger.kernel.org=20 > [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Hollis Blanchard > Sent: Saturday, January 09, 2010 3:30 AM > To: Alexander Graf > Cc: kvm@vger.kernel.org; kvm-ppc; Benjamin Herrenschmidt; Liu Yu > Subject: Re: [PATCH 7/9] KVM: PPC: Emulate trap SRR1 flags properly >=20 > On Thu, Jan 7, 2010 at 5:58 PM, Alexander Graf wrote: > > Book3S needs some flags in SRR1 to get to know details=20 > about an interrupt. > > > > One such example is the trap instruction. It tells the=20 > guest kernel that > > a program interrupt is due to a trap using a bit in SRR1. > > > > This patch implements above behavior, making WARN_ON behave=20 > like WARN_ON. >=20 > ... "for Book S". It already works properly for Book E,=20 > thankyouverymuch. ;) >=20 > > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c > > index 338baf9..e283e44 100644 > > --- a/arch/powerpc/kvm/booke.c > > +++ b/arch/powerpc/kvm/booke.c > > @@ -82,8 +82,9 @@ static void=20 > kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, > > =A0 =A0 =A0 =A0set_bit(priority, &vcpu->arch.pending_exceptions); > > =A0} > > > > -void kvmppc_core_queue_program(struct kvm_vcpu *vcpu) > > +void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags) > > =A0{ > > + =A0 =A0 =A0 /* BookE does flags in ESR, so ignore those we get he= re */ > > =A0 =A0 =A0 =A0kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGR= AM); > > =A0} >=20 > Actually, I think Book E prematurely sets ESR, since it's done before > the program interrupt is actually delivered. Architecturally, I'm not > sure if it's a problem, but philosophically I've always wanted it to > work the way you've just implemented for Book S. >=20 > Anyways, since we can't test changes at the moment (Yu, can you?), I'= d > settle for a comment to the effect that Book E code *should* do this, > but doesn't (rather than the comment above that says it's ok). >=20 Sure. You mean set the ESR at the moment we inject trap to guest? If it is not urgent, I'll do it later. From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Liu Yu-B13201" Date: Mon, 11 Jan 2010 06:58:34 +0000 Subject: RE: [PATCH 7/9] KVM: PPC: Emulate trap SRR1 flags properly Message-Id: <0A1FE637C2C7E148B9573BB60CC630E56C3F11@zch01exm26.fsl.freescale.net> List-Id: References: <1262915889-11526-1-git-send-email-agraf@suse.de> <1262915889-11526-8-git-send-email-agraf@suse.de> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: Hollis Blanchard , Alexander Graf Cc: kvm@vger.kernel.org, kvm-ppc , Benjamin Herrenschmidt , Liu Yu =20 > -----Original Message----- > From: kvm-ppc-owner@vger.kernel.org=20 > [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Hollis Blanchard > Sent: Saturday, January 09, 2010 3:30 AM > To: Alexander Graf > Cc: kvm@vger.kernel.org; kvm-ppc; Benjamin Herrenschmidt; Liu Yu > Subject: Re: [PATCH 7/9] KVM: PPC: Emulate trap SRR1 flags properly >=20 > On Thu, Jan 7, 2010 at 5:58 PM, Alexander Graf wrote: > > Book3S needs some flags in SRR1 to get to know details=20 > about an interrupt. > > > > One such example is the trap instruction. It tells the=20 > guest kernel that > > a program interrupt is due to a trap using a bit in SRR1. > > > > This patch implements above behavior, making WARN_ON behave=20 > like WARN_ON. >=20 > ... "for Book S". It already works properly for Book E,=20 > thankyouverymuch. ;) >=20 > > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c > > index 338baf9..e283e44 100644 > > --- a/arch/powerpc/kvm/booke.c > > +++ b/arch/powerpc/kvm/booke.c > > @@ -82,8 +82,9 @@ static void=20 > kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, > > =A0 =A0 =A0 =A0set_bit(priority, &vcpu->arch.pending_exceptions); > > =A0} > > > > -void kvmppc_core_queue_program(struct kvm_vcpu *vcpu) > > +void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags) > > =A0{ > > + =A0 =A0 =A0 /* BookE does flags in ESR, so ignore those we get here */ > > =A0 =A0 =A0 =A0kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); > > =A0} >=20 > Actually, I think Book E prematurely sets ESR, since it's done before > the program interrupt is actually delivered. Architecturally, I'm not > sure if it's a problem, but philosophically I've always wanted it to > work the way you've just implemented for Book S. >=20 > Anyways, since we can't test changes at the moment (Yu, can you?), I'd > settle for a comment to the effect that Book E code *should* do this, > but doesn't (rather than the comment above that says it's ok). >=20 Sure. You mean set the ESR at the moment we inject trap to guest? If it is not urgent, I'll do it later.