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([2600:1010:b069:8a27:ddd9:92ea:d62b:8a52]) by smtp.gmail.com with ESMTPSA id d69sm4545987pfd.72.2020.02.26.13.35.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Feb 2020 13:35:49 -0800 (PST) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [patch 01/15] x86/irq: Convey vector as argument and not in ptregs Date: Wed, 26 Feb 2020 13:35:47 -0800 Message-Id: <0BF722CE-26CF-43AC-A2E4-5C4639794159@amacapital.net> References: <87k149p0na.fsf@nanos.tec.linutronix.de> Cc: Brian Gerst , LKML , the arch/x86 maintainers , Steven Rostedt , Juergen Gross , Paolo Bonzini , Arnd Bergmann In-Reply-To: <87k149p0na.fsf@nanos.tec.linutronix.de> To: Thomas Gleixner X-Mailer: iPhone Mail (17D50) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Feb 26, 2020, at 12:13 PM, Thomas Gleixner wrote: >=20 > =EF=BB=BFBrian Gerst writes: >=20 >>> On Tue, Feb 25, 2020 at 6:26 PM Thomas Gleixner wro= te: >>>=20 >>> Device interrupts which go through do_IRQ() or the spurious interrupt >>> handler have their separate entry code on 64 bit for no good reason. >>>=20 >>> Both 32 and 64 bit transport the vector number through ORIG_[RE]AX in >>> pt_regs. Further the vector number is forced to fit into an u8 and is >>> complemented and offset by 0x80 for historical reasons. >>=20 >> The reason for the 0x80 offset is so that the push instruction only >> takes two bytes. This allows each entry stub to be packed into a >> fixed 8 bytes. idt_setup_apic_and_irq_gates() assumes this 8-byte >> fixed length for the stubs, so now every odd vector after 0x80 is >> broken. >>=20 >> 508: 6a 7f pushq $0x7f >> 50a: e9 f1 08 00 00 jmpq e00 >> 50f: 90 nop >> 510: 68 80 00 00 00 pushq $0x80 >> 515: e9 e6 08 00 00 jmpq e00 >> 51a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) >> 520: 68 81 00 00 00 pushq $0x81 >> 525: e9 d6 08 00 00 jmpq e00 >> 52a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) >>=20 >> The 0x81 vector should start at 0x518, not 0x520. >=20 > Bah, I somehow missed that big fat comment explaining it. :) >=20 > Thanks for catching it. So my testing just has been lucky to not hit one > of those. >=20 > Now the question is whether we care about the packed stubs or just make > them larger by using alignment to get rid of this silly +0x80 and > ~vector fixup later on. The straight forward thing clearly has its charm > and I doubt it matters in measurable ways. I agree it probably doesn=E2=80=99t matter. That being said, I have a distin= ct memory of fixing that asm so it would fail the build if the alignment was= off. >=20 > Thanks, >=20 > tglx >=20 >=20