From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754003AbcALUrp (ORCPT ); Tue, 12 Jan 2016 15:47:45 -0500 Received: from mail.kernel.org ([198.145.29.136]:53377 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752404AbcALUro (ORCPT ); Tue, 12 Jan 2016 15:47:44 -0500 From: Andy Lutomirski To: peterz@infradead.org, x86@kernel.org Cc: "linux-kernel@vger.kernel.org" , Dave Hansen , Rik van Riel , Brian Gerst , Andrew Morton , Denys Vlasenko , Borislav Petkov , Linus Torvalds , "linux-tip-commits@vger.kernel.org" , Andy Lutomirski , stable@vger.kernel.org Subject: [PATCH v2] x86/mm: Improve switch_mm barrier comments Date: Tue, 12 Jan 2016 12:47:40 -0800 Message-Id: <0a0b43cdcdd241c5faaaecfbcc91a155ddedc9a1.1452631609.git.luto@kernel.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <20160112102105.GA4878@gmail.com> References: <20160112102105.GA4878@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org My previous comments were still a bit confusing and there was a typo. Fix it up. Reported-by: Peter Zijlstra Fixes: 71b3c126e611 ("x86/mm: Add barriers and document switch_mm()-vs-flush synchronization") Cc: stable@vger.kernel.org Signed-off-by: Andy Lutomirski --- Changes from v1: Totally different. arch/x86/include/asm/mmu_context.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 1edc9cd198b8..4fcae1e066f3 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -132,14 +132,16 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * be sent, and CPU 0's TLB will contain a stale entry.) * * The bad outcome can occur if either CPU's load is - * reordered before that CPU's store, so both CPUs much + * reordered before that CPU's store, so both CPUs must * execute full barriers to prevent this from happening. * * Thus, switch_mm needs a full barrier between the * store to mm_cpumask and any operation that could load - * from next->pgd. This barrier synchronizes with - * remote TLB flushers. Fortunately, load_cr3 is - * serializing and thus acts as a full barrier. + * from next->pgd. TLB fills are special and can happen + * due to instruction fetches or for no reason at all, + * and neither LOCK nor MFENCE orders them. + * Fortunately, load_cr3 is serializing and gives the + * ordering guarantee we need. * */ load_cr3(next->pgd); @@ -188,9 +190,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * tlb flush IPI delivery. We must reload CR3 * to make sure to use no freed page tables. * - * As above, this is a barrier that forces - * TLB repopulation to be ordered after the - * store to mm_cpumask. + * As above, load_cr3 is serializing and orders TLB + * fills with respect to the mm_cpumask write. */ load_cr3(next->pgd); trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); -- 2.5.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Andy Lutomirski To: peterz@infradead.org, x86@kernel.org Cc: "linux-kernel@vger.kernel.org" , Dave Hansen , Rik van Riel , Brian Gerst , Andrew Morton , Denys Vlasenko , Borislav Petkov , Linus Torvalds , "linux-tip-commits@vger.kernel.org" , Andy Lutomirski , stable@vger.kernel.org Subject: [PATCH v2] x86/mm: Improve switch_mm barrier comments Date: Tue, 12 Jan 2016 12:47:40 -0800 Message-Id: <0a0b43cdcdd241c5faaaecfbcc91a155ddedc9a1.1452631609.git.luto@kernel.org> In-Reply-To: <20160112102105.GA4878@gmail.com> References: <20160112102105.GA4878@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: My previous comments were still a bit confusing and there was a typo. Fix it up. Reported-by: Peter Zijlstra Fixes: 71b3c126e611 ("x86/mm: Add barriers and document switch_mm()-vs-flush synchronization") Cc: stable@vger.kernel.org Signed-off-by: Andy Lutomirski --- Changes from v1: Totally different. arch/x86/include/asm/mmu_context.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 1edc9cd198b8..4fcae1e066f3 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -132,14 +132,16 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * be sent, and CPU 0's TLB will contain a stale entry.) * * The bad outcome can occur if either CPU's load is - * reordered before that CPU's store, so both CPUs much + * reordered before that CPU's store, so both CPUs must * execute full barriers to prevent this from happening. * * Thus, switch_mm needs a full barrier between the * store to mm_cpumask and any operation that could load - * from next->pgd. This barrier synchronizes with - * remote TLB flushers. Fortunately, load_cr3 is - * serializing and thus acts as a full barrier. + * from next->pgd. TLB fills are special and can happen + * due to instruction fetches or for no reason at all, + * and neither LOCK nor MFENCE orders them. + * Fortunately, load_cr3 is serializing and gives the + * ordering guarantee we need. * */ load_cr3(next->pgd); @@ -188,9 +190,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * tlb flush IPI delivery. We must reload CR3 * to make sure to use no freed page tables. * - * As above, this is a barrier that forces - * TLB repopulation to be ordered after the - * store to mm_cpumask. + * As above, load_cr3 is serializing and orders TLB + * fills with respect to the mm_cpumask write. */ load_cr3(next->pgd); trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); -- 2.5.0