From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joao Pinto Subject: Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Date: Mon, 16 Jan 2017 10:27:58 +0000 Message-ID: <0a16c862-312f-655e-3d66-bdb0c1f78584@synopsys.com> References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-12-git-send-email-kishon@ti.com> <4a89fb45-af84-d660-5ef0-12227b141cda@synopsys.com> <587C586C.6070003@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <587C586C.6070003-l0cyMroinI0@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Kishon Vijay Abraham I , Joao Pinto , Bjorn Helgaas , Jingoo Han , Arnd Bergmann Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-arm-kernel-VrBV9hrLPhE@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, nsekhar-l0cyMroinI0@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org Hi, Ās 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > > On Friday 13 January 2017 10:19 PM, Joao Pinto wrote: >> Ās 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >>> Split pcie-designware.c into pcie-designware-host.c that contains >>> the host specific parts of the driver and pcie-designware.c that >>> contains the parts used by both host driver and endpoint driver. >>> >>> Signed-off-by: Kishon Vijay Abraham I >>> --- >>> drivers/pci/dwc/Makefile | 2 +- >>> drivers/pci/dwc/pcie-designware-host.c | 619 ++++++++++++++++++++++++++++++++ >>> drivers/pci/dwc/pcie-designware.c | 613 +------------------------------ >>> drivers/pci/dwc/pcie-designware.h | 8 + >>> 4 files changed, 634 insertions(+), 608 deletions(-) >>> create mode 100644 drivers/pci/dwc/pcie-designware-host.c >>> >>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile >>> index 7d27c14..3b57e55 100644 >>> --- a/drivers/pci/dwc/Makefile >>> +++ b/drivers/pci/dwc/Makefile >>> @@ -1,4 +1,4 @@ >> >> (snip...) >> >>> -static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> - int type, u64 cpu_addr, u64 pci_addr, >>> - u32 size) >>> +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, >>> + u64 cpu_addr, u64 pci_addr, u32 size) >>> { >>> u32 retries, val; >>> >>> @@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> dev_err(pci->dev, "iATU is not being enabled\n"); >>> } >> >> Kishon, iATU only makes sense in The Root Complex (host), so it should be inside >> the pcie-designware-host. > > That is not true. Outbound ATU should be programmed to access host side buffers > and inbound ATU should be programmed for the host to access EP mem space. Sorry, I was not clear enough. What I was trying to suggest is, since the ATU programming is done by the host, wouldn't be better to include it in the pcie-designware-host? It is just an architectural detail. > > Thanks > Kishon > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751419AbdAPK2G (ORCPT ); Mon, 16 Jan 2017 05:28:06 -0500 Received: from smtprelay2.synopsys.com ([198.182.60.111]:44793 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750991AbdAPK2D (ORCPT ); Mon, 16 Jan 2017 05:28:03 -0500 Subject: Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files To: Kishon Vijay Abraham I , Joao Pinto , Bjorn Helgaas , Jingoo Han , Arnd Bergmann References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-12-git-send-email-kishon@ti.com> <4a89fb45-af84-d660-5ef0-12227b141cda@synopsys.com> <587C586C.6070003@ti.com> CC: , , , , , , , , , , From: Joao Pinto Message-ID: <0a16c862-312f-655e-3d66-bdb0c1f78584@synopsys.com> Date: Mon, 16 Jan 2017 10:27:58 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <587C586C.6070003@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.107.19.116] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Ās 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > > On Friday 13 January 2017 10:19 PM, Joao Pinto wrote: >> Ās 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >>> Split pcie-designware.c into pcie-designware-host.c that contains >>> the host specific parts of the driver and pcie-designware.c that >>> contains the parts used by both host driver and endpoint driver. >>> >>> Signed-off-by: Kishon Vijay Abraham I >>> --- >>> drivers/pci/dwc/Makefile | 2 +- >>> drivers/pci/dwc/pcie-designware-host.c | 619 ++++++++++++++++++++++++++++++++ >>> drivers/pci/dwc/pcie-designware.c | 613 +------------------------------ >>> drivers/pci/dwc/pcie-designware.h | 8 + >>> 4 files changed, 634 insertions(+), 608 deletions(-) >>> create mode 100644 drivers/pci/dwc/pcie-designware-host.c >>> >>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile >>> index 7d27c14..3b57e55 100644 >>> --- a/drivers/pci/dwc/Makefile >>> +++ b/drivers/pci/dwc/Makefile >>> @@ -1,4 +1,4 @@ >> >> (snip...) >> >>> -static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> - int type, u64 cpu_addr, u64 pci_addr, >>> - u32 size) >>> +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, >>> + u64 cpu_addr, u64 pci_addr, u32 size) >>> { >>> u32 retries, val; >>> >>> @@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> dev_err(pci->dev, "iATU is not being enabled\n"); >>> } >> >> Kishon, iATU only makes sense in The Root Complex (host), so it should be inside >> the pcie-designware-host. > > That is not true. Outbound ATU should be programmed to access host side buffers > and inbound ATU should be programmed for the host to access EP mem space. Sorry, I was not clear enough. What I was trying to suggest is, since the ATU programming is done by the host, wouldn't be better to include it in the pcie-designware-host? It is just an architectural detail. > > Thanks > Kishon > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files To: Kishon Vijay Abraham I , Joao Pinto , Bjorn Helgaas , Jingoo Han , Arnd Bergmann References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-12-git-send-email-kishon@ti.com> <4a89fb45-af84-d660-5ef0-12227b141cda@synopsys.com> <587C586C.6070003@ti.com> From: Joao Pinto Message-ID: <0a16c862-312f-655e-3d66-bdb0c1f78584@synopsys.com> Date: Mon, 16 Jan 2017 10:27:58 +0000 MIME-Version: 1.0 In-Reply-To: <587C586C.6070003@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-doc@vger.kernel.org, linux-pci@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="windows-1252" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Hi, =C0s 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > = > On Friday 13 January 2017 10:19 PM, Joao Pinto wrote: >> =C0s 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >>> Split pcie-designware.c into pcie-designware-host.c that contains >>> the host specific parts of the driver and pcie-designware.c that >>> contains the parts used by both host driver and endpoint driver. >>> >>> Signed-off-by: Kishon Vijay Abraham I >>> --- >>> drivers/pci/dwc/Makefile | 2 +- >>> drivers/pci/dwc/pcie-designware-host.c | 619 ++++++++++++++++++++++++= ++++++++ >>> drivers/pci/dwc/pcie-designware.c | 613 +-----------------------= ------- >>> drivers/pci/dwc/pcie-designware.h | 8 + >>> 4 files changed, 634 insertions(+), 608 deletions(-) >>> create mode 100644 drivers/pci/dwc/pcie-designware-host.c >>> >>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile >>> index 7d27c14..3b57e55 100644 >>> --- a/drivers/pci/dwc/Makefile >>> +++ b/drivers/pci/dwc/Makefile >>> @@ -1,4 +1,4 @@ >> >> (snip...) >> >>> -static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> - int type, u64 cpu_addr, u64 pci_addr, >>> - u32 size) >>> +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int typ= e, >>> + u64 cpu_addr, u64 pci_addr, u32 size) >>> { >>> u32 retries, val; >>> = >>> @@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_p= cie *pci, int index, >>> dev_err(pci->dev, "iATU is not being enabled\n"); >>> } >> >> Kishon, iATU only makes sense in The Root Complex (host), so it should b= e inside >> the pcie-designware-host. > = > That is not true. Outbound ATU should be programmed to access host side b= uffers > and inbound ATU should be programmed for the host to access EP mem space. Sorry, I was not clear enough. What I was trying to suggest is, since the A= TU programming is done by the host, wouldn't be better to include it in the pcie-designware-host? It is just an architectural detail. > = > Thanks > Kishon > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joao.Pinto@synopsys.com (Joao Pinto) Date: Mon, 16 Jan 2017 10:27:58 +0000 Subject: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files In-Reply-To: <587C586C.6070003@ti.com> References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-12-git-send-email-kishon@ti.com> <4a89fb45-af84-d660-5ef0-12227b141cda@synopsys.com> <587C586C.6070003@ti.com> Message-ID: <0a16c862-312f-655e-3d66-bdb0c1f78584@synopsys.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, ?s 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > > On Friday 13 January 2017 10:19 PM, Joao Pinto wrote: >> ?s 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >>> Split pcie-designware.c into pcie-designware-host.c that contains >>> the host specific parts of the driver and pcie-designware.c that >>> contains the parts used by both host driver and endpoint driver. >>> >>> Signed-off-by: Kishon Vijay Abraham I >>> --- >>> drivers/pci/dwc/Makefile | 2 +- >>> drivers/pci/dwc/pcie-designware-host.c | 619 ++++++++++++++++++++++++++++++++ >>> drivers/pci/dwc/pcie-designware.c | 613 +------------------------------ >>> drivers/pci/dwc/pcie-designware.h | 8 + >>> 4 files changed, 634 insertions(+), 608 deletions(-) >>> create mode 100644 drivers/pci/dwc/pcie-designware-host.c >>> >>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile >>> index 7d27c14..3b57e55 100644 >>> --- a/drivers/pci/dwc/Makefile >>> +++ b/drivers/pci/dwc/Makefile >>> @@ -1,4 +1,4 @@ >> >> (snip...) >> >>> -static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> - int type, u64 cpu_addr, u64 pci_addr, >>> - u32 size) >>> +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, >>> + u64 cpu_addr, u64 pci_addr, u32 size) >>> { >>> u32 retries, val; >>> >>> @@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, >>> dev_err(pci->dev, "iATU is not being enabled\n"); >>> } >> >> Kishon, iATU only makes sense in The Root Complex (host), so it should be inside >> the pcie-designware-host. > > That is not true. Outbound ATU should be programmed to access host side buffers > and inbound ATU should be programmed for the host to access EP mem space. Sorry, I was not clear enough. What I was trying to suggest is, since the ATU programming is done by the host, wouldn't be better to include it in the pcie-designware-host? It is just an architectural detail. > > Thanks > Kishon >