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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFwmU-0006xp-Sc; Mon, 15 Apr 2019 08:15:58 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFwmB-0006ZQ-9t for linux-arm-kernel@lists.infradead.org; Mon, 15 Apr 2019 08:15:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B23D7374; Mon, 15 Apr 2019 01:15:38 -0700 (PDT) Received: from [10.1.196.92] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C508A3F68F; Mon, 15 Apr 2019 01:15:37 -0700 (PDT) Subject: Re: [PATCH 1/4] arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32 To: Will Deacon References: <20190408160216.223871-1-marc.zyngier@arm.com> <20190408160216.223871-2-marc.zyngier@arm.com> <20190412131750.GC29218@fuggles.cambridge.arm.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190412131750.GC29218@fuggles.cambridge.arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_011539_352455_16789D38 X-CRM114-Status: GOOD ( 21.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Daniel Lezcano , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/04/2019 14:17, Will Deacon wrote: > Hi Marc, > > On Mon, Apr 08, 2019 at 05:02:13PM +0100, Marc Zyngier wrote: >> We currently deal with ARM64_ERRATUM_1188873 by always trapping EL0 >> accesses for both instruction sets. Although nothing wrong comes out >> of that, people trying to squeeze the last drop of performance from >> buggy HW find this over the top. Oh well. >> >> Let's change the mitigation by flipping the counter enable bit >> on return to userspace. Non-broken HW gets an extra branch on >> the fast path, which is hopefully not the end of the world. >> The arch timer workaround it also removed. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/kernel/entry.S | 23 +++++++++++++++++++++++ >> drivers/clocksource/arm_arch_timer.c | 15 --------------- >> 2 files changed, 23 insertions(+), 15 deletions(-) >> >> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S >> index c50a7a75f2e0..e0aed21ab402 100644 >> --- a/arch/arm64/kernel/entry.S >> +++ b/arch/arm64/kernel/entry.S >> @@ -336,6 +336,29 @@ alternative_if ARM64_WORKAROUND_845719 >> alternative_else_nop_endif >> #endif >> 3: >> +#ifdef CONFIG_ARM64_ERRATUM_1188873 >> +alternative_if_not ARM64_WORKAROUND_1188873 >> + b 1f >> +alternative_else_nop_endif >> + >> + ubfx x0, x22, #4, #1 // Extract PSR_MODE32 >> + eor x0, x0, #1 // Negate it >> +alternative_if_not ARM64_HAS_VIRT_HOST_EXTN >> + mrs x1, cntkctl_el1 >> +alternative_else >> + mrs x1, cnthctl_el2 >> +alternative_endif >> + ubfx x2, x1, #1, #1 // Extract EL0VCTEN >> + cmp x2, x0 > > Aren't the flags live at this point (they indicate native vs compat)? > Maybe you can use that instead of re-extracting PSR_MODE32. Robin and I have been reworking this, see other emails in the same thread, and the code looks pretty different now (and not breaking things anymore). > >> + b.eq 1f // Matches, nothing to do >> + bfi x1, x0, #1, #1 // Move EL0VCTEN in place > > ARCH_TIMER_USR_VCT_ACCESS_EN > >> +alternative_if_not ARM64_HAS_VIRT_HOST_EXTN >> + msr cntkctl_el1, x1 >> +alternative_else >> + msr cnthctl_el2, x1 >> +alternative_endif >> +1: > > Sorry to be a pain, but could you use label '4:' here and update the others > in this macro, please? Sure, no problem. > >> +#endif >> apply_ssbd 0, x0, x1 >> .endif >> >> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c >> index 5fcccc467868..27acc9eb0f7c 100644 >> --- a/drivers/clocksource/arm_arch_timer.c >> +++ b/drivers/clocksource/arm_arch_timer.c > > I probably need an Ack from Thomas or Daniel on these parts, so I can take > the series via arm64. Daniel is on Cc, and hopefully v2 will be OK. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel