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[176.184.17.116]) by smtp.gmail.com with ESMTPSA id l21-20020a170906231500b00a0b6541b592sm722657eja.88.2023.11.30.06.17.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Nov 2023 06:17:33 -0800 (PST) Message-ID: <0ae7ffb0-a0af-4afc-ad29-384daff52484@linaro.org> Date: Thu, 30 Nov 2023 15:17:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 04/10] hvf: Add Apple Silicon support Content-Language: en-US To: Alexander Graf , QEMU Developers Cc: Peter Maydell , Eduardo Habkost , Sergio Lopez , Peter Collingbourne , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm , Frank Yang , Paolo Bonzini References: <20210916155404.86958-1-agraf@csgraf.de> <20210916155404.86958-5-agraf@csgraf.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20210916155404.86958-5-agraf@csgraf.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 16/9/21 17:53, Alexander Graf wrote: > With Apple Silicon available to the masses, it's a good time to add support > for driving its virtualization extensions from QEMU. > > This patch adds all necessary architecture specific code to get basic VMs > working, including save/restore. > > Known limitations: > > - WFI handling is missing (follows in later patch) > - No watchpoint/breakpoint support > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Reviewed-by: Sergio Lopez > Reviewed-by: Peter Maydell > --- > MAINTAINERS | 5 + > accel/hvf/hvf-accel-ops.c | 9 + > include/sysemu/hvf_int.h | 10 +- > meson.build | 1 + > target/arm/hvf/hvf.c | 794 ++++++++++++++++++++++++++++++++++++ > target/arm/hvf/trace-events | 10 + > target/i386/hvf/hvf.c | 5 + > 7 files changed, 833 insertions(+), 1 deletion(-) > create mode 100644 target/arm/hvf/hvf.c > create mode 100644 target/arm/hvf/trace-events > +int hvf_arch_init_vcpu(CPUState *cpu) > +{ > + ARMCPU *arm_cpu = ARM_CPU(cpu); > + CPUARMState *env = &arm_cpu->env; > + uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); > + uint32_t sregs_cnt = 0; > + uint64_t pfr; > + hv_return_t ret; > + int i; > + > + env->aarch64 = 1; > + asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); > + > + /* Allocate enough space for our sysreg sync */ > + arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, > + sregs_match_len); > + arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, > + sregs_match_len); > + arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, > + arm_cpu->cpreg_vmstate_indexes, > + sregs_match_len); > + arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, > + arm_cpu->cpreg_vmstate_values, > + sregs_match_len); > + > + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); > + > + /* Populate cp list for all known sysregs */ > + for (i = 0; i < sregs_match_len; i++) { > + const ARMCPRegInfo *ri; > + uint32_t key = hvf_sreg_match[i].key; > + > + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); > + if (ri) { > + assert(!(ri->type & ARM_CP_NO_RAW)); > + hvf_sreg_match[i].cp_idx = sregs_cnt; > + arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); So this hash ...: /* * Convert a truncated 32 bit hashtable key into the full * 64 bit KVM register ID. */ static uint64_t cpreg_to_kvm_id(uint32_t cpregid) { uint64_t kvmid; if (cpregid & CP_REG_AA64_MASK) { kvmid = cpregid & ~CP_REG_AA64_MASK; kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; } else { kvmid = cpregid & ~(1 << 15); if (cpregid & (1 << 15)) { kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; } else { kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; } } return kvmid; } ... just happens to work the same way for HVF? > + } else { > + hvf_sreg_match[i].cp_idx = -1; > + } > + } > + arm_cpu->cpreg_array_len = sregs_cnt; > + arm_cpu->cpreg_vmstate_array_len = sregs_cnt; > + > + assert(write_cpustate_to_list(arm_cpu, false)); > + > + /* Set CP_NO_RAW system registers on init */ > + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, > + arm_cpu->midr); > + assert_hvf_ok(ret); > + > + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, > + arm_cpu->mp_affinity); > + assert_hvf_ok(ret); > + > + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); > + assert_hvf_ok(ret); > + pfr |= env->gicv3state ? (1 << 24) : 0; > + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); > + assert_hvf_ok(ret); > + > + /* We're limited to underlying hardware caps, override internal versions */ > + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, > + &arm_cpu->isar.id_aa64mmfr0); > + assert_hvf_ok(ret); > + > + return 0; > +}