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dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5488.namprd11.prod.outlook.com (2603:10b6:5:39d::5) by DM5PR11MB1850.namprd11.prod.outlook.com (2603:10b6:3:112::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4523.18; Fri, 24 Sep 2021 00:14:08 +0000 Received: from DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::450:6ab1:b0a:a165]) by DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::450:6ab1:b0a:a165%9]) with mapi id 15.20.4544.015; Fri, 24 Sep 2021 00:14:08 +0000 To: Alan Previn , CC: Chris Wilson , Rodrigo Vivi , "Belgaumkar, Vinay" References: <20210923073529.1058204-1-alan.previn.teres.alexis@intel.com> <20210923073529.1058204-5-alan.previn.teres.alexis@intel.com> From: Daniele Ceraolo Spurio Message-ID: <0bb3fff3-e39d-0339-7d79-a9cd3019a3de@intel.com> Date: Thu, 23 Sep 2021 17:14:05 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.14.0 In-Reply-To: <20210923073529.1058204-5-alan.previn.teres.alexis@intel.com> Content-Type: text/plain; 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We can also use the > presence of the context as a check of pxp initialization completion. > > v2: use perma-pinned context (Chris) > v3: rename pinned_context functions (Chris) > v4: split export of pinned_context functions to a separate patch (Rodrigo) > v10: remove inclusion of intel_gt_types.h from intel_pxp.h (Jani) > > Signed-off-by: Alan Previn > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris Wilson > Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/Makefile | 4 ++ > drivers/gpu/drm/i915/gt/intel_engine.h | 2 + > drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++ > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + > drivers/gpu/drm/i915/pxp/intel_pxp.c | 69 ++++++++++++++++++++++ > drivers/gpu/drm/i915/pxp/intel_pxp.h | 30 ++++++++++ > drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 17 ++++++ > 7 files changed, 130 insertions(+) > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 335a8c668848..c94fce9c8ddf 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -280,6 +280,10 @@ i915-y += \ > > i915-y += i915_perf.o > > +# Protected execution platform (PXP) support > +i915-$(CONFIG_DRM_I915_PXP) += \ > + pxp/intel_pxp.o > + > # Post-mortem debug and GPU hang state capture > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o > i915-$(CONFIG_DRM_I915_SELFTEST) += \ > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 87579affb952..eed4634c08cd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -175,6 +175,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) > #define I915_GEM_HWS_SEQNO 0x40 > #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) > #define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32)) > +#define I915_GEM_HWS_PXP 0x60 > +#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32)) > #define I915_GEM_HWS_SCRATCH 0x80 > > #define I915_HWS_CSB_BUF0_INDEX 0x10 > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 5753c5943ed9..88f627f014d3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -21,6 +21,7 @@ > #include "intel_rps.h" > #include "intel_uncore.h" > #include "shmem_utils.h" > +#include "pxp/intel_pxp.h" > > void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) > { > @@ -714,6 +715,8 @@ int intel_gt_init(struct intel_gt *gt) > > intel_migrate_init(>->migrate, gt); > > + intel_pxp_init(>->pxp); > + > goto out_fw; > err_gt: > __intel_gt_disable(gt); > @@ -749,6 +752,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt) > > intel_rps_driver_unregister(>->rps); > > + intel_pxp_fini(>->pxp); > + > /* > * Upon unregistering the device to prevent any new users, cancel > * all in-flight requests so that we can quickly unbind the active > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index 9f711ee0d42c..14216cc471b1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -26,6 +26,7 @@ > #include "intel_rps_types.h" > #include "intel_migrate_types.h" > #include "intel_wakeref.h" > +#include "pxp/intel_pxp_types.h" > > struct drm_i915_private; > struct i915_ggtt; > @@ -201,6 +202,8 @@ struct intel_gt { > struct { > u8 uc_index; > } mocs; > + > + struct intel_pxp pxp; > }; > > enum intel_gt_scratch_field { > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c > new file mode 100644 > index 000000000000..5031ba589d95 > --- /dev/null > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c > @@ -0,0 +1,69 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright(c) 2020 Intel Corporation. > + */ > +#include "intel_pxp.h" > +#include "gt/intel_context.h" > +#include "i915_drv.h" > + > +struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) > +{ > + return container_of(pxp, struct intel_gt, pxp); > +} > + > +static int create_vcs_context(struct intel_pxp *pxp) > +{ > + static struct lock_class_key pxp_lock; > + struct intel_gt *gt = pxp_to_gt(pxp); > + struct intel_engine_cs *engine; > + struct intel_context *ce; > + > + /* > + * Find the first VCS engine present. We're guaranteed there is one > + * if we're in this function due to the check in has_pxp > + */ > + for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0];; engine++) > + if (engine) > + break; Vinay found a silly mistake I did here: the array is an array of pointers, so engine++ doesn't work. The below chunk should work as a fix: --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -37,12 +37,15 @@ static int create_vcs_context(struct intel_pxp *pxp)         struct intel_gt *gt = pxp_to_gt(pxp);         struct intel_engine_cs *engine;         struct intel_context *ce; +       int i;         /*          * Find the first VCS engine present. We're guaranteed there is one          * if we're in this function due to the check in has_pxp          */ -       for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++); +       for (i = 0, engine = NULL; !engine; i++) +               engine = gt->engine_class[VIDEO_DECODE_CLASS][i]; +         GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);         ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, Daniele > + GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS); > + > + ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, > + I915_GEM_HWS_PXP_ADDR, > + &pxp_lock, "pxp_context"); > + if (IS_ERR(ce)) { > + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n"); > + return PTR_ERR(ce); > + } > + > + pxp->ce = ce; > + > + return 0; > +} > + > +static void destroy_vcs_context(struct intel_pxp *pxp) > +{ > + intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce)); > +} > + > +void intel_pxp_init(struct intel_pxp *pxp) > +{ > + struct intel_gt *gt = pxp_to_gt(pxp); > + int ret; > + > + if (!HAS_PXP(gt->i915)) > + return; > + > + ret = create_vcs_context(pxp); > + if (ret) > + return; > + > + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); > +} > + > +void intel_pxp_fini(struct intel_pxp *pxp) > +{ > + if (!intel_pxp_is_enabled(pxp)) > + return; > + > + destroy_vcs_context(pxp); > +} > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h > new file mode 100644 > index 000000000000..73acd879f2fb > --- /dev/null > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h > @@ -0,0 +1,30 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright(c) 2020, Intel Corporation. All rights reserved. > + */ > + > +#ifndef __INTEL_PXP_H__ > +#define __INTEL_PXP_H__ > + > +#include "intel_pxp_types.h" > + > +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp) > +{ > + return pxp->ce; > +} > + > +#ifdef CONFIG_DRM_I915_PXP > +struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); > +void intel_pxp_init(struct intel_pxp *pxp); > +void intel_pxp_fini(struct intel_pxp *pxp); > +#else > +static inline void intel_pxp_init(struct intel_pxp *pxp) > +{ > +} > + > +static inline void intel_pxp_fini(struct intel_pxp *pxp) > +{ > +} > +#endif > + > +#endif /* __INTEL_PXP_H__ */ > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h > new file mode 100644 > index 000000000000..db98df723dbb > --- /dev/null > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright(c) 2020, Intel Corporation. All rights reserved. > + */ > + > +#ifndef __INTEL_PXP_TYPES_H__ > +#define __INTEL_PXP_TYPES_H__ > + > +#include > + > +struct intel_context; > + > +struct intel_pxp { > + struct intel_context *ce; > +}; > + > +#endif /* __INTEL_PXP_TYPES_H__ */