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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Klaus Jensen <its@irrelevant.dk>, qemu-block@nongnu.org
Cc: Kevin Wolf <kwolf@redhat.com>,
	Klaus Jensen <k.jensen@samsung.com>,
	qemu-devel@nongnu.org, Max Reitz <mreitz@redhat.com>,
	Keith Busch <kbusch@kernel.org>,
	Javier Gonzalez <javier.gonz@samsung.com>,
	Maxim Levitsky <mlevitsk@redhat.com>
Subject: Re: [PATCH v6 18/20] hw/block/nvme: factor out pmr setup
Date: Thu, 14 May 2020 09:59:30 +0200	[thread overview]
Message-ID: <0c528722-0117-4842-cb5c-d37090ac71f2@redhat.com> (raw)
In-Reply-To: <20200514044611.734782-19-its@irrelevant.dk>

On 5/14/20 6:46 AM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
> 
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> ---
>   hw/block/nvme.c | 95 ++++++++++++++++++++++++++-----------------------
>   1 file changed, 51 insertions(+), 44 deletions(-)
> 
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index d71a5f142d51..7254b66ae199 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -58,6 +58,7 @@
>   #define NVME_REG_SIZE 0x1000
>   #define NVME_DB_SIZE  4
>   #define NVME_CMB_BIR 2
> +#define NVME_PMR_BIR 2
>   
>   #define NVME_GUEST_ERR(trace, fmt, ...) \
>       do { \
> @@ -1463,6 +1464,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
>                        PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
>   }
>   
> +static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
> +{
> +    /* Controller Capabilities register */
> +    NVME_CAP_SET_PMRS(n->bar.cap, 1);
> +
> +    /* PMR Capabities register */
> +    n->bar.pmrcap = 0;
> +    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
> +    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> +    /* Turn on bit 1 support */
> +    NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
> +    NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
> +
> +    /* PMR Control register */
> +    n->bar.pmrctl = 0;
> +    NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
> +
> +    /* PMR Status register */
> +    n->bar.pmrsts = 0;
> +    NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
> +
> +    /* PMR Elasticity Buffer Size register */
> +    n->bar.pmrebs = 0;
> +    NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
> +    NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
> +    NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
> +
> +    /* PMR Sustained Write Throughput register */
> +    n->bar.pmrswtp = 0;
> +    NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
> +    NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
> +
> +    /* PMR Memory Space Control register */
> +    n->bar.pmrmsc = 0;
> +    NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
> +    NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
> +
> +    pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
> +                     PCI_BASE_ADDRESS_SPACE_MEMORY |
> +                     PCI_BASE_ADDRESS_MEM_TYPE_64 |
> +                     PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
> +}
> +
>   static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
>   {
>       uint8_t *pci_conf = pci_dev->config;
> @@ -1541,50 +1591,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
>       if (n->params.cmb_size_mb) {
>           nvme_init_cmb(n, pci_dev);
>       } else if (n->pmrdev) {
> -        /* Controller Capabilities register */
> -        NVME_CAP_SET_PMRS(n->bar.cap, 1);
> -
> -        /* PMR Capabities register */
> -        n->bar.pmrcap = 0;
> -        NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
> -        NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> -        /* Turn on bit 1 support */
> -        NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
> -        NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
> -
> -        /* PMR Control register */
> -        n->bar.pmrctl = 0;
> -        NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
> -
> -        /* PMR Status register */
> -        n->bar.pmrsts = 0;
> -        NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
> -
> -        /* PMR Elasticity Buffer Size register */
> -        n->bar.pmrebs = 0;
> -        NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
> -        NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
> -        NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
> -
> -        /* PMR Sustained Write Throughput register */
> -        n->bar.pmrswtp = 0;
> -        NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
> -        NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
> -
> -        /* PMR Memory Space Control register */
> -        n->bar.pmrmsc = 0;
> -        NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
> -        NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
> -
> -        pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
> -            PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
> -            PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
> +        nvme_init_pmr(n, pci_dev);
>       }
>   
>       for (i = 0; i < n->num_namespaces; i++) {
> 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>



  reply	other threads:[~2020-05-14  8:00 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-14  4:45 [PATCH v6 00/20] nvme: small fixes, refactoring and cleanups Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 01/20] hw/block/nvme: fix pci doorbell size calculation Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 02/20] hw/block/nvme: rename trace events to pci_nvme Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 03/20] hw/block/nvme: remove superfluous breaks Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 04/20] hw/block/nvme: move device parameters to separate struct Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 05/20] hw/block/nvme: use constants in identify Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 06/20] hw/block/nvme: refactor nvme_addr_read Klaus Jensen
2020-05-14  4:45 ` [PATCH v6 07/20] hw/block/nvme: fix pin-based interrupt behavior Klaus Jensen
2020-05-18  5:02   ` Klaus Jensen
2020-05-25  8:20     ` Klaus Jensen
2020-05-26 14:45   ` Keith Busch
2020-05-14  4:45 ` [PATCH v6 08/20] hw/block/nvme: allow use of any valid msix vector Klaus Jensen
2020-05-28 15:44   ` Philippe Mathieu-Daudé
2020-06-02 16:06     ` Philippe Mathieu-Daudé
2020-05-14  4:46 ` [PATCH v6 09/20] hw/block/nvme: add max_ioqpairs device parameter Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 10/20] hw/block/nvme: remove redundant cmbloc/cmbsz members Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 11/20] hw/block/nvme: factor out property/constraint checks Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 12/20] hw/block/nvme: factor out device state setup Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 13/20] hw/block/nvme: factor out block backend setup Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 14/20] hw/block/nvme: add namespace helpers Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 15/20] hw/block/nvme: factor out namespace setup Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 16/20] hw/block/nvme: factor out pci setup Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 17/20] hw/block/nvme: factor out cmb setup Klaus Jensen
2020-05-14  4:46 ` [PATCH v6 18/20] hw/block/nvme: factor out pmr setup Klaus Jensen
2020-05-14  7:59   ` Philippe Mathieu-Daudé [this message]
2020-05-14  4:46 ` [PATCH v6 19/20] hw/block/nvme: do cmb/pmr init as part of pci init Klaus Jensen
2020-05-14  8:04   ` Philippe Mathieu-Daudé
2020-05-14  4:46 ` [PATCH v6 20/20] hw/block/nvme: factor out controller identify setup Klaus Jensen
2020-06-02 15:31 ` [PATCH v6 00/20] nvme: small fixes, refactoring and cleanups Kevin Wolf
2020-06-07 12:51   ` Maxim Levitsky
2020-06-07 13:08     ` Maxim Levitsky

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