From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dalon L Westergreen Date: Tue, 12 Feb 2019 05:49:50 -0800 Subject: [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 In-Reply-To: <5a03dfd2-06bd-2be4-082f-487daaa1660c@denx.de> References: <1548946304-17460-1-git-send-email-tien.fong.chee@intel.com> <1548946304-17460-2-git-send-email-tien.fong.chee@intel.com> <1548992898.11133.13.camel@intel.com> <581c2c6c-eb0c-8f31-dbba-a966cb93ba27@denx.de> <1549036942.11363.34.camel@intel.com> <22489ae2-80e1-1ece-c241-ee07277f62d5@denx.de> <1549863369.10080.22.camel@intel.com> <1ee58ccd-d7b3-850b-1b5b-c06a71356db6@denx.de> <1549904509.10080.82.camel@intel.com> <5d760e925f48aca5a20e3419c90bbfbcb36a0179.camel@intel.com> <1549964128.10168.5.camel@intel.com> <1549966432.10168.9.camel@intel.com> <5a03dfd2-06bd-2be4-082f-487daaa1660c@denx.de> Message-ID: <0c6e5ee06f9c884c4e4b8f8c5e26f3d7fd32a2f1.camel@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote: > On 2/12/19 11:13 AM, Chee, Tien Fong wrote: > > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote: > > > On 2/12/19 10:35 AM, Chee, Tien Fong wrote: > > > [...] > > > > > > > > my preference for the fit image would be > > > > > > > > > > ... > > > > > images { > > > > > fpga at 1 { > > > > > description = "FPGA Periph"; > > > > > ... > > > > > type = "fpga_periph"; > > > > > ... > > > > > } > > > > > fpga at 2 { > > > > > description = "FPGA Core"; > > > > > ... > > > > > type = "fpga" or > > > > > "fpga_core"; > > > > I'm good with "fpga". > > > > > ... > > > > > } > > > > > }; > > > > > configurations { > > > > > default = "config at 1" > > > > > config at 1 { > > > > > fpga = "fpga at 1"; // periph only > > > > > }; > > > > > config at 2 { > > > > > fpga = "fpga at 1", "fpga at 2"; > > > > > }; > > > > > }; > > > > > > > > > > with the expectation that the order of fpga at 1 and fpga at 2 in confi > > > > > g at 2 > > > > > is not relevant. the code should find the fpga_periph type and > > > > > program > > > > > it first. just my comment, i dont like rellying on the order or > > > > > name. > > > > I can add support for above implementation although this adds more > > > > complexity to the driver. > > > You can have fpga node and e.g. fpga-name node in the configurations > > > section to discern which phandle there is the core and which is the > > > peripheral RBF. Would that work ? > > > > > So something like that? > > > > ... > > > > images { > > fpga-periph at 1 { > > description = "FPGA Periph"; > > ... > > type = "fpga_periph"; > > Do we need a new type for the periph/core distinction ? not really, using the node name is fine with me as is shown below. when i suggested that my intent was to allow the name to be independant of the node name still envisioning scenarios where the fit image has multiple fpga images. > > > ... > > } > > fpga-core at 2 { > > description = "FPGA Core"; > > ... > > type = "fpga"; > > ... > > } > > }; > > configurations { > > default = "config at 1" > > config at 1 { > > fpga = "fpga-periph at 1"; // periph only > > }; > > config at 2 { > > fpga = "fpga-periph at 1", "fpga-core at 2"; > > }; > > }; > > > > > > Marek, are you OK with this implementation? > > > Looks OK to me. Dalon ? > > > > > > [...] > >