From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B48CC432BE for ; Wed, 1 Sep 2021 14:33:10 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1681C61057 for ; Wed, 1 Sep 2021 14:33:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1681C61057 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0E0B6834CD; Wed, 1 Sep 2021 16:33:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1630506786; bh=s1Usb+f+S32er/m7M5NGzQgl7LkJUthkKn07TOHmIZg=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ywQKvsI87+uIXeDn5hvxAE9lhj6Xqy4us7GsuTT7BGfbj85xxI9GQu6ghUnYl4TZ6 I1aDOMk7FF5KEBmHws9oOJLhIdRoZ7uuNRg95oz2wSW7Z1FH313vsZ+gPCjP11ofv7 cvZ+F/w7NIQHWe1vMJkKQYOTWmJMWoGaP+dseeAdPPMx8fzxzKiSwhkj1SjOKsRLF2 twcPMzQuNw9b5cPP+HmQtmQH0Mk4SEJQlxnYMwh12+hrXnEYbdzYOx7v/xuIbOGy0a bDKYDuV/Xx8n7fXfyVfAut201A9iot/bazj8kdqvj7qiI9V7OLBwJcXgy6izHG16Tz IlylAKEdtSQnw== Received: by phobos.denx.de (Postfix, from userid 109) id 052EB832A1; Wed, 1 Sep 2021 16:33:03 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 526CC832A1 for ; Wed, 1 Sep 2021 16:32:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:105:465:1:1:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4H063b1SlGzQkHF; Wed, 1 Sep 2021 16:32:59 +0200 (CEST) Subject: Re: [PATCH 4/9] mvebu: ddr: Rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE To: Tom Rini Cc: u-boot@lists.denx.de, =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20210821175019.24180-1-trini@konsulko.com> <20210821175019.24180-4-trini@konsulko.com> <30126d52-96c9-7d75-b1f6-69b79227402e@denx.de> <20210831124303.GB858@bill-the-cat> <20210901112925.GW858@bill-the-cat> From: Stefan Roese Message-ID: <0cc9f13c-0113-98c4-6301-6d35920baf29@denx.de> Date: Wed, 1 Sep 2021 16:32:55 +0200 MIME-Version: 1.0 In-Reply-To: <20210901112925.GW858@bill-the-cat> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 498021898 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 01.09.21 13:29, Tom Rini wrote: > On Wed, Sep 01, 2021 at 07:27:54AM +0200, Stefan Roese wrote: >> Hi Tom, >> >> On 31.08.21 14:43, Tom Rini wrote: >>> On Tue, Aug 31, 2021 at 07:51:29AM +0200, Stefan Roese wrote: >>>> Hi Tom, >>>> >>>> On 21.08.21 19:50, Tom Rini wrote: >>>>> We have a number of CONFIG symbols to express the fixed size of system >>>>> memory. For now, rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE >>>>> and adjust usage to match that CONFIG_SYS_SDRAM_SIZE expects the entire >>>>> size rather than MiB. >>>>> >>>>> Cc: Marek Behún >>>>> Cc: Stefan Roese >>>>> Signed-off-by: Tom Rini >>>>> --- >>>>> drivers/ddr/marvell/axp/ddr3_axp.h | 4 ++-- >>>>> include/configs/maxbcm.h | 4 +++- >>>>> include/configs/theadorable.h | 4 +++- >>>>> 3 files changed, 8 insertions(+), 4 deletions(-) >>>>> >>>>> diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h >>>>> index 270691e9bcd3..970651f87029 100644 >>>>> --- a/drivers/ddr/marvell/axp/ddr3_axp.h >>>>> +++ b/drivers/ddr/marvell/axp/ddr3_axp.h >>>>> @@ -19,10 +19,10 @@ >>>>> #define FAR_END_DIMM_ADDR 0x50 >>>>> #define MAX_DIMM_ADDR 0x60 >>>>> -#ifndef CONFIG_DDR_FIXED_SIZE >>>>> +#ifndef CONFIG_SYS_SDRAM_SIZE >>>>> #define SDRAM_CS_SIZE 0xFFFFFFF >>>>> #else >>>>> -#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) >>>>> +#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) >>>> >>>> Why are you using ">> 10" (dividing by 1024) here? >>>> >>>> Thanks, >>>> Stefan >>>> >>>>> #endif >>>>> #define SDRAM_CS_BASE 0x0 >>>>> #define SDRAM_DIMM_SIZE 0x80000000 >>>>> diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h >>>>> index fc2393204bec..5098f12f5425 100644 >>>>> --- a/include/configs/maxbcm.h >>>>> +++ b/include/configs/maxbcm.h >>>>> @@ -6,6 +6,8 @@ >>>>> #ifndef _CONFIG_DB_MV7846MP_GP_H >>>>> #define _CONFIG_DB_MV7846MP_GP_H >>>>> +#include >>>>> + >>>>> /* >>>>> * High Level Configuration Options (easy to change) >>>>> */ >>>>> @@ -65,7 +67,7 @@ >>>>> /* SPL related SPI defines */ >>>>> /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ >>>>> -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ >>>>> +#define CONFIG_SYS_SDRAM_SIZE SZ_1G >>> >>> OK, so before my change, SDRAM_CS_SIZE = 0xfffff. After my change, >>> SDRAM_CS_SIZE = 0xfffff, still. >>> >>>>> #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ >>>>> #endif /* _CONFIG_DB_MV7846MP_GP_H */ >>>>> diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h >>>>> index 760713d3ef87..abc48ff44ca5 100644 >>>>> --- a/include/configs/theadorable.h >>>>> +++ b/include/configs/theadorable.h >>>>> @@ -6,6 +6,8 @@ >>>>> #ifndef _CONFIG_THEADORABLE_H >>>>> #define _CONFIG_THEADORABLE_H >>>>> +#include >>>>> + >>>>> /* >>>>> * High Level Configuration Options (easy to change) >>>>> */ >>>>> @@ -93,6 +95,6 @@ >>>>> #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) >>>>> /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ >>>>> -#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ >>>>> +#define CONFIG_SYS_SDRAM_SIZE SZ_2G >>> >>> Here, before SDRAM_CS_SIZE = 0x1fffff and then after SDRAM_CS_SIZE = >>> 0x1fffff. >>> >>> This is because CONFIG_DDR_FIXED_SIZE is kilobytes and >>> CONFIG_SYS_SDRAM_SIZE is bytes, yes? Thanks. >> >> Only if CONFIG_DDR_FIXED_SIZE / CONFIG_SYS_SDRAM_SIZE is undefined. >> >> Please see e.g. theadorable.h above. Here we have: >> >> #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ >> >> With this, the following will happen in ddr3_axp.h: >> >> #ifndef CONFIG_DDR_FIXED_SIZE >> #define SDRAM_CS_SIZE 0xFFFFFFF >> #else >> #define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) >> #endif >> >> So SDRAM_CS_SIZE will be set to "(2 << 20) - 1". >> >> AFAICT, on Armada XP CONFIG_DDR_FIXED_SIZE is bytes and not >> kilobytes. > > I'm not follow, sorry. There's exactly two defines of > CONFIG_DDR_FIXED_SIZE before this patch, neither platform also set > CONFIG_SYS_SDRAM_SIZE, and they're converted to CONFIG_SYS_SDRAM_SIZE > now. I did the evaluations to confirm the code is unchanged. Ah, now I see my misunderstanding. "2 << 20" is of course 2MiB and not 2GiB. I was mislead by the comment in the header. But now I'm thinking that SDRAM_CS_SIZE might need to be set to the CS size in bytes and *not* in kilobytes for Armada XP. But this is a different issue which I need to investigate and perhaps follow up on. Thanks, Stefan