From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C466C43381 for ; Fri, 22 Mar 2019 10:19:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46EB921902 for ; Fri, 22 Mar 2019 10:19:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vUAB5REX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727971AbfCVKT4 (ORCPT ); Fri, 22 Mar 2019 06:19:56 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:35298 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727713AbfCVKT4 (ORCPT ); Fri, 22 Mar 2019 06:19:56 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2MAJjR5102737; Fri, 22 Mar 2019 05:19:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553249985; bh=qbYELvE+I7ZlMz2t0Wa9poruOHu09gV6Yb53Pzj3oPQ=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=vUAB5REXBTtd14OkX5vMnwQTgqPBLRpCabT/UOw2FVa667vM6zovUW/PAMnNA13fU TCjnqY2kOakdvZij1pevADX9iwoT708Hu1VML4v3x67Vg5EqRCMIYV3cs2R66XBmNt jF82oSpgrJv4JiMKCQYwbOKefHZq9yBUupylWKHg= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2MAJjKH075751 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 22 Mar 2019 05:19:45 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 22 Mar 2019 05:19:44 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Fri, 22 Mar 2019 05:19:44 -0500 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2MAJfIN028214; Fri, 22 Mar 2019 05:19:42 -0500 Subject: Re: [PATCH v2 04/15] drm/bridge: tc358767: Simplify tc_set_video_mode() To: Andrey Smirnov , CC: Archit Taneja , Andrzej Hajda , Laurent Pinchart , Andrey Gusakov , Philipp Zabel , Chris Healy , Lucas Stach , References: <20190322032901.12045-1-andrew.smirnov@gmail.com> <20190322032901.12045-5-andrew.smirnov@gmail.com> From: Tomi Valkeinen Message-ID: <0d08d4e0-ff1d-ae14-e8f8-696c7448fcb1@ti.com> Date: Fri, 22 Mar 2019 12:19:41 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <20190322032901.12045-5-andrew.smirnov@gmail.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/03/2019 05:28, Andrey Smirnov wrote: > Simplify tc_set_video_mode() by replacing repreated calls to > tc_write()/regmap_write() with a single call to > regmap_multi_reg_write(). While at it, simplify explicit shifting by > using macros from . No functional change intended. > > Signed-off-by: Andrey Smirnov > Cc: Archit Taneja > Cc: Andrzej Hajda > Cc: Laurent Pinchart > Cc: Tomi Valkeinen > Cc: Andrey Gusakov > Cc: Philipp Zabel > Cc: Chris Healy > Cc: Lucas Stach > Cc: dri-devel@lists.freedesktop.org > Cc: linux-kernel@vger.kernel.org > --- > drivers/gpu/drm/bridge/tc358767.c | 146 +++++++++++++++++------------- > 1 file changed, 85 insertions(+), 61 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index 38d542f553cd..d99c9f32a133 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -24,6 +24,7 @@ > * GNU General Public License for more details. > */ > > +#include > #include > #include > #include > @@ -56,6 +57,7 @@ > > /* Video Path */ > #define VPCTRL0 0x0450 > +#define VSDELAY GENMASK(31, 20) > #define OPXLFMT_RGB666 (0 << 8) > #define OPXLFMT_RGB888 (1 << 8) > #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ > @@ -63,9 +65,17 @@ > #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ > #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ > #define HTIM01 0x0454 > +#define HPW GENMASK(8, 0) > +#define HBPR GENMASK(24, 16) > #define HTIM02 0x0458 > +#define HDISPR GENMASK(10, 0) > +#define HFPR GENMASK(24, 16) > #define VTIM01 0x045c > +#define VSPR GENMASK(7, 0) > +#define VBPR GENMASK(23, 16) > #define VTIM02 0x0460 > +#define VFPR GENMASK(23, 16) > +#define VDISPR GENMASK(10, 0) > #define VFUEN0 0x0464 > #define VFUEN BIT(0) /* Video Frame Timing Upload */ > > @@ -100,14 +110,28 @@ > /* Main Channel */ > #define DP0_SECSAMPLE 0x0640 > #define DP0_VIDSYNCDELAY 0x0644 > +#define VID_SYNC_DLY GENMASK(15, 0) > +#define THRESH_DLY GENMASK(31, 16) > + > #define DP0_TOTALVAL 0x0648 > +#define H_TOTAL GENMASK(15, 0) > +#define V_TOTAL GENMASK(31, 16) > #define DP0_STARTVAL 0x064c > +#define H_START GENMASK(15, 0) > +#define V_START GENMASK(31, 16) > #define DP0_ACTIVEVAL 0x0650 > +#define H_ACT GENMASK(15, 0) > +#define V_ACT GENMASK(31, 16) > + > #define DP0_SYNCVAL 0x0654 > +#define VS_WIDTH GENMASK(30, 16) > +#define HS_WIDTH GENMASK(14, 0) > #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) > #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) > #define DP0_MISC 0x0658 > #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ > +#define MAX_TU_SYMBOL GENMASK(28, 23) > +#define TU_SIZE GENMASK(21, 16) > #define BPC_6 (0 << 5) > #define BPC_8 (1 << 5) > > @@ -184,6 +208,12 @@ > > /* Test & Debug */ > #define TSTCTL 0x0a00 > +#define COLOR_R GENMASK(31, 24) > +#define COLOR_G GENMASK(23, 16) > +#define COLOR_B GENMASK(15, 8) > +#define ENI2CFILTER BIT(4) > +#define COLOR_BAR_MODE GENMASK(1, 0) > +#define COLOR_BAR_MODE_BARS 2 > #define PLL_DBG 0x0a04 > > static bool tc_test_pattern; > @@ -647,10 +677,6 @@ static int tc_get_display_props(struct tc_data *tc) > > static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode) > { > - int ret; > - int vid_sync_dly; > - int max_tu_symbol; > - > int left_margin = mode->htotal - mode->hsync_end; > int right_margin = mode->hsync_start - mode->hdisplay; > int hsync_len = mode->hsync_end - mode->hsync_start; > @@ -659,76 +685,74 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode) > int vsync_len = mode->vsync_end - mode->vsync_start; > > /* > - * Recommended maximum number of symbols transferred in a transfer unit: > + * Recommended maximum number of symbols transferred in a > + * transfer unit: > * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, > * (output active video bandwidth in bytes)) > * Must be less than tu_size. > */ > - max_tu_symbol = TU_SIZE_RECOMMENDED - 1; > - > - dev_dbg(tc->dev, "set mode %dx%d\n", > - mode->hdisplay, mode->vdisplay); > - dev_dbg(tc->dev, "H margin %d,%d sync %d\n", > - left_margin, right_margin, hsync_len); > - dev_dbg(tc->dev, "V margin %d,%d sync %d\n", > - upper_margin, lower_margin, vsync_len); > - dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); > - > + int max_tu_symbol = TU_SIZE_RECOMMENDED - 1; > > + /* DP Main Stream Attributes */ > + int vid_sync_dly = hsync_len + left_margin + mode->hdisplay; > /* > * LCD Ctl Frame Size > * datasheet is not clear of vsdelay in case of DPI > * assume we do not need any delay when DPI is a source of > * sync signals > */ > - tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | > - OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); > - tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ > - (ALIGN(hsync_len, 2) << 0)); /* Hsync */ > - tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ > - (ALIGN(mode->hdisplay, 2) << 0)); /* width */ > - tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ > - (vsync_len << 0)); /* Vsync */ > - tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ > - (mode->vdisplay << 0)); /* height */ > - tc_write(VFUEN0, VFUEN); /* update settings */ > - > - /* Test pattern settings */ > - tc_write(TSTCTL, > - (120 << 24) | /* Red Color component value */ > - (20 << 16) | /* Green Color component value */ > - (99 << 8) | /* Blue Color component value */ > - (1 << 4) | /* Enable I2C Filter */ > - (2 << 0) | /* Color bar Mode */ > - 0); > - > - /* DP Main Stream Attributes */ > - vid_sync_dly = hsync_len + left_margin + mode->hdisplay; > - tc_write(DP0_VIDSYNCDELAY, > - (max_tu_symbol << 16) | /* thresh_dly */ > - (vid_sync_dly << 0)); > + const u32 vs_pol = mode->flags & DRM_MODE_FLAG_NVSYNC ? > + SYNCVAL_VS_POL_ACTIVE_LOW : 0; > + const u32 hs_pol = mode->flags & DRM_MODE_FLAG_NHSYNC ? > + SYNCVAL_HS_POL_ACTIVE_LOW : 0; > + const struct reg_sequence video_mode_settings[] = { > + { VPCTRL0, FIELD_PREP(VSDELAY, 0) | > + OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED }, > + { HTIM01, FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | > + FIELD_PREP(HPW, ALIGN(hsync_len, 2)) }, > + { HTIM02, FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | > + FIELD_PREP(HFPR, ALIGN(right_margin, 2)) }, > + { VTIM01, FIELD_PREP(VBPR, upper_margin) | > + FIELD_PREP(VSPR, vsync_len) }, > + { VTIM02, FIELD_PREP(VFPR, lower_margin) | > + FIELD_PREP(VDISPR, mode->vdisplay) }, > + { VFUEN0, VFUEN }, > + { TSTCTL, FIELD_PREP(COLOR_R, 120) | > + FIELD_PREP(COLOR_G, 20) | > + FIELD_PREP(COLOR_B, 99) | > + ENI2CFILTER | > + FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS) }, > + { DP0_VIDSYNCDELAY, FIELD_PREP(THRESH_DLY, max_tu_symbol) | > + FIELD_PREP(VID_SYNC_DLY, vid_sync_dly) }, > + { DP0_TOTALVAL, FIELD_PREP(H_TOTAL, mode->htotal) | > + FIELD_PREP(V_TOTAL, mode->vtotal) }, > + { DP0_STARTVAL, FIELD_PREP(H_START, left_margin + hsync_len) | > + FIELD_PREP(V_START, > + upper_margin + vsync_len) }, > + { DP0_ACTIVEVAL, FIELD_PREP(V_ACT, mode->vdisplay) | > + FIELD_PREP(H_ACT, mode->hdisplay) }, > + { DP0_SYNCVAL, FIELD_PREP(VS_WIDTH, vsync_len) | > + FIELD_PREP(HS_WIDTH, hsync_len) | > + hs_pol | vs_pol }, > + { DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | > + DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | > + DPI_BPP_RGB888 }, > + { DP0_MISC, FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | > + FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | > + BPC_8 }, > + }; > > - tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); > - > - tc_write(DP0_STARTVAL, > - ((upper_margin + vsync_len) << 16) | > - ((left_margin + hsync_len) << 0)); > - > - tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); > - > - tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | > - ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | > - ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); > - > - tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | > - DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); > - > - tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | > - BPC_8); > + dev_dbg(tc->dev, "set mode %dx%d\n", > + mode->hdisplay, mode->vdisplay); > + dev_dbg(tc->dev, "H margin %d,%d sync %d\n", > + left_margin, right_margin, hsync_len); > + dev_dbg(tc->dev, "V margin %d,%d sync %d\n", > + upper_margin, lower_margin, vsync_len); > + dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); > > - return 0; > -err: > - return ret; > + return regmap_multi_reg_write(tc->regmap, > + video_mode_settings, > + ARRAY_SIZE(video_mode_settings)); > } > > static int tc_wait_link_training(struct tc_data *tc, u32 *error) I don't like this change. I think multi_reg_write is good for writing things like, say, color conversion table. But the data for video mode is more complex and needs more logic (e.g. here ?: operator is used). You need to stuff all that logic into variable initializers. You can't use e.g. if() anymore, and you can't even insert a debug print between the writes if you need to. So, in my opinion, this doesn't look (much) cleaner, and makes life more difficult. Tomi -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomi Valkeinen Subject: Re: [PATCH v2 04/15] drm/bridge: tc358767: Simplify tc_set_video_mode() Date: Fri, 22 Mar 2019 12:19:41 +0200 Message-ID: <0d08d4e0-ff1d-ae14-e8f8-696c7448fcb1@ti.com> References: <20190322032901.12045-1-andrew.smirnov@gmail.com> <20190322032901.12045-5-andrew.smirnov@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE97C892B6 for ; Fri, 22 Mar 2019 10:19:49 +0000 (UTC) In-Reply-To: <20190322032901.12045-5-andrew.smirnov@gmail.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Andrey Smirnov , dri-devel@lists.freedesktop.org Cc: Andrey Gusakov , linux-kernel@vger.kernel.org, Laurent Pinchart , Chris Healy List-Id: dri-devel@lists.freedesktop.org T24gMjIvMDMvMjAxOSAwNToyOCwgQW5kcmV5IFNtaXJub3Ygd3JvdGU6Cj4gU2ltcGxpZnkgdGNf c2V0X3ZpZGVvX21vZGUoKSBieSByZXBsYWNpbmcgcmVwcmVhdGVkIGNhbGxzIHRvCj4gdGNfd3Jp dGUoKS9yZWdtYXBfd3JpdGUoKSB3aXRoIGEgc2luZ2xlIGNhbGwgdG8KPiByZWdtYXBfbXVsdGlf cmVnX3dyaXRlKCkuIFdoaWxlIGF0IGl0LCBzaW1wbGlmeSBleHBsaWNpdCBzaGlmdGluZyBieQo+ IHVzaW5nIG1hY3JvcyBmcm9tIDxsaW51eC9iaXRmaWVsZC5oPi4gTm8gZnVuY3Rpb25hbCBjaGFu Z2UgaW50ZW5kZWQuCj4gCj4gU2lnbmVkLW9mZi1ieTogQW5kcmV5IFNtaXJub3YgPGFuZHJldy5z bWlybm92QGdtYWlsLmNvbT4KPiBDYzogQXJjaGl0IFRhbmVqYSA8YXJjaGl0dEBjb2RlYXVyb3Jh Lm9yZz4KPiBDYzogQW5kcnplaiBIYWpkYSA8YS5oYWpkYUBzYW1zdW5nLmNvbT4KPiBDYzogTGF1 cmVudCBQaW5jaGFydCA8TGF1cmVudC5waW5jaGFydEBpZGVhc29uYm9hcmQuY29tPgo+IENjOiBU b21pIFZhbGtlaW5lbiA8dG9taS52YWxrZWluZW5AdGkuY29tPgo+IENjOiBBbmRyZXkgR3VzYWtv diA8YW5kcmV5Lmd1c2Frb3ZAY29nZW50ZW1iZWRkZWQuY29tPgo+IENjOiBQaGlsaXBwIFphYmVs IDxwLnphYmVsQHBlbmd1dHJvbml4LmRlPgo+IENjOiBDaHJpcyBIZWFseSA8Y3BoZWFseUBnbWFp bC5jb20+Cj4gQ2M6IEx1Y2FzIFN0YWNoIDxsLnN0YWNoQHBlbmd1dHJvbml4LmRlPgo+IENjOiBk cmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gQ2M6IGxpbnV4LWtlcm5lbEB2Z2VyLmtl cm5lbC5vcmcKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2JyaWRnZS90YzM1ODc2Ny5jIHwgMTQ2 ICsrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLQo+ICAxIGZpbGUgY2hhbmdlZCwgODUgaW5z ZXJ0aW9ucygrKSwgNjEgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1 L2RybS9icmlkZ2UvdGMzNTg3NjcuYyBiL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvdGMzNTg3Njcu Ywo+IGluZGV4IDM4ZDU0MmY1NTNjZC4uZDk5YzlmMzJhMTMzIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9icmlkZ2UvdGMzNTg3NjcuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9icmlk Z2UvdGMzNTg3NjcuYwo+IEBAIC0yNCw2ICsyNCw3IEBACj4gICAqIEdOVSBHZW5lcmFsIFB1Ymxp YyBMaWNlbnNlIGZvciBtb3JlIGRldGFpbHMuCj4gICAqLwo+ICAKPiArI2luY2x1ZGUgPGxpbnV4 L2JpdGZpZWxkLmg+Cj4gICNpbmNsdWRlIDxsaW51eC9jbGsuaD4KPiAgI2luY2x1ZGUgPGxpbnV4 L2RldmljZS5oPgo+ICAjaW5jbHVkZSA8bGludXgvZ3Bpby9jb25zdW1lci5oPgo+IEBAIC01Niw2 ICs1Nyw3IEBACj4gIAo+ICAvKiBWaWRlbyBQYXRoICovCj4gICNkZWZpbmUgVlBDVFJMMAkJCTB4 MDQ1MAo+ICsjZGVmaW5lIFZTREVMQVkJCQlHRU5NQVNLKDMxLCAyMCkKPiAgI2RlZmluZSBPUFhM Rk1UX1JHQjY2NgkJCSgwIDw8IDgpCj4gICNkZWZpbmUgT1BYTEZNVF9SR0I4ODgJCQkoMSA8PCA4 KQo+ICAjZGVmaW5lIEZSTVNZTkNfRElTQUJMRUQJCSgwIDw8IDQpIC8qIFZpZGVvIFRpbWluZyBH ZW4gRGlzYWJsZWQgKi8KPiBAQCAtNjMsOSArNjUsMTcgQEAKPiAgI2RlZmluZSBNU0ZfRElTQUJM RUQJCQkoMCA8PCAwKSAvKiBNYWdpYyBTcXVhcmUgRlJDIGRpc2FibGVkICovCj4gICNkZWZpbmUg TVNGX0VOQUJMRUQJCQkoMSA8PCAwKSAvKiBNYWdpYyBTcXVhcmUgRlJDIGVuYWJsZWQgKi8KPiAg I2RlZmluZSBIVElNMDEJCQkweDA0NTQKPiArI2RlZmluZSBIUFcJCQlHRU5NQVNLKDgsIDApCj4g KyNkZWZpbmUgSEJQUgkJCUdFTk1BU0soMjQsIDE2KQo+ICAjZGVmaW5lIEhUSU0wMgkJCTB4MDQ1 OAo+ICsjZGVmaW5lIEhESVNQUgkJCUdFTk1BU0soMTAsIDApCj4gKyNkZWZpbmUgSEZQUgkJCUdF Tk1BU0soMjQsIDE2KQo+ICAjZGVmaW5lIFZUSU0wMQkJCTB4MDQ1Ywo+ICsjZGVmaW5lIFZTUFIJ CQlHRU5NQVNLKDcsIDApCj4gKyNkZWZpbmUgVkJQUgkJCUdFTk1BU0soMjMsIDE2KQo+ICAjZGVm aW5lIFZUSU0wMgkJCTB4MDQ2MAo+ICsjZGVmaW5lIFZGUFIJCQlHRU5NQVNLKDIzLCAxNikKPiAr I2RlZmluZSBWRElTUFIJCQlHRU5NQVNLKDEwLCAwKQo+ICAjZGVmaW5lIFZGVUVOMAkJCTB4MDQ2 NAo+ICAjZGVmaW5lIFZGVUVOCQkJCUJJVCgwKSAgIC8qIFZpZGVvIEZyYW1lIFRpbWluZyBVcGxv YWQgKi8KPiAgCj4gQEAgLTEwMCwxNCArMTEwLDI4IEBACj4gIC8qIE1haW4gQ2hhbm5lbCAqLwo+ ICAjZGVmaW5lIERQMF9TRUNTQU1QTEUJCTB4MDY0MAo+ICAjZGVmaW5lIERQMF9WSURTWU5DREVM QVkJMHgwNjQ0Cj4gKyNkZWZpbmUgVklEX1NZTkNfRExZCQlHRU5NQVNLKDE1LCAwKQo+ICsjZGVm aW5lIFRIUkVTSF9ETFkJCUdFTk1BU0soMzEsIDE2KQo+ICsKPiAgI2RlZmluZSBEUDBfVE9UQUxW QUwJCTB4MDY0OAo+ICsjZGVmaW5lIEhfVE9UQUwJCQlHRU5NQVNLKDE1LCAwKQo+ICsjZGVmaW5l IFZfVE9UQUwJCQlHRU5NQVNLKDMxLCAxNikKPiAgI2RlZmluZSBEUDBfU1RBUlRWQUwJCTB4MDY0 Ywo+ICsjZGVmaW5lIEhfU1RBUlQJCQlHRU5NQVNLKDE1LCAwKQo+ICsjZGVmaW5lIFZfU1RBUlQJ CQlHRU5NQVNLKDMxLCAxNikKPiAgI2RlZmluZSBEUDBfQUNUSVZFVkFMCQkweDA2NTAKPiArI2Rl ZmluZSBIX0FDVAkJCUdFTk1BU0soMTUsIDApCj4gKyNkZWZpbmUgVl9BQ1QJCQlHRU5NQVNLKDMx LCAxNikKPiArCj4gICNkZWZpbmUgRFAwX1NZTkNWQUwJCTB4MDY1NAo+ICsjZGVmaW5lIFZTX1dJ RFRICQlHRU5NQVNLKDMwLCAxNikKPiArI2RlZmluZSBIU19XSURUSAkJR0VOTUFTSygxNCwgMCkK PiAgI2RlZmluZSBTWU5DVkFMX0hTX1BPTF9BQ1RJVkVfTE9XCSgxIDw8IDE1KQo+ICAjZGVmaW5l IFNZTkNWQUxfVlNfUE9MX0FDVElWRV9MT1cJKDEgPDwgMzEpCj4gICNkZWZpbmUgRFAwX01JU0MJ CTB4MDY1OAo+ICAjZGVmaW5lIFRVX1NJWkVfUkVDT01NRU5ERUQJCSg2MykgLyogTFNDTEsgY3lj bGVzIHBlciBUVSAqLwo+ICsjZGVmaW5lIE1BWF9UVV9TWU1CT0wJCUdFTk1BU0soMjgsIDIzKQo+ ICsjZGVmaW5lIFRVX1NJWkUJCQlHRU5NQVNLKDIxLCAxNikKPiAgI2RlZmluZSBCUENfNgkJCQko MCA8PCA1KQo+ICAjZGVmaW5lIEJQQ184CQkJCSgxIDw8IDUpCj4gIAo+IEBAIC0xODQsNiArMjA4 LDEyIEBACj4gIAo+ICAvKiBUZXN0ICYgRGVidWcgKi8KPiAgI2RlZmluZSBUU1RDVEwJCQkweDBh MDAKPiArI2RlZmluZSBDT0xPUl9SCQkJR0VOTUFTSygzMSwgMjQpCj4gKyNkZWZpbmUgQ09MT1Jf RwkJCUdFTk1BU0soMjMsIDE2KQo+ICsjZGVmaW5lIENPTE9SX0IJCQlHRU5NQVNLKDE1LCA4KQo+ ICsjZGVmaW5lIEVOSTJDRklMVEVSCQlCSVQoNCkKPiArI2RlZmluZSBDT0xPUl9CQVJfTU9ERQkJ R0VOTUFTSygxLCAwKQo+ICsjZGVmaW5lIENPTE9SX0JBUl9NT0RFX0JBUlMJMgo+ICAjZGVmaW5l IFBMTF9EQkcJCQkweDBhMDQKPiAgCj4gIHN0YXRpYyBib29sIHRjX3Rlc3RfcGF0dGVybjsKPiBA QCAtNjQ3LDEwICs2NzcsNiBAQCBzdGF0aWMgaW50IHRjX2dldF9kaXNwbGF5X3Byb3BzKHN0cnVj dCB0Y19kYXRhICp0YykKPiAgCj4gIHN0YXRpYyBpbnQgdGNfc2V0X3ZpZGVvX21vZGUoc3RydWN0 IHRjX2RhdGEgKnRjLCBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSkKPiAgewo+IC0JaW50 IHJldDsKPiAtCWludCB2aWRfc3luY19kbHk7Cj4gLQlpbnQgbWF4X3R1X3N5bWJvbDsKPiAtCj4g IAlpbnQgbGVmdF9tYXJnaW4gPSBtb2RlLT5odG90YWwgLSBtb2RlLT5oc3luY19lbmQ7Cj4gIAlp bnQgcmlnaHRfbWFyZ2luID0gbW9kZS0+aHN5bmNfc3RhcnQgLSBtb2RlLT5oZGlzcGxheTsKPiAg CWludCBoc3luY19sZW4gPSBtb2RlLT5oc3luY19lbmQgLSBtb2RlLT5oc3luY19zdGFydDsKPiBA QCAtNjU5LDc2ICs2ODUsNzQgQEAgc3RhdGljIGludCB0Y19zZXRfdmlkZW9fbW9kZShzdHJ1Y3Qg dGNfZGF0YSAqdGMsIHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlKQo+ICAJaW50IHZzeW5j X2xlbiA9IG1vZGUtPnZzeW5jX2VuZCAtIG1vZGUtPnZzeW5jX3N0YXJ0Owo+ICAKPiAgCS8qCj4g LQkgKiBSZWNvbW1lbmRlZCBtYXhpbXVtIG51bWJlciBvZiBzeW1ib2xzIHRyYW5zZmVycmVkIGlu IGEgdHJhbnNmZXIgdW5pdDoKPiArCSAqIFJlY29tbWVuZGVkIG1heGltdW0gbnVtYmVyIG9mIHN5 bWJvbHMgdHJhbnNmZXJyZWQgaW4gYQo+ICsJICogdHJhbnNmZXIgdW5pdDoKPiAgCSAqIERJVl9S T1VORF9VUCgoaW5wdXQgYWN0aXZlIHZpZGVvIGJhbmR3aWR0aCBpbiBieXRlcykgKiB0dV9zaXpl LAo+ICAJICogICAgICAgICAgICAgIChvdXRwdXQgYWN0aXZlIHZpZGVvIGJhbmR3aWR0aCBpbiBi eXRlcykpCj4gIAkgKiBNdXN0IGJlIGxlc3MgdGhhbiB0dV9zaXplLgo+ICAJICovCj4gLQltYXhf dHVfc3ltYm9sID0gVFVfU0laRV9SRUNPTU1FTkRFRCAtIDE7Cj4gLQo+IC0JZGV2X2RiZyh0Yy0+ ZGV2LCAic2V0IG1vZGUgJWR4JWRcbiIsCj4gLQkJbW9kZS0+aGRpc3BsYXksIG1vZGUtPnZkaXNw bGF5KTsKPiAtCWRldl9kYmcodGMtPmRldiwgIkggbWFyZ2luICVkLCVkIHN5bmMgJWRcbiIsCj4g LQkJbGVmdF9tYXJnaW4sIHJpZ2h0X21hcmdpbiwgaHN5bmNfbGVuKTsKPiAtCWRldl9kYmcodGMt PmRldiwgIlYgbWFyZ2luICVkLCVkIHN5bmMgJWRcbiIsCj4gLQkJdXBwZXJfbWFyZ2luLCBsb3dl cl9tYXJnaW4sIHZzeW5jX2xlbik7Cj4gLQlkZXZfZGJnKHRjLT5kZXYsICJ0b3RhbDogJWR4JWRc biIsIG1vZGUtPmh0b3RhbCwgbW9kZS0+dnRvdGFsKTsKPiAtCj4gKwlpbnQgbWF4X3R1X3N5bWJv bCA9IFRVX1NJWkVfUkVDT01NRU5ERUQgLSAxOwo+ICAKPiArCS8qIERQIE1haW4gU3RyZWFtIEF0 dHJpYnV0ZXMgKi8KPiArCWludCB2aWRfc3luY19kbHkgPSBoc3luY19sZW4gKyBsZWZ0X21hcmdp biArIG1vZGUtPmhkaXNwbGF5Owo+ICAJLyoKPiAgCSAqIExDRCBDdGwgRnJhbWUgU2l6ZQo+ICAJ ICogZGF0YXNoZWV0IGlzIG5vdCBjbGVhciBvZiB2c2RlbGF5IGluIGNhc2Ugb2YgRFBJCj4gIAkg KiBhc3N1bWUgd2UgZG8gbm90IG5lZWQgYW55IGRlbGF5IHdoZW4gRFBJIGlzIGEgc291cmNlIG9m Cj4gIAkgKiBzeW5jIHNpZ25hbHMKPiAgCSAqLwo+IC0JdGNfd3JpdGUoVlBDVFJMMCwgKDAgPDwg MjApIC8qIFZTREVMQVkgKi8gfAo+IC0JCSBPUFhMRk1UX1JHQjg4OCB8IEZSTVNZTkNfRElTQUJM RUQgfCBNU0ZfRElTQUJMRUQpOwo+IC0JdGNfd3JpdGUoSFRJTTAxLCAoQUxJR04obGVmdF9tYXJn aW4sIDIpIDw8IDE2KSB8IC8qIEggYmFjayBwb3JjaCAqLwo+IC0JCQkgKEFMSUdOKGhzeW5jX2xl biwgMikgPDwgMCkpOwkgLyogSHN5bmMgKi8KPiAtCXRjX3dyaXRlKEhUSU0wMiwgKEFMSUdOKHJp Z2h0X21hcmdpbiwgMikgPDwgMTYpIHwgIC8qIEggZnJvbnQgcG9yY2ggKi8KPiAtCQkJIChBTElH Tihtb2RlLT5oZGlzcGxheSwgMikgPDwgMCkpOyAvKiB3aWR0aCAqLwo+IC0JdGNfd3JpdGUoVlRJ TTAxLCAodXBwZXJfbWFyZ2luIDw8IDE2KSB8CQkvKiBWIGJhY2sgcG9yY2ggKi8KPiAtCQkJICh2 c3luY19sZW4gPDwgMCkpOwkJLyogVnN5bmMgKi8KPiAtCXRjX3dyaXRlKFZUSU0wMiwgKGxvd2Vy X21hcmdpbiA8PCAxNikgfAkJLyogViBmcm9udCBwb3JjaCAqLwo+IC0JCQkgKG1vZGUtPnZkaXNw bGF5IDw8IDApKTsJLyogaGVpZ2h0ICovCj4gLQl0Y193cml0ZShWRlVFTjAsIFZGVUVOKTsJCS8q IHVwZGF0ZSBzZXR0aW5ncyAqLwo+IC0KPiAtCS8qIFRlc3QgcGF0dGVybiBzZXR0aW5ncyAqLwo+ IC0JdGNfd3JpdGUoVFNUQ1RMLAo+IC0JCSAoMTIwIDw8IDI0KSB8CS8qIFJlZCBDb2xvciBjb21w b25lbnQgdmFsdWUgKi8KPiAtCQkgKDIwIDw8IDE2KSB8CS8qIEdyZWVuIENvbG9yIGNvbXBvbmVu dCB2YWx1ZSAqLwo+IC0JCSAoOTkgPDwgOCkgfAkvKiBCbHVlIENvbG9yIGNvbXBvbmVudCB2YWx1 ZSAqLwo+IC0JCSAoMSA8PCA0KSB8CS8qIEVuYWJsZSBJMkMgRmlsdGVyICovCj4gLQkJICgyIDw8 IDApIHwJLyogQ29sb3IgYmFyIE1vZGUgKi8KPiAtCQkgMCk7Cj4gLQo+IC0JLyogRFAgTWFpbiBT dHJlYW0gQXR0cmlidXRlcyAqLwo+IC0JdmlkX3N5bmNfZGx5ID0gaHN5bmNfbGVuICsgbGVmdF9t YXJnaW4gKyBtb2RlLT5oZGlzcGxheTsKPiAtCXRjX3dyaXRlKERQMF9WSURTWU5DREVMQVksCj4g LQkJIChtYXhfdHVfc3ltYm9sIDw8IDE2KSB8CS8qIHRocmVzaF9kbHkgKi8KPiAtCQkgKHZpZF9z eW5jX2RseSA8PCAwKSk7Cj4gKwljb25zdCB1MzIgdnNfcG9sID0gbW9kZS0+ZmxhZ3MgJiBEUk1f TU9ERV9GTEFHX05WU1lOQyA/Cj4gKwkJU1lOQ1ZBTF9WU19QT0xfQUNUSVZFX0xPVyA6IDA7Cj4g Kwljb25zdCB1MzIgaHNfcG9sID0gbW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX05IU1lOQyA/ Cj4gKwkJU1lOQ1ZBTF9IU19QT0xfQUNUSVZFX0xPVyA6IDA7Cj4gKwljb25zdCBzdHJ1Y3QgcmVn X3NlcXVlbmNlIHZpZGVvX21vZGVfc2V0dGluZ3NbXSA9IHsKPiArCQl7IFZQQ1RSTDAsIEZJRUxE X1BSRVAoVlNERUxBWSwgMCkgfAo+ICsJCQkgICBPUFhMRk1UX1JHQjg4OCB8IEZSTVNZTkNfRElT QUJMRUQgfCBNU0ZfRElTQUJMRUQgfSwKPiArCQl7IEhUSU0wMSwgRklFTERfUFJFUChIQlBSLCBB TElHTihsZWZ0X21hcmdpbiwgMikpIHwKPiArCQkJICBGSUVMRF9QUkVQKEhQVywgQUxJR04oaHN5 bmNfbGVuLCAyKSkgfSwKPiArCQl7IEhUSU0wMiwgRklFTERfUFJFUChIRElTUFIsIEFMSUdOKG1v ZGUtPmhkaXNwbGF5LCAyKSkgfAo+ICsJCQkgIEZJRUxEX1BSRVAoSEZQUiwgQUxJR04ocmlnaHRf bWFyZ2luLCAyKSkgfSwKPiArCQl7IFZUSU0wMSwgRklFTERfUFJFUChWQlBSLCB1cHBlcl9tYXJn aW4pIHwKPiArCQkJICBGSUVMRF9QUkVQKFZTUFIsIHZzeW5jX2xlbikgfSwKPiArCQl7IFZUSU0w MiwgRklFTERfUFJFUChWRlBSLCBsb3dlcl9tYXJnaW4pIHwKPiArCQkJICBGSUVMRF9QUkVQKFZE SVNQUiwgbW9kZS0+dmRpc3BsYXkpIH0sCj4gKwkJeyBWRlVFTjAsIFZGVUVOIH0sCj4gKwkJeyBU U1RDVEwsIEZJRUxEX1BSRVAoQ09MT1JfUiwgMTIwKSB8Cj4gKwkJCSAgRklFTERfUFJFUChDT0xP Ul9HLCAyMCkgfAo+ICsJCQkgIEZJRUxEX1BSRVAoQ09MT1JfQiwgOTkpIHwKPiArCQkJICBFTkky Q0ZJTFRFUiB8Cj4gKwkJCSAgRklFTERfUFJFUChDT0xPUl9CQVJfTU9ERSwgQ09MT1JfQkFSX01P REVfQkFSUykgfSwKPiArCQl7IERQMF9WSURTWU5DREVMQVksIEZJRUxEX1BSRVAoVEhSRVNIX0RM WSwgbWF4X3R1X3N5bWJvbCkgfAo+ICsJCQkJICAgIEZJRUxEX1BSRVAoVklEX1NZTkNfRExZLCB2 aWRfc3luY19kbHkpIH0sCj4gKwkJeyBEUDBfVE9UQUxWQUwsIEZJRUxEX1BSRVAoSF9UT1RBTCwg bW9kZS0+aHRvdGFsKSB8Cj4gKwkJCQlGSUVMRF9QUkVQKFZfVE9UQUwsIG1vZGUtPnZ0b3RhbCkg fSwKPiArCQl7IERQMF9TVEFSVFZBTCwgRklFTERfUFJFUChIX1NUQVJULCBsZWZ0X21hcmdpbiAr IGhzeW5jX2xlbikgfAo+ICsJCQkJRklFTERfUFJFUChWX1NUQVJULAo+ICsJCQkJCSAgIHVwcGVy X21hcmdpbiArIHZzeW5jX2xlbikgfSwKPiArCQl7IERQMF9BQ1RJVkVWQUwsIEZJRUxEX1BSRVAo Vl9BQ1QsIG1vZGUtPnZkaXNwbGF5KSB8Cj4gKwkJCQkgRklFTERfUFJFUChIX0FDVCwgbW9kZS0+ aGRpc3BsYXkpIH0sCj4gKwkJeyBEUDBfU1lOQ1ZBTCwgRklFTERfUFJFUChWU19XSURUSCwgdnN5 bmNfbGVuKSB8Cj4gKwkJCSAgICAgICBGSUVMRF9QUkVQKEhTX1dJRFRILCBoc3luY19sZW4pIHwK PiArCQkJICAgICAgIGhzX3BvbCB8IHZzX3BvbCB9LAo+ICsJCXsgRFBJUFhMRk1ULCBWU19QT0xf QUNUSVZFX0xPVyB8IEhTX1BPTF9BQ1RJVkVfTE9XIHwKPiArCQkJICAgICBERV9QT0xfQUNUSVZF X0hJR0ggfCBTVUJfQ0ZHX1RZUEVfQ09ORklHMSB8Cj4gKwkJCSAgICAgRFBJX0JQUF9SR0I4ODgg fSwKPiArCQl7IERQMF9NSVNDLCBGSUVMRF9QUkVQKE1BWF9UVV9TWU1CT0wsIG1heF90dV9zeW1i b2wpIHwKPiArCQkJICAgIEZJRUxEX1BSRVAoVFVfU0laRSwgVFVfU0laRV9SRUNPTU1FTkRFRCkg fAo+ICsJCQkgICAgQlBDXzggfSwKPiArCX07Cj4gIAo+IC0JdGNfd3JpdGUoRFAwX1RPVEFMVkFM LCAobW9kZS0+dnRvdGFsIDw8IDE2KSB8IChtb2RlLT5odG90YWwpKTsKPiAtCj4gLQl0Y193cml0 ZShEUDBfU1RBUlRWQUwsCj4gLQkJICgodXBwZXJfbWFyZ2luICsgdnN5bmNfbGVuKSA8PCAxNikg fAo+IC0JCSAoKGxlZnRfbWFyZ2luICsgaHN5bmNfbGVuKSA8PCAwKSk7Cj4gLQo+IC0JdGNfd3Jp dGUoRFAwX0FDVElWRVZBTCwgKG1vZGUtPnZkaXNwbGF5IDw8IDE2KSB8IChtb2RlLT5oZGlzcGxh eSkpOwo+IC0KPiAtCXRjX3dyaXRlKERQMF9TWU5DVkFMLCAodnN5bmNfbGVuIDw8IDE2KSB8ICho c3luY19sZW4gPDwgMCkgfAo+IC0JCSAoKG1vZGUtPmZsYWdzICYgRFJNX01PREVfRkxBR19OSFNZ TkMpID8gU1lOQ1ZBTF9IU19QT0xfQUNUSVZFX0xPVyA6IDApIHwKPiAtCQkgKChtb2RlLT5mbGFn cyAmIERSTV9NT0RFX0ZMQUdfTlZTWU5DKSA/IFNZTkNWQUxfVlNfUE9MX0FDVElWRV9MT1cgOiAw KSk7Cj4gLQo+IC0JdGNfd3JpdGUoRFBJUFhMRk1ULCBWU19QT0xfQUNUSVZFX0xPVyB8IEhTX1BP TF9BQ1RJVkVfTE9XIHwKPiAtCQkgREVfUE9MX0FDVElWRV9ISUdIIHwgU1VCX0NGR19UWVBFX0NP TkZJRzEgfCBEUElfQlBQX1JHQjg4OCk7Cj4gLQo+IC0JdGNfd3JpdGUoRFAwX01JU0MsIChtYXhf dHVfc3ltYm9sIDw8IDIzKSB8IChUVV9TSVpFX1JFQ09NTUVOREVEIDw8IDE2KSB8Cj4gLQkJCSAg IEJQQ184KTsKPiArCWRldl9kYmcodGMtPmRldiwgInNldCBtb2RlICVkeCVkXG4iLAo+ICsJCW1v ZGUtPmhkaXNwbGF5LCBtb2RlLT52ZGlzcGxheSk7Cj4gKwlkZXZfZGJnKHRjLT5kZXYsICJIIG1h cmdpbiAlZCwlZCBzeW5jICVkXG4iLAo+ICsJCWxlZnRfbWFyZ2luLCByaWdodF9tYXJnaW4sIGhz eW5jX2xlbik7Cj4gKwlkZXZfZGJnKHRjLT5kZXYsICJWIG1hcmdpbiAlZCwlZCBzeW5jICVkXG4i LAo+ICsJCXVwcGVyX21hcmdpbiwgbG93ZXJfbWFyZ2luLCB2c3luY19sZW4pOwo+ICsJZGV2X2Ri Zyh0Yy0+ZGV2LCAidG90YWw6ICVkeCVkXG4iLCBtb2RlLT5odG90YWwsIG1vZGUtPnZ0b3RhbCk7 Cj4gIAo+IC0JcmV0dXJuIDA7Cj4gLWVycjoKPiAtCXJldHVybiByZXQ7Cj4gKwlyZXR1cm4gcmVn bWFwX211bHRpX3JlZ193cml0ZSh0Yy0+cmVnbWFwLAo+ICsJCQkJICAgICAgdmlkZW9fbW9kZV9z ZXR0aW5ncywKPiArCQkJCSAgICAgIEFSUkFZX1NJWkUodmlkZW9fbW9kZV9zZXR0aW5ncykpOwo+ ICB9Cj4gIAo+ICBzdGF0aWMgaW50IHRjX3dhaXRfbGlua190cmFpbmluZyhzdHJ1Y3QgdGNfZGF0 YSAqdGMsIHUzMiAqZXJyb3IpCgpJIGRvbid0IGxpa2UgdGhpcyBjaGFuZ2UuIEkgdGhpbmsgbXVs dGlfcmVnX3dyaXRlIGlzIGdvb2QgZm9yIHdyaXRpbmcKdGhpbmdzIGxpa2UsIHNheSwgY29sb3Ig Y29udmVyc2lvbiB0YWJsZS4gQnV0IHRoZSBkYXRhIGZvciB2aWRlbyBtb2RlIGlzCm1vcmUgY29t cGxleCBhbmQgbmVlZHMgbW9yZSBsb2dpYyAoZS5nLiBoZXJlID86IG9wZXJhdG9yIGlzIHVzZWQp LiBZb3UKbmVlZCB0byBzdHVmZiBhbGwgdGhhdCBsb2dpYyBpbnRvIHZhcmlhYmxlIGluaXRpYWxp emVycy4gWW91IGNhbid0IHVzZQplLmcuIGlmKCkgYW55bW9yZSwgYW5kIHlvdSBjYW4ndCBldmVu IGluc2VydCBhIGRlYnVnIHByaW50IGJldHdlZW4gdGhlCndyaXRlcyBpZiB5b3UgbmVlZCB0by4K ClNvLCBpbiBteSBvcGluaW9uLCB0aGlzIGRvZXNuJ3QgbG9vayAobXVjaCkgY2xlYW5lciwgYW5k IG1ha2VzIGxpZmUgbW9yZQpkaWZmaWN1bHQuCgogVG9taQoKLS0gClRleGFzIEluc3RydW1lbnRz IEZpbmxhbmQgT3ksIFBvcmtrYWxhbmthdHUgMjIsIDAwMTgwIEhlbHNpbmtpLgpZLXR1bm51cy9C dXNpbmVzcyBJRDogMDYxNTUyMS00LiBLb3RpcGFpa2thL0RvbWljaWxlOiBIZWxzaW5raQpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFp bGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWw=