From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 869DFC47094 for ; Thu, 10 Jun 2021 13:03:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67485613DE for ; Thu, 10 Jun 2021 13:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230368AbhFJNE7 (ORCPT ); Thu, 10 Jun 2021 09:04:59 -0400 Received: from mail-wr1-f51.google.com ([209.85.221.51]:33660 "EHLO mail-wr1-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbhFJNE5 (ORCPT ); Thu, 10 Jun 2021 09:04:57 -0400 Received: by mail-wr1-f51.google.com with SMTP id a20so2267923wrc.0 for ; Thu, 10 Jun 2021 06:03:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=6shO42h72qRWo8OQX0kP7yL9Z4bJuOUKyxOwM0jZHao=; b=UXtNw6SBlPyy1sfqx+i5lUpQEtwcLkJuDdcWk/xH0YQd6Zbt3aD0FWuTE+7FZYuHgB q/MV79OcXXsRJoWmnZB/lvI6LUjyyCLNow+q4ocRXM6BCbb7AhkJbLc2QXS3UXi7pow/ kGyjka+r8CrpOQTt/iQ0NUYm9lRIt/lDQTRxmPNLmZDaKGeojsPfmT2pJyiQHpS+8Y0j R9bKqqDy08nIuXMDblUrBepA1MwyqsJHciMblxTVoWMpFEbOwTZcYpqraSD1JP8cDpH8 OfGwStxAPeuspcQUGSDQtT07KLWGdDDdEAy3EMTM+nuvWEPnYeEOjKZZ+oPTnQBSCr+z zYGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=6shO42h72qRWo8OQX0kP7yL9Z4bJuOUKyxOwM0jZHao=; b=ottej+xJAWpTs5rYiyYtFG+f+UGhV9L5FsmFHiEl9H2ZIQJU9xVfhexGIZ9W5lAihb WizcEd8rKD4EKgzQqk4pr3W09OTUZ+wx3NGHq3ek51DGdwHQkAg7czf+AR+m9i+Rzws2 IeP+r08vuCDFUcG2bBhmdoVD3I+peF3Xkj2VzeLaP/fsDAG6ndu5WcydLztjYo+BiAue vKJZenNuk9HmVTS94yadYZD04MPM3N2+RHhkr9/90Xm2vZvNkpTkyrPNBCOKSqyXlQvS DE5bffRLsb0Q3x0iKwDxNNN+89EQnYabGGmQzpER1wi5kfAUpGzRrXqCazL7FbM0mBuH hLAA== X-Gm-Message-State: AOAM530jhrb6n/yysL5HYqIc+XMOhkY1a4W/q7rDjae8pcE48Owwkkhi /YH1/xRjAi/9Uv0oOx7Jkk6RR9R2pU/pStYP X-Google-Smtp-Source: ABdhPJxPzrNTrIGL4+I37QwwsNYCckHfJuaN6lDRoGfQawcCiLUNt9xiQrdXtdfq8TLphq1Rh17OKg== X-Received: by 2002:a5d:6a02:: with SMTP id m2mr5345088wru.77.1623330119825; Thu, 10 Jun 2021 06:01:59 -0700 (PDT) Received: from ?IPv6:2a01:e34:ed2f:f020:e537:d458:d3c4:18e1? ([2a01:e34:ed2f:f020:e537:d458:d3c4:18e1]) by smtp.googlemail.com with ESMTPSA id b8sm10070075wmd.35.2021.06.10.06.01.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jun 2021 06:01:56 -0700 (PDT) Subject: Re: [PATCH v2 1/2] clocksource: arm_global_timer: implement rate compensation whenever source clock changes To: Andrea Merello , tglx@linutronix.de, patrice.chotard@foss.st.com Cc: Patrice Chotard , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michal Simek , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= References: <20210406130045.15491-1-andrea.merello@gmail.com> <20210406130045.15491-2-andrea.merello@gmail.com> From: Daniel Lezcano Message-ID: <0d33db1f-8af1-1519-aba1-3e46afa4cf4c@linaro.org> Date: Thu, 10 Jun 2021 15:01:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210406130045.15491-2-andrea.merello@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Patrice, do you have any comment about these changes ? On 06/04/2021 15:00, Andrea Merello wrote: > This patch adds rate change notification support for the parent clock; > should that clock change, then we try to adjust the our prescaler in order > to compensate (i.e. we adjust to still get the same timer frequency). > > This is loosely based on what it's done in timer-cadence-ttc. timer-sun51, > mips-gic-timer and smp_twd.c also seem to look at their parent clock rate > and to perform some kind of adjustment whenever needed. > > In this particular case we have only one single counter and prescaler for > all clocksource, clockevent and timer_delay, and we just update it for all > (i.e. we don't let it go and call clockevents_update_freq() to notify to > the kernel that our rate has changed). > > Note that, there is apparently no other way to fixup things, because once > we call register_current_timer_delay(), specifying the timer rate, it seems > that that rate is not supposed to change ever. > > In order for this mechanism to work, we have to make assumptions about how > much the initial clock is supposed to eventually decrease from the initial > one, and set our initial prescaler to a value that we can eventually > decrease enough to compensate. We provide an option in KConfig for this. > > In case we end up in a situation in which we are not able to compensate the > parent clock change, we fail returning NOTIFY_BAD. > > This fixes a real-world problem with Zynq arch not being able to use this > driver and CPU_FREQ at the same time (because ARM global timer is fed by > the CPU clock, which may keep changing when CPU_FREQ is enabled). > > Signed-off-by: Andrea Merello > Cc: Patrice Chotard > Cc: linux-kernel@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: Michal Simek > Cc: Sören Brinkmann > --- > drivers/clocksource/Kconfig | 13 +++ > drivers/clocksource/arm_global_timer.c | 122 +++++++++++++++++++++++-- > 2 files changed, 125 insertions(+), 10 deletions(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 39aa21d01e05..19fc5f8883e0 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -358,6 +358,19 @@ config ARM_GLOBAL_TIMER > help > This option enables support for the ARM global timer unit. > > +config ARM_GT_INITIAL_PRESCALER_VAL > + int "ARM global timer initial prescaler value" > + default 1 > + depends on ARM_GLOBAL_TIMER > + help > + When the ARM global timer initializes, its current rate is declared > + to the kernel and maintained forever. Should it's parent clock > + change, the driver tries to fix the timer's internal prescaler. > + On some machs (i.e. Zynq) the initial prescaler value thus poses > + bounds about how much the parent clock is allowed to decrease or > + increase wrt the initial clock value. > + This affects CPU_FREQ max delta from the initial frequency. > + > config ARM_TIMER_SP804 > bool "Support for Dual Timer SP804 module" if COMPILE_TEST > depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP > diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c > index 88b2d38a7a61..60a8047fd32e 100644 > --- a/drivers/clocksource/arm_global_timer.c > +++ b/drivers/clocksource/arm_global_timer.c > @@ -31,6 +31,10 @@ > #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ > #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ > #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ > +#define GT_CONTROL_PRESCALER_SHIFT 8 > +#define GT_CONTROL_PRESCALER_MAX 0xF > +#define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ > + GT_CONTROL_PRESCALER_SHIFT) > > #define GT_INT_STATUS 0x0c > #define GT_INT_STATUS_EVENT_FLAG BIT(0) > @@ -39,6 +43,7 @@ > #define GT_COMP1 0x14 > #define GT_AUTO_INC 0x18 > > +#define MAX_F_ERR 50 > /* > * We are expecting to be clocked by the ARM peripheral clock. > * > @@ -46,7 +51,8 @@ > * the units for all operations. > */ > static void __iomem *gt_base; > -static unsigned long gt_clk_rate; > +struct notifier_block gt_clk_rate_change_nb; > +static u32 gt_psv_new, gt_psv_bck, gt_target_rate; > static int gt_ppi; > static struct clock_event_device __percpu *gt_evt; > > @@ -96,7 +102,10 @@ static void gt_compare_set(unsigned long delta, int periodic) > unsigned long ctrl; > > counter += delta; > - ctrl = GT_CONTROL_TIMER_ENABLE; > + ctrl = readl(gt_base + GT_CONTROL); > + ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE | > + GT_CONTROL_AUTO_INC | GT_CONTROL_AUTO_INC); > + ctrl |= GT_CONTROL_TIMER_ENABLE; > writel_relaxed(ctrl, gt_base + GT_CONTROL); > writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0); > writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1); > @@ -123,7 +132,7 @@ static int gt_clockevent_shutdown(struct clock_event_device *evt) > > static int gt_clockevent_set_periodic(struct clock_event_device *evt) > { > - gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1); > + gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1); > return 0; > } > > @@ -177,7 +186,7 @@ static int gt_starting_cpu(unsigned int cpu) > clk->cpumask = cpumask_of(cpu); > clk->rating = 300; > clk->irq = gt_ppi; > - clockevents_config_and_register(clk, gt_clk_rate, > + clockevents_config_and_register(clk, gt_target_rate, > 1, 0xffffffff); > enable_percpu_irq(clk->irq, IRQ_TYPE_NONE); > return 0; > @@ -232,9 +241,28 @@ static struct delay_timer gt_delay_timer = { > .read_current_timer = gt_read_long, > }; > > +static void gt_write_presc(u32 psv) > +{ > + u32 reg; > + > + reg = readl(gt_base + GT_CONTROL); > + reg &= ~GT_CONTROL_PRESCALER_MASK; > + reg |= psv << GT_CONTROL_PRESCALER_SHIFT; > + writel(reg, gt_base + GT_CONTROL); > +} > + > +static u32 gt_read_presc(void) > +{ > + u32 reg; > + > + reg = readl(gt_base + GT_CONTROL); > + reg &= GT_CONTROL_PRESCALER_MASK; > + return reg >> GT_CONTROL_PRESCALER_SHIFT; > +} > + > static void __init gt_delay_timer_init(void) > { > - gt_delay_timer.freq = gt_clk_rate; > + gt_delay_timer.freq = gt_target_rate; > register_current_timer_delay(>_delay_timer); > } > > @@ -243,18 +271,81 @@ static int __init gt_clocksource_init(void) > writel(0, gt_base + GT_CONTROL); > writel(0, gt_base + GT_COUNTER0); > writel(0, gt_base + GT_COUNTER1); > - /* enables timer on all the cores */ > - writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); > + /* set prescaler and enable timer on all the cores */ > + writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) << > + GT_CONTROL_PRESCALER_SHIFT) > + | GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); > > #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK > - sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate); > + sched_clock_register(gt_sched_clock_read, 64, gt_target_rate); > #endif > - return clocksource_register_hz(>_clocksource, gt_clk_rate); > + return clocksource_register_hz(>_clocksource, gt_target_rate); > +} > + > +static int gt_clk_rate_change_cb(struct notifier_block *nb, > + unsigned long event, void *data) > +{ > + struct clk_notifier_data *ndata = data; > + > + switch (event) { > + case PRE_RATE_CHANGE: > + { > + int psv; > + > + psv = DIV_ROUND_CLOSEST(ndata->new_rate, > + gt_target_rate); > + > + if (abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR) > + return NOTIFY_BAD; > + > + psv--; > + > + /* prescaler within legal range? */ > + if (psv < 0 || psv > GT_CONTROL_PRESCALER_MAX) > + return NOTIFY_BAD; > + > + /* > + * store timer clock ctrl register so we can restore it in case > + * of an abort. > + */ > + gt_psv_bck = gt_read_presc(); > + gt_psv_new = psv; > + /* scale down: adjust divider in post-change notification */ > + if (ndata->new_rate < ndata->old_rate) > + return NOTIFY_DONE; > + > + /* scale up: adjust divider now - before frequency change */ > + gt_write_presc(psv); > + break; > + } > + case POST_RATE_CHANGE: > + /* scale up: pre-change notification did the adjustment */ > + if (ndata->new_rate > ndata->old_rate) > + return NOTIFY_OK; > + > + /* scale down: adjust divider now - after frequency change */ > + gt_write_presc(gt_psv_new); > + break; > + > + case ABORT_RATE_CHANGE: > + /* we have to undo the adjustment in case we scale up */ > + if (ndata->new_rate < ndata->old_rate) > + return NOTIFY_OK; > + > + /* restore original register value */ > + gt_write_presc(gt_psv_bck); > + break; > + default: > + return NOTIFY_DONE; > + } > + > + return NOTIFY_DONE; > } > > static int __init global_timer_of_register(struct device_node *np) > { > struct clk *gt_clk; > + static unsigned long gt_clk_rate; > int err = 0; > > /* > @@ -292,11 +383,20 @@ static int __init global_timer_of_register(struct device_node *np) > } > > gt_clk_rate = clk_get_rate(gt_clk); > + gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; > + gt_clk_rate_change_nb.notifier_call = > + gt_clk_rate_change_cb; > + err = clk_notifier_register(gt_clk, >_clk_rate_change_nb); > + if (err) { > + pr_warn("Unable to register clock notifier\n"); > + goto out_clk; > + } > + > gt_evt = alloc_percpu(struct clock_event_device); > if (!gt_evt) { > pr_warn("global-timer: can't allocate memory\n"); > err = -ENOMEM; > - goto out_clk; > + goto out_clk_nb; > } > > err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt, > @@ -326,6 +426,8 @@ static int __init global_timer_of_register(struct device_node *np) > free_percpu_irq(gt_ppi, gt_evt); > out_free: > free_percpu(gt_evt); > +out_clk_nb: > + clk_notifier_unregister(gt_clk, >_clk_rate_change_nb); > out_clk: > clk_disable_unprepare(gt_clk); > out_unmap: > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E34C47094 for ; Thu, 10 Jun 2021 13:03:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6DEC613C9 for ; Thu, 10 Jun 2021 13:03:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6DEC613C9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=KioKZXuPW/p8vAzR80a/AvZjScDepTvt4OI1vmLgRqs=; b=QPHJg5vWhnKknabIlFQnWQ8DX9 ScTEEapRC3tf3TssMoX6HMFUIasB8P3esnm7/a8uEzg/mPUBEZnQXeYs9bf4iJDkhJe6VYfFq67wL ooTOKpHJWLAwIP0J5Ll10tjkm9/X1kMb0fWVYQmqfPYQ7CO6o31cJZL8r9NuaDcwrTmoRNIuxGBqI aJKPF1OlUsDqzr9POTJIZuZBVBjmirw/KBX8vEgR4Q6gUvEdRsBlbBdZ3lXijkgL2H43OfZnpPlIF Qx1qm+eCLbj5s/YH6nCFXkPkiB50oWcTRvO3Gbl9bxIZwMPqatGSMzTJDuUZxh4uQ/v4Ov4+aa3JL 87tUaQuw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrKK0-000o1F-PB; Thu, 10 Jun 2021 13:02:09 +0000 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrKJw-000nz4-1n for linux-arm-kernel@lists.infradead.org; Thu, 10 Jun 2021 13:02:06 +0000 Received: by mail-wr1-x433.google.com with SMTP id c9so2227216wrt.5 for ; Thu, 10 Jun 2021 06:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=6shO42h72qRWo8OQX0kP7yL9Z4bJuOUKyxOwM0jZHao=; b=UXtNw6SBlPyy1sfqx+i5lUpQEtwcLkJuDdcWk/xH0YQd6Zbt3aD0FWuTE+7FZYuHgB q/MV79OcXXsRJoWmnZB/lvI6LUjyyCLNow+q4ocRXM6BCbb7AhkJbLc2QXS3UXi7pow/ kGyjka+r8CrpOQTt/iQ0NUYm9lRIt/lDQTRxmPNLmZDaKGeojsPfmT2pJyiQHpS+8Y0j R9bKqqDy08nIuXMDblUrBepA1MwyqsJHciMblxTVoWMpFEbOwTZcYpqraSD1JP8cDpH8 OfGwStxAPeuspcQUGSDQtT07KLWGdDDdEAy3EMTM+nuvWEPnYeEOjKZZ+oPTnQBSCr+z zYGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=6shO42h72qRWo8OQX0kP7yL9Z4bJuOUKyxOwM0jZHao=; b=GMUzTfP7enUHTVcZj/qgGMs2rYEjVFPXf1wTP0Mm57jBa7fSH5OasB2SwmP6Lxh41/ ZlMdwkH7nRrjPpSNvIrzz8M7dbXezcCQiYX7toeJ0dwcQU20mSL6Qdsw/8tO/27JsfBf WRWSOQa3A2F8HH0xOoGUSqcswC0a7VcVFC09PghcX1/JSzKZUu7zE2hm9M4KU6sgy7rZ i1lDaD0VPHl90NUIbHcY9FYJQjEus6zcdRfUOuXAOlJUjL7IHG1pS1WI5z4sSIetaSHt oLjePSsxQFznB2t8qM4oY6u0UAGfQf8AH8rvw+Kj+U4veBL8WtGQx6ID6H/BZ6Kkp7Aa 3UZw== X-Gm-Message-State: AOAM530389bp5RdwlBc6/19+/oWhVEsEeKdAlBZ95ZLr9LRkUKg5ThvC 4n1xtS8YTzxKj6WxVENbMLS5Lg== X-Google-Smtp-Source: ABdhPJxPzrNTrIGL4+I37QwwsNYCckHfJuaN6lDRoGfQawcCiLUNt9xiQrdXtdfq8TLphq1Rh17OKg== X-Received: by 2002:a5d:6a02:: with SMTP id m2mr5345088wru.77.1623330119825; Thu, 10 Jun 2021 06:01:59 -0700 (PDT) Received: from ?IPv6:2a01:e34:ed2f:f020:e537:d458:d3c4:18e1? ([2a01:e34:ed2f:f020:e537:d458:d3c4:18e1]) by smtp.googlemail.com with ESMTPSA id b8sm10070075wmd.35.2021.06.10.06.01.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jun 2021 06:01:56 -0700 (PDT) Subject: Re: [PATCH v2 1/2] clocksource: arm_global_timer: implement rate compensation whenever source clock changes To: Andrea Merello , tglx@linutronix.de, patrice.chotard@foss.st.com Cc: Patrice Chotard , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michal Simek , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= References: <20210406130045.15491-1-andrea.merello@gmail.com> <20210406130045.15491-2-andrea.merello@gmail.com> From: Daniel Lezcano Message-ID: <0d33db1f-8af1-1519-aba1-3e46afa4cf4c@linaro.org> Date: Thu, 10 Jun 2021 15:01:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210406130045.15491-2-andrea.merello@gmail.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_060204_162494_69A716B6 X-CRM114-Status: GOOD ( 50.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CkhpIFBhdHJpY2UsCgpkbyB5b3UgaGF2ZSBhbnkgY29tbWVudCBhYm91dCB0aGVzZSBjaGFuZ2Vz ID8KCgpPbiAwNi8wNC8yMDIxIDE1OjAwLCBBbmRyZWEgTWVyZWxsbyB3cm90ZToKPiBUaGlzIHBh dGNoIGFkZHMgcmF0ZSBjaGFuZ2Ugbm90aWZpY2F0aW9uIHN1cHBvcnQgZm9yIHRoZSBwYXJlbnQg Y2xvY2s7Cj4gc2hvdWxkIHRoYXQgY2xvY2sgY2hhbmdlLCB0aGVuIHdlIHRyeSB0byBhZGp1c3Qg dGhlIG91ciBwcmVzY2FsZXIgaW4gb3JkZXIKPiB0byBjb21wZW5zYXRlIChpLmUuIHdlIGFkanVz dCB0byBzdGlsbCBnZXQgdGhlIHNhbWUgdGltZXIgZnJlcXVlbmN5KS4KPiAKPiBUaGlzIGlzIGxv b3NlbHkgYmFzZWQgb24gd2hhdCBpdCdzIGRvbmUgaW4gdGltZXItY2FkZW5jZS10dGMuIHRpbWVy LXN1bjUxLAo+IG1pcHMtZ2ljLXRpbWVyIGFuZCBzbXBfdHdkLmMgYWxzbyBzZWVtIHRvIGxvb2sg YXQgdGhlaXIgcGFyZW50IGNsb2NrIHJhdGUKPiBhbmQgdG8gcGVyZm9ybSBzb21lIGtpbmQgb2Yg YWRqdXN0bWVudCB3aGVuZXZlciBuZWVkZWQuCj4gCj4gSW4gdGhpcyBwYXJ0aWN1bGFyIGNhc2Ug d2UgaGF2ZSBvbmx5IG9uZSBzaW5nbGUgY291bnRlciBhbmQgcHJlc2NhbGVyIGZvcgo+IGFsbCBj bG9ja3NvdXJjZSwgY2xvY2tldmVudCBhbmQgdGltZXJfZGVsYXksIGFuZCB3ZSBqdXN0IHVwZGF0 ZSBpdCBmb3IgYWxsCj4gKGkuZS4gd2UgZG9uJ3QgbGV0IGl0IGdvIGFuZCBjYWxsIGNsb2NrZXZl bnRzX3VwZGF0ZV9mcmVxKCkgdG8gbm90aWZ5IHRvCj4gdGhlIGtlcm5lbCB0aGF0IG91ciByYXRl IGhhcyBjaGFuZ2VkKS4KPiAKPiBOb3RlIHRoYXQsIHRoZXJlIGlzIGFwcGFyZW50bHkgbm8gb3Ro ZXIgd2F5IHRvIGZpeHVwIHRoaW5ncywgYmVjYXVzZSBvbmNlCj4gd2UgY2FsbCByZWdpc3Rlcl9j dXJyZW50X3RpbWVyX2RlbGF5KCksIHNwZWNpZnlpbmcgdGhlIHRpbWVyIHJhdGUsIGl0IHNlZW1z Cj4gdGhhdCB0aGF0IHJhdGUgaXMgbm90IHN1cHBvc2VkIHRvIGNoYW5nZSBldmVyLgo+IAo+IElu IG9yZGVyIGZvciB0aGlzIG1lY2hhbmlzbSB0byB3b3JrLCB3ZSBoYXZlIHRvIG1ha2UgYXNzdW1w dGlvbnMgYWJvdXQgaG93Cj4gbXVjaCB0aGUgaW5pdGlhbCBjbG9jayBpcyBzdXBwb3NlZCB0byBl dmVudHVhbGx5IGRlY3JlYXNlIGZyb20gdGhlIGluaXRpYWwKPiBvbmUsIGFuZCBzZXQgb3VyIGlu aXRpYWwgcHJlc2NhbGVyIHRvIGEgdmFsdWUgdGhhdCB3ZSBjYW4gZXZlbnR1YWxseQo+IGRlY3Jl YXNlIGVub3VnaCB0byBjb21wZW5zYXRlLiBXZSBwcm92aWRlIGFuIG9wdGlvbiBpbiBLQ29uZmln IGZvciB0aGlzLgo+IAo+IEluIGNhc2Ugd2UgZW5kIHVwIGluIGEgc2l0dWF0aW9uIGluIHdoaWNo IHdlIGFyZSBub3QgYWJsZSB0byBjb21wZW5zYXRlIHRoZQo+IHBhcmVudCBjbG9jayBjaGFuZ2Us IHdlIGZhaWwgcmV0dXJuaW5nIE5PVElGWV9CQUQuCj4gCj4gVGhpcyBmaXhlcyBhIHJlYWwtd29y bGQgcHJvYmxlbSB3aXRoIFp5bnEgYXJjaCBub3QgYmVpbmcgYWJsZSB0byB1c2UgdGhpcwo+IGRy aXZlciBhbmQgQ1BVX0ZSRVEgYXQgdGhlIHNhbWUgdGltZSAoYmVjYXVzZSBBUk0gZ2xvYmFsIHRp bWVyIGlzIGZlZCBieQo+IHRoZSBDUFUgY2xvY2ssIHdoaWNoIG1heSBrZWVwIGNoYW5naW5nIHdo ZW4gQ1BVX0ZSRVEgaXMgZW5hYmxlZCkuCj4gCj4gU2lnbmVkLW9mZi1ieTogQW5kcmVhIE1lcmVs bG8gPGFuZHJlYS5tZXJlbGxvQGdtYWlsLmNvbT4KPiBDYzogUGF0cmljZSBDaG90YXJkIDxwYXRy aWNlLmNob3RhcmRAc3QuY29tPgo+IENjOiBsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnCj4g Q2M6IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwo+IENjOiBNaWNoYWwgU2lt ZWsgPG1pY2hhbC5zaW1la0B4aWxpbnguY29tPgo+IENjOiBTw7ZyZW4gQnJpbmttYW5uIDxzb3Jl bi5icmlua21hbm5AeGlsaW54LmNvbT4KPiAtLS0KPiAgZHJpdmVycy9jbG9ja3NvdXJjZS9LY29u ZmlnICAgICAgICAgICAgfCAgMTMgKysrCj4gIGRyaXZlcnMvY2xvY2tzb3VyY2UvYXJtX2dsb2Jh bF90aW1lci5jIHwgMTIyICsrKysrKysrKysrKysrKysrKysrKysrLS0KPiAgMiBmaWxlcyBjaGFu Z2VkLCAxMjUgaW5zZXJ0aW9ucygrKSwgMTAgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZpZyBiL2RyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZp Zwo+IGluZGV4IDM5YWEyMWQwMWUwNS4uMTlmYzVmODg4M2UwIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvY2xvY2tzb3VyY2UvS2NvbmZpZwo+ICsrKyBiL2RyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZp Zwo+IEBAIC0zNTgsNiArMzU4LDE5IEBAIGNvbmZpZyBBUk1fR0xPQkFMX1RJTUVSCj4gIAloZWxw Cj4gIAkgIFRoaXMgb3B0aW9uIGVuYWJsZXMgc3VwcG9ydCBmb3IgdGhlIEFSTSBnbG9iYWwgdGlt ZXIgdW5pdC4KPiAgCj4gK2NvbmZpZyBBUk1fR1RfSU5JVElBTF9QUkVTQ0FMRVJfVkFMCj4gKwlp bnQgIkFSTSBnbG9iYWwgdGltZXIgaW5pdGlhbCBwcmVzY2FsZXIgdmFsdWUiCj4gKwlkZWZhdWx0 IDEKPiArCWRlcGVuZHMgb24gQVJNX0dMT0JBTF9USU1FUgo+ICsJaGVscAo+ICsJICBXaGVuIHRo ZSBBUk0gZ2xvYmFsIHRpbWVyIGluaXRpYWxpemVzLCBpdHMgY3VycmVudCByYXRlIGlzIGRlY2xh cmVkCj4gKwkgIHRvIHRoZSBrZXJuZWwgYW5kIG1haW50YWluZWQgZm9yZXZlci4gU2hvdWxkIGl0 J3MgcGFyZW50IGNsb2NrCj4gKwkgIGNoYW5nZSwgdGhlIGRyaXZlciB0cmllcyB0byBmaXggdGhl IHRpbWVyJ3MgaW50ZXJuYWwgcHJlc2NhbGVyLgo+ICsJICBPbiBzb21lIG1hY2hzIChpLmUuIFp5 bnEpIHRoZSBpbml0aWFsIHByZXNjYWxlciB2YWx1ZSB0aHVzIHBvc2VzCj4gKwkgIGJvdW5kcyBh Ym91dCBob3cgbXVjaCB0aGUgcGFyZW50IGNsb2NrIGlzIGFsbG93ZWQgdG8gZGVjcmVhc2Ugb3IK PiArCSAgaW5jcmVhc2Ugd3J0IHRoZSBpbml0aWFsIGNsb2NrIHZhbHVlLgo+ICsJICBUaGlzIGFm ZmVjdHMgQ1BVX0ZSRVEgbWF4IGRlbHRhIGZyb20gdGhlIGluaXRpYWwgZnJlcXVlbmN5Lgo+ICsK PiAgY29uZmlnIEFSTV9USU1FUl9TUDgwNAo+ICAJYm9vbCAiU3VwcG9ydCBmb3IgRHVhbCBUaW1l ciBTUDgwNCBtb2R1bGUiIGlmIENPTVBJTEVfVEVTVAo+ICAJZGVwZW5kcyBvbiBHRU5FUklDX1ND SEVEX0NMT0NLICYmIENMS0RFVl9MT09LVVAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbG9ja3Nv dXJjZS9hcm1fZ2xvYmFsX3RpbWVyLmMgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL2FybV9nbG9iYWxf dGltZXIuYwo+IGluZGV4IDg4YjJkMzhhN2E2MS4uNjBhODA0N2ZkMzJlIDEwMDY0NAo+IC0tLSBh L2RyaXZlcnMvY2xvY2tzb3VyY2UvYXJtX2dsb2JhbF90aW1lci5jCj4gKysrIGIvZHJpdmVycy9j bG9ja3NvdXJjZS9hcm1fZ2xvYmFsX3RpbWVyLmMKPiBAQCAtMzEsNiArMzEsMTAgQEAKPiAgI2Rl ZmluZSBHVF9DT05UUk9MX0NPTVBfRU5BQkxFCQlCSVQoMSkJLyogYmFua2VkICovCj4gICNkZWZp bmUgR1RfQ09OVFJPTF9JUlFfRU5BQkxFCQlCSVQoMikJLyogYmFua2VkICovCj4gICNkZWZpbmUg R1RfQ09OVFJPTF9BVVRPX0lOQwkJQklUKDMpCS8qIGJhbmtlZCAqLwo+ICsjZGVmaW5lIEdUX0NP TlRST0xfUFJFU0NBTEVSX1NISUZUICAgICAgOAo+ICsjZGVmaW5lIEdUX0NPTlRST0xfUFJFU0NB TEVSX01BWCAgICAgICAgMHhGCj4gKyNkZWZpbmUgR1RfQ09OVFJPTF9QUkVTQ0FMRVJfTUFTSyAg ICAgICAoR1RfQ09OVFJPTF9QUkVTQ0FMRVJfTUFYIDw8IFwKPiArCQkJCQkgR1RfQ09OVFJPTF9Q UkVTQ0FMRVJfU0hJRlQpCj4gIAo+ICAjZGVmaW5lIEdUX0lOVF9TVEFUVVMJMHgwYwo+ICAjZGVm aW5lIEdUX0lOVF9TVEFUVVNfRVZFTlRfRkxBRwlCSVQoMCkKPiBAQCAtMzksNiArNDMsNyBAQAo+ ICAjZGVmaW5lIEdUX0NPTVAxCTB4MTQKPiAgI2RlZmluZSBHVF9BVVRPX0lOQwkweDE4Cj4gIAo+ ICsjZGVmaW5lIE1BWF9GX0VSUiA1MAo+ICAvKgo+ICAgKiBXZSBhcmUgZXhwZWN0aW5nIHRvIGJl IGNsb2NrZWQgYnkgdGhlIEFSTSBwZXJpcGhlcmFsIGNsb2NrLgo+ICAgKgo+IEBAIC00Niw3ICs1 MSw4IEBACj4gICAqIHRoZSB1bml0cyBmb3IgYWxsIG9wZXJhdGlvbnMuCj4gICAqLwo+ICBzdGF0 aWMgdm9pZCBfX2lvbWVtICpndF9iYXNlOwo+IC1zdGF0aWMgdW5zaWduZWQgbG9uZyBndF9jbGtf cmF0ZTsKPiArc3RydWN0IG5vdGlmaWVyX2Jsb2NrIGd0X2Nsa19yYXRlX2NoYW5nZV9uYjsKPiAr c3RhdGljIHUzMiBndF9wc3ZfbmV3LCBndF9wc3ZfYmNrLCBndF90YXJnZXRfcmF0ZTsKPiAgc3Rh dGljIGludCBndF9wcGk7Cj4gIHN0YXRpYyBzdHJ1Y3QgY2xvY2tfZXZlbnRfZGV2aWNlIF9fcGVy Y3B1ICpndF9ldnQ7Cj4gIAo+IEBAIC05Niw3ICsxMDIsMTAgQEAgc3RhdGljIHZvaWQgZ3RfY29t cGFyZV9zZXQodW5zaWduZWQgbG9uZyBkZWx0YSwgaW50IHBlcmlvZGljKQo+ICAJdW5zaWduZWQg bG9uZyBjdHJsOwo+ICAKPiAgCWNvdW50ZXIgKz0gZGVsdGE7Cj4gLQljdHJsID0gR1RfQ09OVFJP TF9USU1FUl9FTkFCTEU7Cj4gKwljdHJsID0gcmVhZGwoZ3RfYmFzZSArIEdUX0NPTlRST0wpOwo+ ICsJY3RybCAmPSB+KEdUX0NPTlRST0xfQ09NUF9FTkFCTEUgfCBHVF9DT05UUk9MX0lSUV9FTkFC TEUgfAo+ICsJCSAgR1RfQ09OVFJPTF9BVVRPX0lOQyB8IEdUX0NPTlRST0xfQVVUT19JTkMpOwo+ ICsJY3RybCB8PSBHVF9DT05UUk9MX1RJTUVSX0VOQUJMRTsKPiAgCXdyaXRlbF9yZWxheGVkKGN0 cmwsIGd0X2Jhc2UgKyBHVF9DT05UUk9MKTsKPiAgCXdyaXRlbF9yZWxheGVkKGxvd2VyXzMyX2Jp dHMoY291bnRlciksIGd0X2Jhc2UgKyBHVF9DT01QMCk7Cj4gIAl3cml0ZWxfcmVsYXhlZCh1cHBl cl8zMl9iaXRzKGNvdW50ZXIpLCBndF9iYXNlICsgR1RfQ09NUDEpOwo+IEBAIC0xMjMsNyArMTMy LDcgQEAgc3RhdGljIGludCBndF9jbG9ja2V2ZW50X3NodXRkb3duKHN0cnVjdCBjbG9ja19ldmVu dF9kZXZpY2UgKmV2dCkKPiAgCj4gIHN0YXRpYyBpbnQgZ3RfY2xvY2tldmVudF9zZXRfcGVyaW9k aWMoc3RydWN0IGNsb2NrX2V2ZW50X2RldmljZSAqZXZ0KQo+ICB7Cj4gLQlndF9jb21wYXJlX3Nl dChESVZfUk9VTkRfQ0xPU0VTVChndF9jbGtfcmF0ZSwgSFopLCAxKTsKPiArCWd0X2NvbXBhcmVf c2V0KERJVl9ST1VORF9DTE9TRVNUKGd0X3RhcmdldF9yYXRlLCBIWiksIDEpOwo+ICAJcmV0dXJu IDA7Cj4gIH0KPiAgCj4gQEAgLTE3Nyw3ICsxODYsNyBAQCBzdGF0aWMgaW50IGd0X3N0YXJ0aW5n X2NwdSh1bnNpZ25lZCBpbnQgY3B1KQo+ICAJY2xrLT5jcHVtYXNrID0gY3B1bWFza19vZihjcHUp Owo+ICAJY2xrLT5yYXRpbmcgPSAzMDA7Cj4gIAljbGstPmlycSA9IGd0X3BwaTsKPiAtCWNsb2Nr ZXZlbnRzX2NvbmZpZ19hbmRfcmVnaXN0ZXIoY2xrLCBndF9jbGtfcmF0ZSwKPiArCWNsb2NrZXZl bnRzX2NvbmZpZ19hbmRfcmVnaXN0ZXIoY2xrLCBndF90YXJnZXRfcmF0ZSwKPiAgCQkJCQkxLCAw eGZmZmZmZmZmKTsKPiAgCWVuYWJsZV9wZXJjcHVfaXJxKGNsay0+aXJxLCBJUlFfVFlQRV9OT05F KTsKPiAgCXJldHVybiAwOwo+IEBAIC0yMzIsOSArMjQxLDI4IEBAIHN0YXRpYyBzdHJ1Y3QgZGVs YXlfdGltZXIgZ3RfZGVsYXlfdGltZXIgPSB7Cj4gIAkucmVhZF9jdXJyZW50X3RpbWVyID0gZ3Rf cmVhZF9sb25nLAo+ICB9Owo+ICAKPiArc3RhdGljIHZvaWQgZ3Rfd3JpdGVfcHJlc2ModTMyIHBz dikKPiArewo+ICsJdTMyIHJlZzsKPiArCj4gKwlyZWcgPSByZWFkbChndF9iYXNlICsgR1RfQ09O VFJPTCk7Cj4gKwlyZWcgJj0gfkdUX0NPTlRST0xfUFJFU0NBTEVSX01BU0s7Cj4gKwlyZWcgfD0g cHN2IDw8IEdUX0NPTlRST0xfUFJFU0NBTEVSX1NISUZUOwo+ICsJd3JpdGVsKHJlZywgZ3RfYmFz ZSArIEdUX0NPTlRST0wpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdTMyIGd0X3JlYWRfcHJlc2Modm9p ZCkKPiArewo+ICsJdTMyIHJlZzsKPiArCj4gKwlyZWcgPSByZWFkbChndF9iYXNlICsgR1RfQ09O VFJPTCk7Cj4gKwlyZWcgJj0gR1RfQ09OVFJPTF9QUkVTQ0FMRVJfTUFTSzsKPiArCXJldHVybiBy ZWcgPj4gR1RfQ09OVFJPTF9QUkVTQ0FMRVJfU0hJRlQ7Cj4gK30KPiArCj4gIHN0YXRpYyB2b2lk IF9faW5pdCBndF9kZWxheV90aW1lcl9pbml0KHZvaWQpCj4gIHsKPiAtCWd0X2RlbGF5X3RpbWVy LmZyZXEgPSBndF9jbGtfcmF0ZTsKPiArCWd0X2RlbGF5X3RpbWVyLmZyZXEgPSBndF90YXJnZXRf cmF0ZTsKPiAgCXJlZ2lzdGVyX2N1cnJlbnRfdGltZXJfZGVsYXkoJmd0X2RlbGF5X3RpbWVyKTsK PiAgfQo+ICAKPiBAQCAtMjQzLDE4ICsyNzEsODEgQEAgc3RhdGljIGludCBfX2luaXQgZ3RfY2xv Y2tzb3VyY2VfaW5pdCh2b2lkKQo+ICAJd3JpdGVsKDAsIGd0X2Jhc2UgKyBHVF9DT05UUk9MKTsK PiAgCXdyaXRlbCgwLCBndF9iYXNlICsgR1RfQ09VTlRFUjApOwo+ICAJd3JpdGVsKDAsIGd0X2Jh c2UgKyBHVF9DT1VOVEVSMSk7Cj4gLQkvKiBlbmFibGVzIHRpbWVyIG9uIGFsbCB0aGUgY29yZXMg Ki8KPiAtCXdyaXRlbChHVF9DT05UUk9MX1RJTUVSX0VOQUJMRSwgZ3RfYmFzZSArIEdUX0NPTlRS T0wpOwo+ICsJLyogc2V0IHByZXNjYWxlciBhbmQgZW5hYmxlIHRpbWVyIG9uIGFsbCB0aGUgY29y ZXMgKi8KPiArCXdyaXRlbCgoKENPTkZJR19BUk1fR1RfSU5JVElBTF9QUkVTQ0FMRVJfVkFMIC0g MSkgPDwKPiArCQlHVF9DT05UUk9MX1BSRVNDQUxFUl9TSElGVCkKPiArCSAgICAgICB8IEdUX0NP TlRST0xfVElNRVJfRU5BQkxFLCBndF9iYXNlICsgR1RfQ09OVFJPTCk7Cj4gIAo+ICAjaWZkZWYg Q09ORklHX0NMS1NSQ19BUk1fR0xPQkFMX1RJTUVSX1NDSEVEX0NMT0NLCj4gLQlzY2hlZF9jbG9j a19yZWdpc3RlcihndF9zY2hlZF9jbG9ja19yZWFkLCA2NCwgZ3RfY2xrX3JhdGUpOwo+ICsJc2No ZWRfY2xvY2tfcmVnaXN0ZXIoZ3Rfc2NoZWRfY2xvY2tfcmVhZCwgNjQsIGd0X3RhcmdldF9yYXRl KTsKPiAgI2VuZGlmCj4gLQlyZXR1cm4gY2xvY2tzb3VyY2VfcmVnaXN0ZXJfaHooJmd0X2Nsb2Nr c291cmNlLCBndF9jbGtfcmF0ZSk7Cj4gKwlyZXR1cm4gY2xvY2tzb3VyY2VfcmVnaXN0ZXJfaHoo Jmd0X2Nsb2Nrc291cmNlLCBndF90YXJnZXRfcmF0ZSk7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQg Z3RfY2xrX3JhdGVfY2hhbmdlX2NiKHN0cnVjdCBub3RpZmllcl9ibG9jayAqbmIsCj4gKwkJCQkg dW5zaWduZWQgbG9uZyBldmVudCwgdm9pZCAqZGF0YSkKPiArewo+ICsJc3RydWN0IGNsa19ub3Rp Zmllcl9kYXRhICpuZGF0YSA9IGRhdGE7Cj4gKwo+ICsJc3dpdGNoIChldmVudCkgewo+ICsJY2Fz ZSBQUkVfUkFURV9DSEFOR0U6Cj4gKwl7Cj4gKwkJaW50IHBzdjsKPiArCj4gKwkJcHN2ID0gRElW X1JPVU5EX0NMT1NFU1QobmRhdGEtPm5ld19yYXRlLAo+ICsJCQkJCWd0X3RhcmdldF9yYXRlKTsK PiArCj4gKwkJaWYgKGFicyhndF90YXJnZXRfcmF0ZSAtIChuZGF0YS0+bmV3X3JhdGUgLyBwc3Yp KSA+IE1BWF9GX0VSUikKPiArCQkJcmV0dXJuIE5PVElGWV9CQUQ7Cj4gKwo+ICsJCXBzdi0tOwo+ ICsKPiArCQkvKiBwcmVzY2FsZXIgd2l0aGluIGxlZ2FsIHJhbmdlPyAqLwo+ICsJCWlmIChwc3Yg PCAwIHx8IHBzdiA+IEdUX0NPTlRST0xfUFJFU0NBTEVSX01BWCkKPiArCQkJcmV0dXJuIE5PVElG WV9CQUQ7Cj4gKwo+ICsJCS8qCj4gKwkJICogc3RvcmUgdGltZXIgY2xvY2sgY3RybCByZWdpc3Rl ciBzbyB3ZSBjYW4gcmVzdG9yZSBpdCBpbiBjYXNlCj4gKwkJICogb2YgYW4gYWJvcnQuCj4gKwkJ ICovCj4gKwkJZ3RfcHN2X2JjayA9IGd0X3JlYWRfcHJlc2MoKTsKPiArCQlndF9wc3ZfbmV3ID0g cHN2Owo+ICsJCS8qIHNjYWxlIGRvd246IGFkanVzdCBkaXZpZGVyIGluIHBvc3QtY2hhbmdlIG5v dGlmaWNhdGlvbiAqLwo+ICsJCWlmIChuZGF0YS0+bmV3X3JhdGUgPCBuZGF0YS0+b2xkX3JhdGUp Cj4gKwkJCXJldHVybiBOT1RJRllfRE9ORTsKPiArCj4gKwkJLyogc2NhbGUgdXA6IGFkanVzdCBk aXZpZGVyIG5vdyAtIGJlZm9yZSBmcmVxdWVuY3kgY2hhbmdlICovCj4gKwkJZ3Rfd3JpdGVfcHJl c2MocHN2KTsKPiArCQlicmVhazsKPiArCX0KPiArCWNhc2UgUE9TVF9SQVRFX0NIQU5HRToKPiAr CQkvKiBzY2FsZSB1cDogcHJlLWNoYW5nZSBub3RpZmljYXRpb24gZGlkIHRoZSBhZGp1c3RtZW50 ICovCj4gKwkJaWYgKG5kYXRhLT5uZXdfcmF0ZSA+IG5kYXRhLT5vbGRfcmF0ZSkKPiArCQkJcmV0 dXJuIE5PVElGWV9PSzsKPiArCj4gKwkJLyogc2NhbGUgZG93bjogYWRqdXN0IGRpdmlkZXIgbm93 IC0gYWZ0ZXIgZnJlcXVlbmN5IGNoYW5nZSAqLwo+ICsJCWd0X3dyaXRlX3ByZXNjKGd0X3Bzdl9u ZXcpOwo+ICsJCWJyZWFrOwo+ICsKPiArCWNhc2UgQUJPUlRfUkFURV9DSEFOR0U6Cj4gKwkJLyog d2UgaGF2ZSB0byB1bmRvIHRoZSBhZGp1c3RtZW50IGluIGNhc2Ugd2Ugc2NhbGUgdXAgKi8KPiAr CQlpZiAobmRhdGEtPm5ld19yYXRlIDwgbmRhdGEtPm9sZF9yYXRlKQo+ICsJCQlyZXR1cm4gTk9U SUZZX09LOwo+ICsKPiArCQkvKiByZXN0b3JlIG9yaWdpbmFsIHJlZ2lzdGVyIHZhbHVlICovCj4g KwkJZ3Rfd3JpdGVfcHJlc2MoZ3RfcHN2X2Jjayk7Cj4gKwkJYnJlYWs7Cj4gKwlkZWZhdWx0Ogo+ ICsJCXJldHVybiBOT1RJRllfRE9ORTsKPiArCX0KPiArCj4gKwlyZXR1cm4gTk9USUZZX0RPTkU7 Cj4gIH0KPiAgCj4gIHN0YXRpYyBpbnQgX19pbml0IGdsb2JhbF90aW1lcl9vZl9yZWdpc3Rlcihz dHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQo+ICB7Cj4gIAlzdHJ1Y3QgY2xrICpndF9jbGs7Cj4gKwlz dGF0aWMgdW5zaWduZWQgbG9uZyBndF9jbGtfcmF0ZTsKPiAgCWludCBlcnIgPSAwOwo+ICAKPiAg CS8qCj4gQEAgLTI5MiwxMSArMzgzLDIwIEBAIHN0YXRpYyBpbnQgX19pbml0IGdsb2JhbF90aW1l cl9vZl9yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQo+ICAJfQo+ICAKPiAgCWd0X2Ns a19yYXRlID0gY2xrX2dldF9yYXRlKGd0X2Nsayk7Cj4gKwlndF90YXJnZXRfcmF0ZSA9IGd0X2Ns a19yYXRlIC8gQ09ORklHX0FSTV9HVF9JTklUSUFMX1BSRVNDQUxFUl9WQUw7Cj4gKwlndF9jbGtf cmF0ZV9jaGFuZ2VfbmIubm90aWZpZXJfY2FsbCA9Cj4gKwkJZ3RfY2xrX3JhdGVfY2hhbmdlX2Ni Owo+ICsJZXJyID0gY2xrX25vdGlmaWVyX3JlZ2lzdGVyKGd0X2NsaywgJmd0X2Nsa19yYXRlX2No YW5nZV9uYik7Cj4gKwlpZiAoZXJyKSB7Cj4gKwkJcHJfd2FybigiVW5hYmxlIHRvIHJlZ2lzdGVy IGNsb2NrIG5vdGlmaWVyXG4iKTsKPiArCQlnb3RvIG91dF9jbGs7Cj4gKwl9Cj4gKwo+ICAJZ3Rf ZXZ0ID0gYWxsb2NfcGVyY3B1KHN0cnVjdCBjbG9ja19ldmVudF9kZXZpY2UpOwo+ICAJaWYgKCFn dF9ldnQpIHsKPiAgCQlwcl93YXJuKCJnbG9iYWwtdGltZXI6IGNhbid0IGFsbG9jYXRlIG1lbW9y eVxuIik7Cj4gIAkJZXJyID0gLUVOT01FTTsKPiAtCQlnb3RvIG91dF9jbGs7Cj4gKwkJZ290byBv dXRfY2xrX25iOwo+ICAJfQo+ICAKPiAgCWVyciA9IHJlcXVlc3RfcGVyY3B1X2lycShndF9wcGks IGd0X2Nsb2NrZXZlbnRfaW50ZXJydXB0LAo+IEBAIC0zMjYsNiArNDI2LDggQEAgc3RhdGljIGlu dCBfX2luaXQgZ2xvYmFsX3RpbWVyX29mX3JlZ2lzdGVyKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAp Cj4gIAlmcmVlX3BlcmNwdV9pcnEoZ3RfcHBpLCBndF9ldnQpOwo+ICBvdXRfZnJlZToKPiAgCWZy ZWVfcGVyY3B1KGd0X2V2dCk7Cj4gK291dF9jbGtfbmI6Cj4gKwljbGtfbm90aWZpZXJfdW5yZWdp c3RlcihndF9jbGssICZndF9jbGtfcmF0ZV9jaGFuZ2VfbmIpOwo+ICBvdXRfY2xrOgo+ICAJY2xr X2Rpc2FibGVfdW5wcmVwYXJlKGd0X2Nsayk7Cj4gIG91dF91bm1hcDoKPiAKCgotLSAKPGh0dHA6 Ly93d3cubGluYXJvLm9yZy8+IExpbmFyby5vcmcg4pSCIE9wZW4gc291cmNlIHNvZnR3YXJlIGZv ciBBUk0gU29DcwoKRm9sbG93IExpbmFybzogIDxodHRwOi8vd3d3LmZhY2Vib29rLmNvbS9wYWdl cy9MaW5hcm8+IEZhY2Vib29rIHwKPGh0dHA6Ly90d2l0dGVyLmNvbS8jIS9saW5hcm9vcmc+IFR3 aXR0ZXIgfAo8aHR0cDovL3d3dy5saW5hcm8ub3JnL2xpbmFyby1ibG9nLz4gQmxvZwoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5l bCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=